6
Servaikaran street [email protected] Cell: +91-7708897566 in.linkedin.com/pub/saravana-kumar/68/53/619/ OBJECTIVE Intend to build a career to improve my skills for the development of the industry and also deliver the best for the role assigned to me. EDUCATION Course School / College Instituti on / Universit y Year of passin g Class % of Marks M.E in VLSI Design Karpagam Institutions Karpagam Institutio ns 2014 First class with distincti on 90.8 BE in Electronics and Communication Engineering(E CE) Maharaja Prithvi Engineering College, Avinashi. Anna University 2012 First class with distinct ion 91.5 Diploma in Electronics and Communication Engineering(E CE) VLB Janakiammal polytechnic College, Coimbatore DOTE 2009 First class with distinct ion 91.2 SSLC CBM Sakunthala Vidyalaya High School, Coimbatore State Board 2006 First class 87 TECHNICAL SKILLS and AREA of INTEREST SARAVANAKUMAR . A

SaravanaKumar_Resume

Embed Size (px)

Citation preview

Page 1: SaravanaKumar_Resume

16/5, Servaikaran streetSundakkamuthurCoimbatore-641010 Mail: [email protected] D.O.B:29/10/1990 Cell: +91-7708897566

in.linkedin.com/pub/saravana-kumar/68/53/619/

OBJECTIVE

Intend to build a career to improve my skills for the development of the industry and also deliver the best for the role assigned to me.

EDUCATION

Course School / College Institution / University

Year of passing Class % of

Marks

M.E in VLSI Design Karpagam Institutions

Karpagam

Institutions2014

First class with

distinction90.8

BE in Electronics and

Communication Engineering(ECE)

Maharaja Prithvi Engineering College,

Avinashi.

Anna

University2012

First class with

distinction91.5

Diploma in Electronics and Communication

Engineering(ECE)

VLB Janakiammal polytechnic College,

CoimbatoreDOTE 2009

First class with

distinction91.2

SSLCCBM Sakunthala Vidyalaya

High School, Coimbatore State Board 2006 First class 87

TECHNICAL SKILLS and AREA of INTEREST

Tools and Libraries FPGA- Spartan 3E(Program Dumping) Cadence( Virtuoso, Assura, Low

power design, Mixed analog and digital design ,GDS file Generation)

Xilinx-Simulation/Synthesis Microwind Tanner and Proteus

Languages VHDL VERILOG C,C++

Operating Systems Windows - 7,8, XP| Linux – Red hat

SARAVANAKUMAR . A

Page 2: SaravanaKumar_Resume

VALUE ADDED COURSE

Karpagam Academy of Higher Education Completed 2 year value added course on “Digital (Verilog&VHDL) and Analog

Design using Cadence Tools”(upto GDS file generation).

EXPERIENCE

NAME OF THE COLLEGE/INDUSTRY DESIGNATION JOINING

DATERELIEVING

DATE

EXPERIENCE

YEARS MONTHS DAYS

Gnanamani College of Technology Assistant

Professor 02-06-2014 - 01 11 -

TOTAL 01 11 -

WORKSHOPS AND SEMINARSKarpagam University

Hands on workshop on advanced digital logic system using cadence tools Feb 2016 Hands on workshop on analog and mixed signal IC design using cadence Oct 2013 Hands on workshop on low power VLSI design using cadence tools Mar 2013

ACHIEVEMENTS

Won Anna University Gold Medal for 40th rank in Anna University. Won 1st prize in Academic performer at Maharaja Prithvi Engineering College. Won 1st prize in Academic performer for 1st, 3rd,4th and 5th semesters at VLB

Janakiammal Polytechnic College. Best Outgoing Student in the year of 2008-2009 at VLB Janakiammal Polytechnic

College. Achieved 100% attendance for 3rd and 5th semester at VLB Janakiammal

Polytechnic College.ACADEMIC PROJECTS

Efficient Design of Integrated Power and Clock Distribution Network Jun2013-Ap2014 To reduce the power consumption of power and clock of combinational and

sequential circuits using cadence toolSmart Card and Securable Information System for Buses Jun 2012-Apr 2013

To reduce work difficulty of driver and conductor and providing security information for buses

Ultrasonic Based Pneumatic System for Vehicles Dec 2008-Apr 2009 Providing automatic speed controlling system to vehicles( cars and buses ) based on

distance calculation

JOURNALS

Published journals on the topic of

Page 3: SaravanaKumar_Resume

[1] “ Energy Recycling for Large Chip Design using Low Power Switching Converters” in International Journal for Advance Research in Engineering and Technology (IJARET 02-02-09, ISSN 2320-6802,VOL1,ISSUE1 JAN 2014).

[2] “An Improved Shannon Adder Based Low Power Boughwooley Multiplier in Switching Activities of Partial Products” in International Journal of Innovations in Scientific and Engineering Research (IJISER ID-JAN103,VOL2,ISSUE2,FEB 2014)

[3] ” Efficient Design of Power and Clock Network for Large Chip design using Energy Recycling Technique” in International Journal for Research in Applied Science and Engineering Technology (IJRASET, ISSN 2321-9653,VOL2,ISSUE3 MAR 2014)

[4] “Efficient Design of New Novel Full Adder in Gate Diffusion Input Techniques” in International Journal of Modern Electronics and Communication Engineering (IJMECE,MAR 2014)

CONFERENCE

Presented International Conference in Adithya Institute of Technology on the topic of “ Integrated Power and Clock Network Design for Large Chip Design”

PAPER PRESENTATION ACHIEVEMENTS

Won 1st prize in national level technical symposium on Guidance systems for blind at KGISL Institute of Technology Mar 2011

Won 3rd prize in state level technical symposium on Guidance systems for blind at KTVR Knowledge Park for Engineering and Technology Mar 2011

Won 2nd prize in Sliding Talents on Guidance systems for blind at Maharaja Prithvi Engineering College Feb 2011

CERTIFICATION

Diploma in Computer Application ( DCA ) in CSC Aug 2006-Feb 2007 Programming and application in personal computers in Canada India institutional

cooperation project director of technical education Feb 2007TRAININGS Vasantha Advanced Systems May 2008

undergone training on assembling components in an electronic board as per circuit Crisp Systems Nov 2008 Undergone training on about ultrasonic, DC motor with power supply circuit design VOLUNTEER EXPERIENCE

Participated in NSS ( National Service Scheme )on the theme of healthy youth for India Dec-2006

Participated in HIV/ AIDS awareness programming organized by Red Ribbon Club with TN State Mar-2008

HOBBIES

| Solving Sudoku | ChessDECLARTION

I hereby declare that the above details are true to the best of my knowledge. I also declare to serve the firm with great ability and sincerity.

Place : (SARAVANAKUMAR.A)

Page 4: SaravanaKumar_Resume

Date : Signature of the Applicant References1) G.Surya B.ECell.no: +91 7708164815Solution Developer (Cisco)Tata Consultancy Services (TCS)[email protected] 2) P. Ravi Kumar (HR)Cell.no: +91 9566626082.Themesoft [email protected]