SiP/3D Device Test Challenges using Ever Changing JTAG …koreatest.or.kr/sub08/sub08_data/정성수.pdf · 2013-10-24 · enhanced test and debug standard that meets the demands

© 2013 Hanyang University ERICA, All rights reserved Page 1 October, 2013

SiP/3D Device Test

Challenges using Ever

Changing JTAG Standards

(끝없이 변하는 JTAG 표준과 이를 이용한 SiP/3D 소자 테스트의 도전)

Sung Chung, Research Professor


Overview of Current Standards

Standards in SiP/3D Test Perspective

Overview of SiP/3D Test Challenges

Disturbing Thought / New Development

Presentation Summary

Q and A

Selective References

Presentation Outline







Q and A




The Beginning 1st JTAG Meeting, 17 Sep., 1988

Photo Courtesy of “Boundary Scan Tutorial by ”Dr. RG “Ben” Bennetts


Test Access Port and Boundary-Scan Architecture Called Joint Test Action Group (JTAG)

Referred to as DCJTAG to distinguish from ACJTAG (1149.6)

1149.1-1990: 1st release

1149.1a-1993: added Boundary Scan Description

Language (BSDL) 1149.1b-1994: 1st major clean up and clarification

1149.1c-2001: add provisions for DFT circuit

1149.1-2013 Active Standard Add provisions for dynamic test capabilities with new instructions and BSDL files

P1149.1.1 Active Working Group It is called TDRI or JTDRI

The Original JTAG IEEE Std 1149.1

IEEE P1149.1.1


Three Instructions for initializing programmable IP connected to I/O pins

INIT_SETUP INIT_SETUP_CLAMP INIT_RUN

Standardized on-chip per domain system reset IC_RESET

Unique per die identifier ECIDCODE

Standardizes a method to hold and isolate I/O pins during in-situ test of an IC

CLAMP_HOLD CLAMP_RELEASE TMP_STATUS

Other updates No more BC_6 Support excludable register segments All (except TAP) pins may have additional observe-only cells Defined interface for design-specific TDR Power domain control

New to 1149.1-2013 IEEE Std 1149.1

IEEE 1149.1-2013 New IC level Instructions


1149.2: Withdrawn Extended Digital Serial Test Bus Subset

Withdrawn during 1997, became part of 1149.1

1149.3: Withdrawn System Test Bus

Withdrawn known

Std. 1149.4-1999 AJTAG (Analog JTAG)

Mixed Signal Test Bus

1999 standard superseded by 2010

1149.4-2010 Active Standard

1149.5-1995: Module Test and MTM Protocol VME backplane and system and it’s a withdrawn, inactive standard

Std. 1149.6-2003 ACJTAG (AC JTAG) Advanced I/O digital network test, known as ACJTAG

IEEE Std 1149.4 IEEE Std 1149.6

IEEE Std 1149.5

Voltage-current measurement method principle with variable sense resistor

Jari Hannu et al., “Current State of the Mixed-Signal Test Bus 1149.4”, J. of Electron Test (2012) 28:857–863, DOI 10.1007/s10836-012-5339-7


Std. 1149.7-2009 cJTAG (Compact JTAG) (or aJTAG) Reduced-pin and Enhanced-functionality Test Access Port and

Boundary Scan Architecture

Purpose: cJTAG is compatible with IEEE Std. 1149.1 to provide an

enhanced test and debug standard that meets the demands of

modern systems. One unique feature is the reduced pin count interface

for the TAP; it uses a two-wire interface, since it is compatible with

1149.1, it also permits four- or five-wire implementation as well.

cJTAG IEEE Std 1149.7

Benefits. cJTAG enables easier

implementation of JTAG for SoC, SiP

and PoP. It supports multi-die SiPs or

PoPs and a star configuration of TAP.

A key advantage is that it can be

implemented on TSV to link each die

through a via that connects the

1149.7 interface on each die to one

another.

IEEE Std 1149.7 TAP Capability Classes


Std. 1149.8.1-2012 : TJTAG (A Toggle JTAG) Boundary-Scan-Based Stimulus of Interconnections to Passive

and/or Active Components Purpose: To regain test coverage on connectors and devices

connected to boundary scan devices without the need for test

points, 1149.8.1 uses a combination of boundary scan devices as signal driver and a noncontact signal sensing or vectorless

sensor plate controlled by ICT to detect opens and shorts on

connectors, sockets and semiconductor device pins.

Benefit: There is already a working solution currently implemented in some ICTs using a noncontact signal sensing or

vectorless sensor plate that detects open/shorted pins on non-

boundary scan devices and connectors connected to boundary scan devices.

IEEE Std 1149.8.1 A Toggle


IEEE Std 1450.6

IEEE Std 1450.3

Std. 1450-1999 STIL Standard Test Interface Language (STIL)

STIL is a common test data description

language that can be used in various

environments of semiconductor testing such as

design, simulation, ATE testing and failure

analysis.

1450.1-2005 Semicon Design Environ

1450.2-2002 DC Level Spec

1450.3-2007 Target Tester Spec

P1450.4 Test Flow Spec

P1450.5 Dropped, plan to restart after P1450.4

1450.6-2005 Core Test Language

P1450.6-1 CTL for Memory Model

P1450.6-2 CTL for Scan Compression

P1450.7 Analog Mixed Signal

P1450.8 Design Information

STIL

IEEE Std 1450.2

IEEE Std 1450.1

IEEE P1450.8

IEEE P1450.7

IEEE P1450.6-2

IEEE P1450.6-1

IEEE P1450.5

IEEE P1450.4

IEEE Std 1450


Std. 1500-2005 Embedded Core Test

Defines a mechanism for the test of cores within a system on chip, including a wrapper hardware architecture. It also uses a core test language (CTL, IEEE Std. 1450.6-2005) to facilitate communication between core designers and integrators.

Core Test IEEE Std 1500

Photo Courtesy of Mentor Graphics

Source: ASSET InterTech, Inc. All rights reserved

Defines standard components and general wrapper architecture, including wrapper parallel input and output ports, core functional inputs and outputs, wrapper serial input, and serial output for test


Std. 1532 ISC In-System Configuration of Programmable

Devices

1532.1-2000 Superseded

1532.1-2001 Superseded

1532.1-2002 Active

The IEEE Std. 1532 was adopted in 2000 and

updated in 2001 and 2002 to include a

programming data file format and a method for

implementing adaptive programming

algorithms.

ISC IEEE Std 1532


Std. 1581-2011 mJTAG (Memory) Static Component Interconnection Test Protocol and Architecture Purpose: Low-cost method for testing the interconnection of discrete, complex memory ICs where additional pins for testing are not available and JTAG is not feasible. Benefit: Improve interconnect test for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs.

Limited to behavioral description of implementation, does not include the technical design of the test logic or test mode control circuitry Simple test logic implementation for memory devices (and possibly other complex, slave-type components) No extra pins are required Not relying on complex memory access cycles Fast test execution, small test vector set Usable with any access methodology (JTAG, functional, ICT)

mJTAG IEEE Std 1581


P1687 iJTAG (Instrument): in vallot process.. Standard methodology for access to embedded test and

debug features through IEEE Std. 1149.1

This Standard provides a method of adding additional lines

and functionality to the JTAG TAP to enable far greater

levels of internal testing to be achieved using internal instrumentation

iJTAG IEEE P1687

1. Integrated into existing ICT

2. ICT system > P1687 test solution

3. P1687 test solution > functional test

4. Integrated into existing functional test

Key Differences between JTAG and iJTAG

JTAG iJTAG

Control of internal IP Ad hoc method, vendor specific

Standard protocol

External interface to internal instrument and 3rd-party IP

Need information from instrument vendor

Plug-and-play and vendor independent

Coolness Old and boring Fancy and New

Instrument access through hierarchical

logic structure

Must be manually defined of the JTAG

interface

Automated retargeting from TAP to instrument

through logic hierarchy

Register size Fixed per instruction Flexible


The control data for the SIB is transported on the same wire as test data Control data is transferred to the status register when the JTAG state machine does ”apply and capture” “CUC”: Apply Capture Update Cycle: 5 clock cycles in the FSM

Analysis of IEEE P1687 network

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, “Test Time Analysis

for IEEE P1687”, IEEE 19th Asian Test Symposium (ATS 2010), Shanghai, China, Dec. 2010


3D Test IEEE P1838

P1838 3D Device Test & DFT Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

Scope: The proposed standard is a ‘die-centric’ standard; it applies to a die that is pre-destined to be part of a multi-die stack and such a die can be compliant (or not compliant) to the standard Two Standardized Components

3D Test Wrapper hardware per die Description + description language

Leverage existing DFT wherever Applicable/Appropriate Test access ports: utilize IEEE Std. 1149.x On-die design-for-test: utilize IEEE Std. 1500 On-die design-for-debug: Utilize IEEE P1687

Web Page http://grouper.ieee.org/groups/3Dtest/

http://grouper.ieee.org/groups/3Dtest/



SJTAG (System JTAG) http://www.dft.co.uk/SJTAG/ SJTAG deals with JTAG architectures and operations in a multi-board environment Typical SJTAG operations:

Another JTAG…. SJTAG

Conventional (single board) interconnect test In-system programming System interconnect test using chain configuration devices (bridges, scan routers/multiplexors) Simple iJTAG operations (single board, no hierarchy) Complex iJTAG operations (through system and device hierarchies)

http://www.dft.co.uk/SJTAG/


IEEE-ISTO 5001TM Forum The Nexus standard defines classes of standard on chip

features, auxiliary pins, transfer protocol, connectors and

API for communication between an embedded

instrumentation and a host computer

IEEE-ISTO 5001TM = IEEE-ISTO 5001

IEEE-ISTO 5001TM-1999 Superseded

IEEE-ISTO 5001TM-2003 Active

Spec Updates are ongoing SerDes IO for debug – Aurora protocol Convergence with IEEE Std. 1149.7 cJTAG and P1867 iJTAG

Debug Standards IEEE-ISTO 5001

Nexus 5001


MIPS® EJTAG EJTAG (Extended JTAG) is a hardware/software subsystem that provides comprehensive debugging and performance tuning capabilities to MIPS® microprocessors and to system-on-a-chip components having MIPS® processor cores. The MIPS® architecture has historically provided a set of primitives for debugging software, which includes

A breakpoint instruction A set of trap instructions Dual optional watch registers An optional TLB-based MMU

MIPS Debug EJTAG

Source: MIPS Technologies, Inc. All rights reserved







Q and A




IEEE 1149.7

P1838 uses the largest number of standards to solve 3D test challenges

Relationship between All Standards

IEEE 1149.1

IEEE 1581

IEEE P1687

Nexus 5001

IEEE 1532

IEEE 1500

EJTAG

SJTAG

IEEE P1838


IEEE P1838

IEEE P1687 IEEE Std 1581

IEEE Std 1532

IEEE Std 1500

IEEE Std 1450

IEEE Std 1450.6

IEEE Std 1450.3

IEEE Std 1450.2

IEEE Std 1450.1

IEEE P1450.8

IEEE P1450.7

IEEE P1450.6-2

IEEE P1450.6-1

IEEE P1450.5

IEEE P1450.4

IEEE Std 1149.7

IEEE Std 1149.8.1

IEEE Std 1149.4

IEEE Std 1149.6

IEEE Std 1149.1

IEEE P1149.1.1

SJTAG

IEEE-ISTO 5001 Nexus 5001

EJTAG

Active Standards Work in progress

Active Standards

Most likely to be used

Less likely to be used

For SiP and 3D Test

=

My Best Picks for SiP/3D IC Test







Q and A




Test Delivery and DFT Hierarchy

Core-level DFT BIST, scan chain, scan data compression

Die-level DFT Wrapper and test-access mechanism (TAM)

SIC- level DFT Wrapper at die boundary KGD: extra probe pads KGS: Known Good Stack Test Elevators Signal Switches Board-level DFT (JTAG)


3D Testing Testing at individual die level

Determine Known Good Die (KGD) for stacking Testing at 3D stack level

Final stack test Individual die test options

No Test Built-In-Self-Test (BIST) and Built-Out-Self-Test (BOST) Reduced-Pad-Count-Test (RPCT)

3D Testing assumptions Final, Post-stacking Test performed in ALL cases Test Bottom die

Avoid stacking cost if die is faulty Scan chains in place on all stacked dice

To be utilized in the Final, Post-stacking Test New issues and requirements

IP and Test Security Near-field wireless communication

Test is Considered “3D Challenge No. 1”


Testing Differences

Defect Mode

Functional Test

DFT / BIST

EDA

Data Mining

Probe Access

Point

Wafer Handling

KDG / PGD

Burn In

Supply Chain

Same Enhance New Don’t Need Portion

Items SoC POP/PIP SIP 3D SIC 3D IC

Adopted from Wendy Chen, “3DS IC Test Cost Reduction Challenges”


1149.1, 1149.4, 1149.6, 1149.7 1149.8.1, 1500, 1581 P1687, P1838 Analog test bus, Loopback Parametric Test BIST and BOST Functional Test, At-Speed Test Debug, Diagnosis, ICE

Danger is to try to use all tricks even

unapproved Standards

Example 3D Test DFT Trends

Stephen Sunter, “Mixed-signal testing, DFT, and BIST: Trends and Principles,” June 2010, Mentor Graphics

http://www.techdesignforums.com/practice/files/2012/11/tdf-nov12-ment-test-fig1lrg.jpg


DFT and DFD are key for success

Still some test issues unresolved

Example Test Coverage Summary

Stéphane GUILHOT,”DFT challenges and results for a 3D-IC including a WideIO memory,” ST Ericsson 2013.







Q and A




What about Non-Contact Probing

Source: Marinissen et. al., DATE ‘09

Near field inductive coupling is the most powerful

technique for stacked IC’s Scalable solution from wafer, die, and to stack

Can solve KGD, PGD and KGS

BOST and other off-chip test and analysis support

Contactless I/O

Proximity I/O (Sun Micro Systems) and Scaimetrics: high-speed, low-power data communication (wireless test access port)

Different Principles & Approaches Non contact coupling

Capacitive / Inductive coupled high speed data communication Near field and Far field e.g., DFT Build-in transmitters with read-out electronics in the probe card

Laser direct testing

But works only for passive networks


Advantages of inductive near field coupling approaches Contactless & low chip to chip distances

High interconnect RF and data speeds

Many parallel links

No probe force (except power)

Low delay, area, power, higher speeds, more tolerant

No ESD protection required

Still High reliability (compared to the TSV challenges)

Standard CMOS process less expensive then TSV process

Limitations of inductive near field coupling approaches Dimensions of antenna >~200μm circumference

Limited pitch e.g., 30μm with 20μm x 90μm antenna

Controllable cross talk DC power must provided to DUT by additional electrical contact

Summary of Non Contact Data

Communication

Thomas Thärigen, Stojan Kanev, “3D IC Test Challenges and Probing Concepts,” DATE'10 Workshop on "3D Integration" Mar. 12, 2010, Dresden, Germany







Q and A




Market gives Fair Test to Select The One to Survive!

Ca

rto

on

fro

m R

ich

Ric

e,

“K

GD

an

d 2

.5D

& 3

D IC

Ass

em

bly

-

Bu

ild

ing

a P

ath

to

Su

cc

ess

,” A

SE G

rou

p, N

ov 1

5,

2012

Are you ready?


Thank you!

Q and A


IEEEE 3D Test Working Group (3DF-WG) - http://grouper.ieee.org/groups/3Dtest/

Sematech WiKi 3D Standards - http://wiki.sematech.org/3D-Standards Kenneth P. Parker, “3D-IC Defect Investigation,” provided report for the IEEE P1838 Defect Tiger Team, July 5, 2012 Tsutomu Takeya et al., “A 12-Gb/s Non-Contact Interface With Coupled Transmission

Lines.” IEEE Journal of Solid-state Circuit, Vol. 48, No. 3, Mar. 2013, pp. 790 – 800

Hsien-Hsin S. Lee and Krishnendu Chakrabarty, “Test Challenges for 3D Integrated Circuits,” IEEE Desgn & Test of Computer, Sep./Oct. 2009., vol. 26 no. 5, pp. 26-35

Nauman Khan, Soha Hassoun,”Designing TSVs for 3D Integrated Circuits,” Springer, ISBN

978-1-4614-5507-3, 2013 Sai-Wang Tam and Eran Socher, et al.,“RF-Interconnect for Future Network-On-Chip,” Springer “Low Power Networks-on-Chip,” 2011, pp 255-280 Chapter 9, IEEE P1687 – IJTAG, N. Stollon, “On-Chip Instrumentation: Design and Debug for

Systems on Chip,” 2011, DOI 10.1007/978-1-4419-7563-8_9, Springer

Selected References


http://wiki.sematech.org/3D-Standards



Documents

SiP/3D Device Test Challenges using Ever Changing JTAG …koreatest.or.kr/sub08/sub08_data/정성수.pdf · 2013-10-24 · enhanced test and debug standard that meets the demands