STRJ WG3 Front End Processes）活動報告semicon.jeita.or.jp/STRJ/STRJ/2009/15_FEP.pdf · Work in Progress - Do not publish STRJ WS: March 5, 2010, WG3 FEP 1um 100nm 0.1nm 10um

Work in Progress - Do not publish STRJ WS: March 5, 2010, WG3 FEP

北島,丹羽,水島,若林,堀井,奈良,後藤,大路,永田,酒井,クロス,中嶋,大形,渡辺,三木

STRJ_WG3（Front End Processes）活動報告-ＦＥＰ技術動向とＩＴＲＳ２００９改訂 -

FEP WG

内容

1. FEP_WGのスコープ2. ITRS2009の章構成（大きく変更）

3. スケーリングトレンド4. Parallel Pathの新規記載内容について5. Potential Solutions概観6. ITRS2009の主な変更点7. ITRS2010updateに向けての検討項目


用語集

ALD: Atomic Layer DepositionA/R: Aspect RatioCMP: Chemical Mechanical PolishCT-Flash: Charge Trapping Flash, FG-Flash: Floating Gate FlashDWF: Dual Work FunctionEOT: Equivalent Oxide ThicknessFDSOI: Fully Depleted Silicon On InsulatorHP/LOP/LSTP: High Performance/Low Operating Power/Low Stand-by PowerLA/FLA: Laser Anneal / Flash Lamp AnnealLg: Gate LengthMGHK: Metal Gate (Electrode) / High-k (Dielectric)MRAM: Magnetic Random Access MemoryPCM: Phase Change Memory (PCRAMとも言う)SDE: Source Drain ExtensionUTBSOI: Ultra Thin Body SOI


FrontEndProcess Scope


ITRS2009

Logic Devices [HP, LOP, LSTP]DRAM DevicesFlash DevicesPCM DevicesFeRAM Devices

Starting MaterialsSurface PreparationThermal/Thin Films/DopingEtchCMP

ITRS2007

Starting MaterialsSurface PreparationThermal/Thin Films/DopingEtch

Stacked DRAMTrench DRAMFlashPCMFeRAM

DEVICEMETRICS

PROCESSMETRICS

注：MRAM（PIDSに記載有）は記載を見合わせている

NEWNEW

NEW

NEW

DELETE

FEP 章構成


DEVICE METRICSLogic Devices [HP, LOP, LSTP]: Prashant Majhi (US)DRAM Devices: Deoksin Kil (KR)Flash Devices: Mauro Alessandri (EU)PCM Devices: Mauro Alessandri (EU)FeRAM Devices: Yoshimasa Horii (JP)

PROCESS METRICSStarting Materials: Mike Walden (US), Mike Goldstein (US)Surface Preparation: Joel Barnett (US)Thermal/Thin Films/Doping: Prashant Majhi (US)Etch: Tom Lii (US)CMP: Darryl Peters (US)

2009 ITRS FEP Sub-TWG LeadershipCo-Charis: Jeff Butterbaugh (FSI International)

Raj Jammy (SEMATECH/IBM)NEW

NEWNEW

NEW

NEW


1um

100nm

0.1nm

10um

1nm

10nm

1995 2000 2005 2010 2015年

traditional scaling

½ PichLg

EOT

P.Packan, IEDM2007Short Course

G.Timp et al.,IEDM1998

equivalent scaling

ＣＭＯＳスケーリングトレンド


1um

100nm

0.1nm

10um

1nm

10nm

1995 2000 2005 2010 2015年

traditional scaling equivalent scaling

多電源化

SOI

300mmFeRAM PCMMRAM

MGHK歪

HK容量

Salicide STI

Cu配線

SDE枚葉

大電流

LA/FLAALD

3DFET

½ Pich

Lg

EOT

CT-Flash

Dual Silicide

FDSOIMulti-G

450mm

3Dメモリ

FEP関連 CMOS/Memory導入技術


Timing of CMOS Innovations


Bulkor

SOI

Multi Gate（Si-FinFET)

Nanowire・表面に高移動度材料・Wire全体が高移動度材料

FinFET・表面に高移動度材料・Fin全体が高移動度材料

Parallel Path

Work in Progress - Do not publish STRJ WS: March 5, 2010, WG3 FEP注：複数年に亘るのは複数の技術がSolutionとして存在している（詳細省略）

Potential Solutions(ITRS2009)2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

planar bulkFDSOIMultiple GateStarting Materials 450mm 量産

平坦度（新技術）量産HK/new-ch界面制御量産微小粒子除去(No damage)レジスト除去（No Mat. Loss)高A/R構造の洗浄・リンス・乾燥New High-k(k＞30）量産HK/new-ch. 量産Low-k spacer 量産プロファイル制御：Multi Gate 量産USJドーピングmsec(FLA, LA) 量産thermalアニール量産DWF コンタクト量産新プラズマ源量産MG, HKエッチング量産スクラッチ無しのSTICMP 量産Ge-ch.(pFET) 量産ⅢⅤ-ch(nFET) 量産DRAM 上部電極（Ru系, Ir系）量産

High-k（TiO2, STO, BST）量産下部電極（SrRuO2) 量産

FG: SiON/High-k stack 量産FG:Metal電極量産

量産

量産量産

量産

2018年以

降は

高移

動度

チャネル

とDRAM電極

だけ


ITRS2009の主な変更点

Logic deviceのテーブルを追加（HP, LOP, LSTP）

Trench DRAMのテーブルを削除

DRAM：容量膜の誘電率（要求値）が大きく減少

Charge-trapping Flashのテーブルが追加された

FeRAM：技術変化が4年毎になるテーブルに変更

Starting Material：450mmのSカーブがPilot line／量産の2本立

Thermal Thin Film：Lgの3～4年（ITRS2007比）先延ばし

⇒EOT, Xjなどの要求値も緩和

Doping：Si/Silicideコンタクト抵抗のColor Code見直し

CMPのテーブルを追加


Logic devices

・ New Table Structure

・ New scaling approach coordinated with PIDS- Individual tables to focus on device metrics for HP, LOP, and LSTP

- reset CV/I benchmark in 2009- CV/I improvement factor changed to 13% per year

・ New Model Assumption and New Rows; Parasitic Resistance Constraint

・ LOP and LSTP still need to be addressed・ Introduction of FDSOI and Multigate still under consideration


DRAM


Charge trapping FLASH

Year of Production 2012 2013 2014 2015 2016 2017 2018 2019NANd Flash technology node - F(nm) 25 22 20 19 18 16 14 13

Tunnel Dielectrics EOT thickness (nm)Tunnel Dielectric MaterialTunnel Dielectric max leakage current density athighest write/erase voltage (A/cm2)Erase/program time degradation t max /t 0 at constant VCharge trap layer trap densitu (cm-3) >1e19 >8e19 >8e19 >8e19 >1e20 >1e20 >1e20 >1e20Trapping Energe Level (eV)Charge trap layer minimum band offset vstunnel/blocking dielectric conduction band (eV)Charge trap layer dielectric constant >7 7-10 7-10 7-10 >10 >10 >10 >10Charge trap layer material eSiNBlocking dielectric thickness EOT (nm) 6-8 6-8 6 6 6 6 5 5Blocking Dielectric max leakage current density athighest write/erase voltage (A/cm2)Blocking dielectric materialGate material working function (eV)Gate Material

3-4

metal>5

>1

>1.5

eSiN/high k high k

<5e-16

Al2O3 Al2O3/higher k higher k

SiO2 or BE

<5e-16

<2

• Floating Gate Flash no longer scaled beyond 16nm node• New Table added for the Charge-Trapping Flash added

BE: Barrier Engineered, eSiN: engineered SiN


• Table parameters, general trend are unchanged• Trends in 4-year blocks

FeRAM

Year of Production 2009-2012 2013-2016 2017-2020 2021-2024FeRAM technology – F (nm)[A] 180 130 90 65FeRAM cell size – area factor ain multiples of F2 [B]FeRAM cell size ( µm2) [C] 0.713 0.27 0.113 0.051FeRAM cell structure [D] 1T1C 1T1C 1T1C 1T1CFeRAM capacitor structure [E] stack stack 3D 3DFeRAM capacitor footprint (µm2) [F] 0.33 0.106 0.041 0.016FeRAM capacitor active area (µm2) [G] 0.33 0.106 0.1 0.069FeRAM cap active area/footprint ratio 1 1 2.46 4.25Ferro capacitor voltage (V) [I] 1.5 1.2 1 0.7FeRAM minimum switching charge density (µC/cm2) [J] 13.5 34 30 30FeRAM endurance (read/write cycles) [K] 1.00E+14 1.00E+15 >1.0E16 >1.0E16FeRAM nonvolatile data retention(years) [L] 10 Years 10 Years 10 Years 10 Years

12141622


450mm Production Ramp-up Model


Year of Production 2009 2010 2011 2012 2013 2014 20152007 20 18 16 14 13 11 102008 27 24 22 20 18 17 152009 29 27 24 22 20 18 172007 0.75 0.65 0.55 0.52008 1 0.95 0.88 0.75 0.65 0.6 0.532009 1 0.95 0.88 0.75 0.65 0.6 0.542007 0.7 0.6 0.55 0.5 0.5 0.52008 0.7 0.65 0.582009 0.7 0.68 0.62007 0.8 0.7 0.6 0.6 0.62008 0.772009 0.77

MPU Physical Gate Length (nm)

EOT for bulk MPU/ASIC

EOT for FDSOI MPU/ASIC

EOT for multi-gate MPU/ASIC

Thermal/Thin Film

ゲート長の変遷（ITRS2007→2009）MPU/ASIC, Metal Gate

HPのゲート長は3～4年後倒し ⇒ EOTに対する要求も緩和


Intel 1st and 2nd generation metal gate/high-k

45nm(2007)Lg=35nm

EOT=1.0nm

32nm(2009)Lg=30nm

EOT=0.9nm

Packan et al., IEDM2009Mistry et al., IEDM2007


CMP

• New Table for 2009 ITRS FEP Chapter• Initially addressing Allowable Scratches and Uniformity• Need to clean up colorization

Year of Production 2009 2010 2011 2012 2013 2014 2015 2016DRAM ½ Pitch (nm) (contacted) 52 45 40 36 32 28 25 22.5MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) 54 45 38 32 27 24 21 18.9MPU Physical Gate Length (nm) 29 27 24 22 20 18 17 15.3Wafer diameter (mm) 300 300 300 300 300 450 450 450Wafer edge exclusion (mm) 2 2 2 2 2 2 2 2

Critical scratch length, sc(nm) [F] 25.8 22.5 20.0 17.9 15.9 14.5 12.6 11.3Critical scratch count, Sp(#/wafer) [F] 40.1 40.1 40.1 40.1 40.1 166 105 105

CMP total uniformity (3σ ) for removal (%) [F] 8 8 8 8 8 8 8 8CMP uniformity (3σ ) within wafer (%) [F] 6 6 6 6 6 6 6 6

Scratches

Uniformity


Logic Table：PIDSと不整合, Noteとの不整合の修正LOP/LSTP Tableの統合DRAM Table：Cell area factorがPIDSと不整合Starting Materials：Edge Exclusion 再見直し

FDSOI用の基板仕様Doping：PIDSの寄生抵抗値との不整合、モデルの見直し

ITRS2010 以降に対して検討が必要な項目

消費電力のロードマップⅢV材料の扱い3D配線新材料・新構造に関するDefect BudgetWaste Metrics

Cross Cut

Documents

STRJ WG3 Front End Processes）活動報告semicon.jeita.or.jp/STRJ/STRJ/2009/15_FEP.pdf · Work in Progress - Do not publish STRJ WS: March 5, 2010, WG3 FEP 1um 100nm 0.1nm 10um