Temperature- Power Consumption Relationship and Hot-spot Migration for FPGA- based System

Green Workshop – 06 November 2009IETR - INSTITUT D’ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNESUne grande école d’ingénieurs au cœur des sciences de l’information, de l’énergie et des systèmes 1Xun ZHANG, Séminaire 18.nov. 2010

Temperature-Power Consumption Relationship and Hot-spot Migration

forFPGA-based System

Xun Zhang, Pierre LeraySUPELEC/IETR, Rennes, France

Signal, Communication and Embedded Electronics Team

supported by Motorola Foundation


Outline

1. Context & Motivation2. Power consumption & temperature 3. Die temperature measurement 4. Architectural changes5. Future Works


Outline



3% of the world-wide energy is consumed by the ICT infrastructure which causes about 2% of the world-wide CO2 emissions [1]

ICT carbon footprint is comparable to the world-wide CO2 emissions by airplanes or one quarter of the world-wide CO2 emissions by cars.

[1] http://www.cwc.oulu.fi/workshops/W-Green2008.pdf

Context & Motivation (1)

CO2 reduction at two levels: To reduce the ICT emission itself Use ICT to reduce emission of other human activities (transport, tele-

working, e-commerce,…..)

http://planeteinfo.centerblog.net/

http://www.protegeonslaterre.com/photogallery/ma-planete/terre-entre-nos-mains.jpg


Context & Motivation (2)


Influence from CR environments

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# $ % !


Outline



Power Dissipation

Minimize Ileak by:– Reducing operating

voltage– Fewer leaking

transistors– Reduce transistor

leakage

Minimize Iswitch by:– Reducing operating

voltage– Less switching cap– Less switching activity

Total Power Dissipation

Dynamic PowerDissipation

Static PowerDissipation

dtfCVIVEt

cDDleakDD )(0

2

t

leakDD dtIV0

Total PowerDissipation

Switching PowerDissipation

Leakage PowerDissipation

t

cDD dtfCV0

2

Ileak

Iswitch


Dynamic Power dissipation

• Dynamic power– Average dynamic power (logic gate)

fVCP DDLdynamic 2

21

i

igatewirediffL CCCC ,

Dynamic power is relatively insensitive to temperature

Cgate,i

Cwire Cdi

ff

α CL: load capacitance α: switching activity f: system frequency


Static Power Dissipation(cont.)

• Static power– Leakage components

• Sub-threshold leakage (Isub) • Gate direct-tunneling leakage (Igate)

)( subgateDDleakDDstatic IIVIVP

Gate

DrainSourceIsub

Igate

Static power relates directly to temperature

nkTVVq

sldsubthresho

thGS

eqkT

LWAI

)(

))((

)1)((2)( oxoxox VcVbaBT

ox

auxgnt

ox

oxrJgate e

TVV

TTWLAI


Effect of Die temperature

• Lifetime – Exponential degradation

• Static power– Exponential increase

• Circuit delay

Simulation on Virtex-5 FPGA plate-formMTTF vs Junction temperature


Outline



0 200 400 600 800 1000 1200

30

35

40

45

50

38°C

40°C

Tem

pera

ture

(°C

)

Time (s)

Processing periode : 100 s Processing periode : 50 s

Power (W) Periode 100 s Periode 50 sStatic Power 6,072 6,092Total power 7,028 6,988

46°C

48°C

Temperature and Power consumption

Max. Temp. is produced during running time

Max.Temp. determines cooling system’s performance


Ring-oscillatorT’=2Nτ’

T=2Nτ τ =T(N/2C)/K


• Easy to place• Low power consumption• Few logic resource

Thermal identification

Matlab

∑2Nτ

51-inverter ring oscillator

2^14

100 MHz


Impact of temperatureTotal FPGA die temperature

Local peak temperature


Local thermal characteristic (1)


temperature on different sensor position

Local heat propriety







Dynamically Architectural changes…


Hots-pot migration

Two identify PEs;

Alternate function on different switching frequencies;

1 Hz, ½ Hz, and 1/3 Hz

Thermal sensor placement;


Result

0 100 20026

28

30

32

34

36

38

40

42av

erag

e te

mpe

ratu

re

time

RPD 1Hz without RPD

0 20 40 60 80 10024

26

28

30

32

34

36

38

40

42Te

mep

ratu

re(°

C)

Time(s)

Without DPR DPR 1/3 Hz DPR 1/2 Hz DPR 1 Hz


0 50 100 15027000

28000

29000

30000

31000

32000

33000

34000

35000

Cou

nter

val

ue

Time

without RPD RPD 1Hz/2 RPD 1Hz I

Thermal sensor value


summary

• Thermal sensor design and implementation

• Temperature-Power relationship studying

• Possibility to reduce Hotspot effect by using Dynamic Partial Reconfiguration


Outline



Thermal management for SoC Design

Thermal information helps to build a thermal modelling location working frequency power consumption ….

Time

T °C

T0

Max. Tempera

ture

Configuratio

n contra

int

Configuration rate =f(T0, Pconfig)


Software management policiesHardware management policies

Thermal management for SoC Design

Dynamic time part: make a decision to apply one of the predefined sets found in part one. For required system performance and power economics; make a decision to choose a location to apply hotspot migration

Design-time part: Optimal set of frequencies, parallelism levels for the PE for different working condition


Future work


Hierarchical configuration scenario for homogenous MP area

PE1

Thermal Sensor

C2

BusyT

PE2

Thermal Sensor

C2

BusyT

PE3

Thermal Sensor

C2

BusyT

PE4

Thermal Sensor

C2

BusyT

C1

Migrating Hotspot Guarantee performance Easily to identify PE location with NoC Overhead of configuration

Circuit Parameters : Frequency, voltage, ... The most efficient solution Decease performance

Ring topology


Configuration scenario

Valve of hotspot migrating process – Free choosing at alarm level e.g.: T(1..0)=11– Interrupts function and copy date from

the queue – Locally makes decision without

communication with central controller– Add updated status of cluster to central

controller

Cluster 1

Cluster k


Exemple of queue of thermal information

• Thermal sensor checks remarkable temperature information and sent alarm info with computing data

IDComputing date T(1..0)

T(1..0) Temperature status00 idle

01 lowest occupy10 middle occupy11 Hotspot

ID_ClusterID_PE


• Thermal issues in FPGAs will grow as more and more hard blocks are added to the FPGA fabric;

• A reduction of few degrees in die temperature could have a high impact on the lifetime, reliability and leakage power of the device, but also cooling system;

• Our Digital thermal sensor has shown a flexibility solution to identify local thermal propriety;

• Potential ability to use Dynamic Partial Reconfiguration;• Tutorial : thermal sensor implementation;

Summary


Thank you for your attension?


Detailed configuration scenario

• C2: response hot alarm from PE (operator) and check situation of the others PE in the same cluster.

• Give an order to do hotspot migrating inside cluster• Require hotspot at higher level

• C1: started by requirement of C2. Check situation of the others cluster in the system

• Decide hotspot migrating between cluster (entire cluster)• Require circuit parameters modification at the highest level

C0: started by requirement of C1• Partial Frequency scaling or others strategies


Configuration process

IDComputing date T(1..0)


Future works

• Configuration scenario development • Comparing with others methods

Documents

Temperature- Power Consumption Relationship and Hot-spot Migration for FPGA- based System