The Arrival of the 64bit CPUs - Itanium1 นายชนินท์วงษ์ใหญ่รหัส 43650076 นายสุนัยสุขเอนกรหัส 43650340

The Arrival of the 64bit CPUs - Itanium

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นายส�น�ย ส�ขเอนก รห�ส43650340


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EPIC ( Explicitly Parallel InstructionComputing)

- IA 64 - compatibility with the IA 32 instru

ction set. CPU speed800 MHz , 6.4 GFLOP

S 3 Level Cache

- 1128 225On Die Lv Kb, Lv bb6

34Lv Mb 264 Address space 254 Million Transistors

®What is the Intel Itaniu ™ ?


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bbbb bbbbb 1 2 4Integer: , ,

8 ( ) - Floatingpoi nt si ngl e,dou

-ble and double ebbbbbbb bbbb bbb

bbbbb: 8


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® ™Intel Itanium Instructbbb bbbbbb

1 2[(qp)] mnemonic[.comp ][.comp ] dests = srcs

bbb bbb bbbbbbbbbbb 1 2 3add r = r , r

Predicated instruction 4 1 2 3(p )add r = r , r

Instruction with immediate 1 2 3 1add r = r , r ,

Instruction with completer cmp.eq p3 = r2, r4


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bbbbbb bbbbbbbbbi on

Single space means that both data and in structions share the same memory range.

Uniform means that there are no address regions with predefined functionality.

Linear means that the address space cont ains no segments; all 264 bytes are conse

cutive - Support 2 byte order: Little endian and Bi

-g endian

defines a single, uniform, linear 2address space of 64 bbbbb


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InstructionLevelPar al l el i sm(I LP)

Enabling the compiler/assembly writer to e xplicitly indicate parallelism.

- - Providing a three instruction wide word, ca lled a bundle, that facilitates parallel proce

ssing of instructions. Providing a large number of registers, enab

ling using different registers for different v ariables and avoiding register contention.


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An instruction group is a set of instructions which do not have - -read after write or -write a

-fter write dependencies between them and may execute in parallel.

An instruction group must contain at least o ne instruction; the number of instructions in an instruction group is not limited. Instructi on groups are indicated in the code by cycle

breaks. An instruction group may also end d - ynamically during run time by a taken branc

h.


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Instruction Bundles

Instruction groups are composed of instruction s contained in bundles.

Each bundle contains three instructions, and a template field, which are set during code gener

ation, by a compiler, or the assembler. Template allows the processor to dispatch all t

hree instructions in parallel. - Bundles are aligned at 16 byte boundaries.


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bbbbbbbbb 128 General regi ste

rs 128 - Floating point re

gi sters 64 Predicate registers 8 Branch registers 128 Application regist

ers I nstructi onPoi nter

(IP)regi ster


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Register Validity

enable propagating valid ity/invalidity of a specula

tive load result. Each general register ha

s an a corresponding NaT (Not a Thing) Bit.

- Floating point registers use a special instance of

- pseudo zero, called NaTVal .


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® ™Branchingint he I nt el I t ani um Arbbbbbbbbbb

- Relativedirectbranches,using21bi t di spl acement th at is appended to the in

bbbbbbbbb bbbbbbb bb bbb bundle containing the b

ranch. Indirect branches, using 64

- bit addresses in the branc hr egi st er s.


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bbbbbbbbbbb Allowing the processor to execute all poss

ible branch paths in parallel. 1Instruction 2Instruction

3()

4( 1) 7( 2) 5( 1) 8(2) 6( 1) 9( 2)

1

3

2 2


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Predicationbbb bbb bbbbb rearrange instruction in this order, paring

instruction 4 and 7, 5 and 8 and 6 9and for parallel execution. 1Instruction 2Instruction 3()

4( 1) 7( 2) 5( 1) 8(2) 6( 1) 9( 2)

128 bit longinstruction

word


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Reduced Memory Accbbb bbbbb Hiding memory latency . This e

nables the processor to bring t he data in time, and avoid stalli ng the processor.

Memory latency is hidden thro ugh the use of:

Data speculation - the execut ion of an operation before its

data dependency is resolved. Control speculation - the exe

cution of an instruction befor e its control dependencyis re

solved.


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bbbbbb bbbbbb bbbbbbbbb speculative loads , error/ex

ception detection is deferr ed until final result is actua lly required:

If no error/exception is d etected the latency is hid

den. If an error/exception is d

etected then memory acc esses and dependent ins

tructions must be redone by an exception handler.


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bbbbbbbbbbb bbbbbbb Fetch data before the program needs it, even beyond a branch that hasn't executed.

1Instruction 2Instruction

3()

44 47 45 8Instruction (Load data)

46 Speculative Check

Speculative loading

9Instruction (Use data)

1 2

3

4

5


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Floating Point and Multimedia

-support for single, double, and double exten ded IEEE formats.

- support for multimedia, or data parallel appli cations:

integer data and SIMD computations, simila r to the MMX™ technology.

- - floating point data and SIMD FP computatio - ns, similar to IA 32 Streaming SIMD Extensi

ons.


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™Itanium Architecture Flo- ating point Features

128 - fl oati ng poi nt regi sters

- Amultiplyandaccumulateinstruction(fma),withfourdifferentfloatingpoi nt regi sters for operands (f=a *b+c).Thi s i nstruction enables performinga multiply andadd in the sa

me numberofcycles as one addormultiply instruction. Loadandstore toandf rommemory.Youcanal so l oadf rommemor

- yi nto twofl oati ng poi nt regi sters. - Datatransfer betweenfl oati ng poi nt andgeneral regi ste

rs. -Multiplestatusfi el ds regi ster,enabl es specul ati ononfl oati ng po

intoperati ons. - -Quickconversi onf romi nteger tofl oati ng poi nt andvi ce v

ersa. - Rotatingfl oati ng poi nt regi sters.


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bbbbbbbbbb bbbbbbb Integer multimedia is pro

vided by defining a set of i nstructions which treat th

e general registers 8x8, 4 16 232x , or x bit elements,

and by providing specific i nstructions for operating

on these data elements. support is semantically co

mpatible with the MMX™Technology.


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Chipset 460 4AL GX (support

), 4 6 0 ( 2ort CPU)

400MHz Bus speed bbb-bbbbb, RAMBUS onl

y bbb bbbb bbbbbbb bbbbbb

b bbb bbbbb 10 PCI Slot


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Reference ://../0 2 3 . #proc htm Itanium

http://www.sysopt.com/articles/64bit/index.html -http://developer.intel.com/design/ia64


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The Arrival of the 64bit CPUs - Itanium1 นายชนินท์วงษ์ใหญ่รหัส 43650076 นายสุนัยสุขเอนกรหัส 43650340