thiết kế hệ thống số

7/30/2019 thit k h thng s

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Bi 1 : DFF khng ng b

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity DFF is

port(

d, clk, rst : in STD_LOGIC;

q : out STD_LOGIC

);

end DFF;

architecture DFF of DFF is

begin

process (clk,rst)

begin

if (rst='1') then

q


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Bi 2 : DFF ng b

library IEEE;


entity dff is

port(

d, clk, rst : in STD_LOGIC;

q : out STD_LOGIC );

end dff;

architecture dff of dff is

begin

process

begin

wait until (clk' event and clk='1');

if (rst='1') then

q


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Bi 3 : JKFF khng ng b

library IEEE;


entity JKFF is

port(

J, K, rst,clk : in STD_LOGIC;

Q : buffer STD_LOGIC

);

end JKFF;

architecture JKFF of JKFF is

begin

process(clk,rst)

begin

if(rst='1')then

Q


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Q


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wait until(clk' event and clk='0');

if(rst='1')then

Q


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end RSFF;

architecture RSFF of RSFF is

begin

process

begin

wait until(clk' event and clk='0');

if(rst='1') then

Q


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entity RSFF is

port(

R, S, rst, clk : in STD_LOGIC;

Q : out STD_LOGIC

);

end RSFF;

architecture RSFF of RSFF is

begin

process(clk,rst)

begin

if(rst='1') then

Q


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end if;

end process;

end RSFF;

Bi 7 : mch c 3 u vo a,b,c khi hai trong 3 u vo c gitr bng mt th u ra bng 1

library IEEE;


entity ba_dau_vao is

port( a,b,c : in STD_LOGIC;

y : out STD_LOGIC );

end ba_dau_vao;

architecture ba_dau_vao of ba_dau_vao is

begin

process(a,b,c)

begin

if((a='1' and b='1') or (a='1' and c='1') or (b='1' and c='1'))then

y


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end process;

end ba_dau_vao;

Bi 8: mch 3 trng thi

library IEEE;


entity ba_trang_thai is

port( ena : in STD_LOGIC;

x : in STD_LOGIC_VECTOR(7 downto 0);

y : out STD_LOGIC_VECTOR(7 downto 0));

end ba_trang_thai;

architecture ba_trang_thai of ba_trang_thai is

begin

y'Z');

end ba_trang_thai;

Bi 9 : IC 74139 (//)

library IEEE;


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entity song_song is

port( x : in STD_LOGIC_VECTOR(2 downto 0);

y : out STD_LOGIC_VECTOR(3 downto 0) );

end song_song;

architecture song_song of song_song is

begin

y


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end noi_tiep;

architecture noi_tiep of noi_tiep is

begin

with x select

y


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"10111111"when x="001001"else

"11011111"when x="001010"else

"11101111"when x="001011"else

"11110111"when x="001100" else

"11111011"when x="001101"else

"11111101"when x="001110"else

"11111110"when x="001111"else

"11111111";

end song_song;

Bi 12 : IC 74138 (nt)

library IEEE;


entity noi_tiep is

port(x : in STD_LOGIC_VECTOR(5 downto 0);

y: out STD_LOGIC_VECTOR(7 downto 0) );

end noi_tiep;

architecture noi_tiep of noi_tiep is

begin

with x select


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y


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begin

process

variable x: integer range -1 to n;

begin

wait until (clk='1' and clk' event);

X:=x+1;

if(x=n)then

X:=0;

end if;

y


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architecture demlui of demlui is

begin

process

variable x: integer range n to -1;

begin

wait until (clk='1' and clk' event);

X:=x+1;

if(x=-1)then

X:=n-1;

end if;

y


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end mux4;

architecture mux4 of mux4 is

begin

process(i,s)

begin

case s is

when "00"=>qqqq null;

end case ;

end process;

end mux4;

Bi 16 : phn knh 1-4

library IEEE;



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entity demux4 is

port(i : in STD_LOGIC;

s : in STD_LOGIC_VECTOR(1 downto 0);

q : out STD_LOGIC_VECTOR(3 downto 0) );

end demux4;

architecture demux4 of demux4 is

begin

process(i,s)

begin

case s is

when "00"=>q(0)q(1)q(2)q(3) null;

end case ;

end process;

end demux4;

Bi 17 : Ghp knh 8-1


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library IEEE;


entity mux8 is

port(i : in STD_LOGIC_VECTOR(7 downto 0);

s : in STD_LOGIC_VECTOR(2 downto 0);

q : out STD_LOGIC);

end mux8 ;

architecture mux8 of mux8 is

begin

process(i,s)

begin

case s is

when "000"=>qqqqqqqq null;


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end case ;

end process;

end mux8 ;

Bi 18 : phn knh 1-8

library IEEE;


entity demux8 is

port(I : in STD_LOGIC;

S : in STD_LOGIC_VECTOR(2 downto 0);

Q : out STD_LOGIC_VECTOR(7 downto 0));

end demux8 ;

architecture demux8 of demux8 is

begin

process(I,S)

begin

case S is

when "000"=>q(0)q(1)q(2)


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when "011"=>q(3)q(4)q(5)q(6)q(7) null;

end case ;

end process;

end demux8 ;

Bi 19 : thanh ghi dch c di 4 bt

library IEEE;


entity bon_bit is

port( d,clk,rst : in STD_LOGIC;


end bon_bit;

architecture bon_bit of bon_bit is

signal internal: std_logic_vector(3 downto 0 );

begin


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process(clk,rst)

begin

if(rst='1')then

internal


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"1101101" when x="0010" else

"1111001" when x="0011" else

"0110011" when x="0100" else

"1011011"when x="0101" else

"1011111" when x="0110"else

"1110000" when x="0111"else

"1111111" when x="1000"else

"1111011" when x="1001"else

"0000000";

end chuyen_doi;

Bi 21: chuyn m HEX sang LED 7 thanh

library IEEE;


entity chuyen_ma is



end chuyen_ma;

architecture chuyen_ma of chuyen_ma is

begin

with x select


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y


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library IEEE;


entity thap_phan is

port( x : in STD_LOGIC_VECTOR(3 downto 0);

y : out INTEGER range 0 to 15 );

end thap_phan;

architecture thap_phan of thap_phan is

begin

process(x)

begin

case x is

when "0000" => yy y y y y y y y y


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when "1010"=> y y y y y y


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process(x)

variable temp : bit;

begin

temp:='0';

for i in x ' range loop

temp:=temp xor

x(i);

end loop;

y


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end alu;

architecture alu of alu is

begin

with sel select

y


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variable temp: integer range 0 to 8;

begin

temp:=0;

for i in 0 to 7 loop

if(a (i)='1')then

temp:=temp +1;

end if;

end loop;

q


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begin

process(a )

variable temp: integer range 0 to 8;

begin

temp:=0;

for i in 0 to 7 loop

if(a(i)='0')then

temp:=temp+1;

end if;

end loop;

q


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y : buffer STD_LOGIC );

end chia_tan;

architecture chia_tan of chia_tan is

begin

process(clk)

variable dem:integer range 0 to n;

begin

if(clk='1' and clk' event ) then

dem:=dem + 1;

if(dem=n)then

y


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entity mahoa is



end mahoa;

architecture mahoa of mahoa is

begin

y


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entity giaima is



end giaima;

architecture giaima of giaima is

begin

with x select

y


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use IEEE.STD_LOGIC_signed.all;

entity ma_bu is

generic (n:integer:=4);

port(x : in STD_LOGIC_VECTOR(n downto 0);

y : out STD_LOGIC_VECTOR(n downto 0));

end ma_bu;

architecture ma_bu of ma_bu is

begin

process(x)

variable bien1:std_logic_vector(n downto 0 );

begin

bien1:=not(x);

bien1:=bien1+1;

y


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Bi 31 : B cng n bit

entity bocongnbit is

generic (n:integer:=4);

port(a : in STD_LOGIC_vector (n-1 downto 0);

b : in STD_LOGIC_vector (n-1 downto 0);

cin : in STD_LOGIC;

s : out STD_LOGIC_vector (n-1 downto 0);

cout : out STD_LOGIC

);

end bocongnbit;

architecture bocongnbit of bocongnbit is

begin

process(a,b,cin)

variable c: std_logic_vector (n downto 0);

begin

c(0):=cin;

for i in 0 to n-1 loop

s(i)

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