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I HC QUC GIA THNH PH H CH MINH
TRNG I HC KHOA HC T NHIN
KHOA: IN T VIN THNG
B MN: MY TNH - H THNG NHNG
BI TP MN HC THIT K VLSI
TUN 2
GVGD: Nguyn c Phc
Thnh vin nhm (nhm 4):
1220116 - Lu Trung Tn 1220028 - Trn Hng c
1220089 - Nguyn Tin Phng 1020103 - Nguyn Vn Linh
1220092 - on Minh Qun
1220289 - Giang Thanh Phc
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1 | P a g e
CU 1: VLSI DESIGN FLOW
1/System Ideas:
- Mc ch s dng ca h thng.
- Cu hnh ca h thng.
- S c check li trong phn verification.
2/System-level Verification:
- Do IC v cng phc tp nn ch cn mt b phn gp vn , ton b IC c th s
khng
hot ng.
- System-level Verification c s dng kim tra li nhng thnh phn
mang tm vc
h thng pht hin v sa cha nhng li c th c.
- C board mch s khng c kim tra, thay vo nhng tng v thit k ch
c
kim tra thng qua kh nng thc hin chc nng tm h thng.
- C kh nhiu cng c h tr cho vn ny nh: LVS, DRC, ERC
3/Identifying Sub-blocks:
- L s chia nh qu trnh thc hin chip thnh nhiu khi nh.
- c thc hin nhm sp xp cc b phn c cng mc ch vo cng mt khi d
qun l, ng thi i dy d dng hn.
- Tt c cc khi c kt ni bng TOP LEVEL module.
BOTTOM-UP (FULL CUSTOM) TOP-DOWN (STANDARD CELL) 4/Sub-block
schematic: v schematic ch gm ton transistor bng phn mm Schematic
Editor. 5/Transistor level simulation: m phng mch xem tha mn yu cu
ca project hay cha.
4/+RTL Code: l mt loi intermediate representation rt gn vi ngn
ng assembly, c dng trong cc trnh bin dch. +Structural Code: l code
dng m t cc kt cu cp cng. 5/Logic Synthesis & Target Library
Mapping: s dng nhng thng tin bn trong Target Library kt hp vi RTL v
Structural Code to thnh cc din dch cp cng logic cho cc thnh phn ca
mch. + Target Library: l cc tp hp cc cu lnh c s dng khi vit
code.
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2 | P a g e
6/Layout: to mask-layout bng cng c Layout Editor. 7/Extraction:
kch thc linh kin cng nh parasitic paremeters c tnh ton da vo
mask-layout. 8/Layout vs schematic check (LVS): bc ny nhm kim tra
tin cy ca mt n. Sau khi thit k xong mt n, thit k phi c kim tra vi s
mch ban u xem c thc s chnh xc vi b tr mch ban u.Nu c bt k li g(thiu
hoc tha kt ni ) th phi c sa cha ngay.
Ex: Std. cell library, Embedded memory compilers (memory
libraries), Basic I/O (general purpose), Speciality I/O.
6/Gate-level netlist : V c bn l mt mch thc hin m t cc thit k ca cc
thnh phn c sn trong th vin (c mch t hp v tun t) v mi lin kt ca
chng. Cc netlist ny c to ra bi cc cng c tng hp theo cc rng buc c
thit lp bi cc nh thit k. + Schematic Capture: c s dng thay th cc
HDL code nhm to ra cc gin hoc mch nguyn l ca h thng. 7/Digital
simulation: l vic s dng cc phn mm m phng d on hnh vi ca cc mch k
thut s v Hardware description language . M phng c th c thc hin mc
khc, chng hn nh cp transitor, mc cng, Register Transition Level
(RTL), Electronics system- level (ESL) hoc mc hnh vi. 8/Placement
and routing (standard cell): l mt giai on trong vic thit k cc bng
mch in , mch tch hp. N bao gm hai bc, placement v routing : _ Bc u
tin, placement, bao gm vic quyt nh ni t tt c cc linh kin in t , mch
in , v logic ca cc yu t trong mt s lng gii hn ca khng gian chung. _
Tip theo l routing, n quyt nh vic thit k chnh xc ca tt c cc dy cn
thit kt ni cc thnh phn c t. Bc ny phi thc hin tt c cc kt ni mong
mun trong khi theo cc quy tc v hn ch ca qu trnh sn xut.
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3 | P a g e
9/Post-layout simulation: trch xut t net-list ra nhng mch nh c
nhim v nht nh hoc mt h thng, mc ch l kim tra nh gi v tc mch, nh hng
ca t k sinh v cc trc trc xy ra do tn hiu b sai lch do tr.
9/Post Layout Simulation: l bc m t cc bc cn thit chy mt m phng
trn bn thit k. Cc bc ca m phng trn bn thit k gm: - Chit xut t
Layout - Chit xut t Cell xem - M phng s Layout - Tm tt cc Cell c -
M phng cc Cell xem
10/Placement & routing
Sp linh kin vo trong mt vng xp sn ri map cc chn li vi nhau.
11/Verification
Kim tra li, timing, chc nng mch. Nu khng ng yu cu th phi map
li.
12/Tape-out:
a photomask cho fab.
13/Prototyping
Lm bn mu th.
14/Test:
Kim tra bn mu.
15/Fabrication:
Sau khi kim tra, chnh li, th em sn xut s lng ln.
CU 2: SO SNH THIT K THEO BOTTOM-UP V TOP-DOWN
- Bottom-up:
+ Thit k cc thnh phn t thp nht(t cc cng logic) cu thnh nn cc
b
phn phc tp hn cho n khi hon chnh h thng.
+ u im: c th ti u ha.
+ Nhc im: Nu mun thay i th phi thay i t nhng thit k cn bn
nht.
+ c s dng cho nhng thit b c thit k sn, c cc thnh phn c sn,
hoc nhng thnh phn tiu chun nh phn cng, motor.
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4 | P a g e
- Top-down:
+ c thc hin t trn xung, s dng nhng thnh phn c thit k sn v i
dy li.
+ u im: rt t cng vic phi thc hin li khi c thay i.
+ Nhc im: khng th ti u ha.
+ c s dng rng ri thit k mt phn hay ton b h thng khi yu t thi
gian thit k qu ngn.
