Thuc Hanh Thiet Ke Mach So Voi Hdl -

8/2/2019 Thuc Hanh Thiet Ke Mach So Voi Hdl -

1/83

Gii thiu

B ti liu thc hnh thit kt mch s vi HDL c son tho nhm mc ch htrcc bn sinh vin trong vic tip xc vi ngn ngc t phn cng. M c th l htrcho mn hc thit kt mch s vi HDL.

Ti liu ny bao gm 9 bi, tng ng vi 9 bui. Ni dung chu yu hng nvic hc t duy thit kt phn cng. Gip sinh vin luyn tp cc k nng lp trnh viVerilog, m phng trn Model Sim hay trc tip trn board DE2.

Mc d rt c gng nhng cng khng th trnh khi nhng sai st. V vy rtmong nhn c kin ng gp t pha bn c hoc cc bn sinh vin.

Chn thnh cm n!

TP.HCM, ngy 27 thng 9 nm 2009


2/83

Mc lc

Bui 1. Tng quan v cc phn mm thit k trn FPGA ....................................... 7I. Gii thiu Board DE2 ca Altera............................................................................. 7

1. Gii thiu.......................................................................................................... 72. Thnh phn ....................................................................................................... 73. Mt vi ng dng ca board DE2 .................................................................... 8

II. Cch ci t Quartus II 8.0 v Nios II ..................................................................... 91. Gii thiu.......................................................................................................... 92. Ci t............................................................................................................. 10

III. Cch np chng trnh cho Quartus II 8.0:............................................................ 131. To 1 project:.................................................................................................. 132. Vit chng trnh v bin dch: ...................................................................... 173. To file m phng (simulate) v bt u simulate ......................................... 224. Cu hnh chn v np ln board...................................................................... 30

Bui 2. Mch t hp v mch tun t...................................................................... 40I. Gii thiu ............................................................................................................... 40

1. Gii thiu........................................................................................................ 402. Hng dn thit k FPGA thng qua s khi/Schematic.......................... 40

II. Bi tp .................................................................................................................... 46Bui 3. Lp trnh Verilog vi m hnh cu trc ..................................................... 48

I. Gii thiu ModelSim ............................................................................................. 481. Gii thiu........................................................................................................ 482. Ci t............................................................................................................. 483. Hng dn ...................................................................................................... 58

II. Bi tp .................................................................................................................... 65Bui 4. M hnh hnh vi ............................................................................................ 67

I. Bi tp .................................................................................................................... 67Bui 5. M hnh hnh vi (tt)...................................................................................... 71

I. Bi tp .................................................................................................................... 71Bui 6. My trng thi .............................................................................................. 75

I. Gii thiu ............................................................................................................... 751. Gii thiu........................................................................................................ 752. Hng dn ...................................................................................................... 75

II. Bi tp .................................................................................................................... 83


3/83

Mc lc hnh

Hnh 1.Board DE2 ............................................................................................................. 7Hnh 2. TV Box.................................................................................................................. 8Hnh 3. Chng trnh v (paintbrush)................................................................................ 9Hnh 4. My ht Karaoke v my chi nhc t card SD ................................................... 9Hnh 5. Thng bo cha ci dirver .................................................................................. 10Hnh 6. Chn cch thc ci t driver ............................................................................. 11Hnh 7. Chn th mc tm kim driver............................................................................ 11Hnh 8. Chn th mc cha dirver .................................................................................. 12Hnh 9. Thng bo li ...................................................................................................... 12Hnh 10. Thng bo ci t hon tt ................................................................................ 13Hnh 11. To mi mt project.......................................................................................... 14Hnh 12. Hp hi thoi to mi project ........................................................................... 15

Hnh 13. Hp thoi la chn chip.................................................................................... 16Hnh 14. Hp thoi tng hp cc thng tin ca project ................................................... 17Hnh 15. To mi file....................................................................................................... 18Hnh 16. La chn loi file cn to.................................................................................. 19Hnh 17. Ca s vit code................................................................................................ 19Hnh 18. Ca s lp trnh................................................................................................. 20Hnh 19. Hp thoi lu file .............................................................................................. 20Hnh 20. La chn lop-level cho file ............................................................................... 21Hnh 21. Bin dch chng trnh ..................................................................................... 21Hnh 22. Thng bo vic bin dch thnh cng ............................................................... 22Hnh 23. To mi file testbench....................................................................................... 23Hnh 24. Chn tn hiu sc test................................................................................. 23Hnh 25. Hp thoi la chn tn hiu............................................................................... 24Hnh 26. Ca s la chn tn hiu ................................................................................... 24Hnh 27. Xc nhn li vic la chn tn hiu................................................................... 25Hnh 28. Thit lp gi tr cho cc tn hiu........................................................................ 25Hnh 29. Ca s Save As ................................................................................................. 26Hnh 30. La chn ch simulate ................................................................................. 26Hnh 31. Ca s thit lp cc thng s ca qu trnh simulate........................................ 27Hnh 32. Thc hin chc nng tng hp v phn tch chng trnh ............................... 27Hnh 33. Thng bo thnh cng....................................................................................... 28Hnh 34. Thit lp file testbench cho chng trnh ......................................................... 28Hnh 35. La chn ng dn lu tr file testbench....................................................... 28Hnh 36. Chnh v tr lu tr file testbench.................................................................. 29Hnh 37. Tin hnh qu trnh simulation ......................................................................... 29Hnh 38. Thng bo simulate thnh cng ........................................................................ 30Hnh 39. Kt qu qu trnh m phng (simulation)......................................................... 30Hnh 40. Ca s gn chn ................................................................................................ 31Hnh 41. Cc tn hiu cn gn chn ................................................................................. 31Hnh 42. Danh sch cc chn c thc gn ................................................................ 32Hnh 43. Qu trnh gn chn hon tt .............................................................................. 32

Hnh 44. Lu li file cu hnh chn ................................................................................. 33


4/83

Hnh 45. Hp thoi load file cu hnh chn ..................................................................... 33Hnh 46. Ca s lp trnh (np) ....................................................................................... 34Hnh 47. Ca s Hardware Setup .................................................................................... 35Hnh 48. Ca s lp trnh................................................................................................. 35Hnh 49. Ca s thit b ................................................................................................... 36Hnh 50. Ca s Device & Pin Options........................................................................... 37Hnh 51. Thng bo thay i ch lp trnh ................................................................. 37Hnh 52. Ca s lp trnh trong ch AS...................................................................... 38Hnh 53. La chn file cu hnh ...................................................................................... 38Hnh 54. Qu trnh lp trnh hon tt ............................................................................... 39Hnh 55. Ca s la chn loi file ................................................................................... 41Hnh 56. Ca s lm vic ca Quartus ............................................................................ 42Hnh 57. Hp thoi la chn linh kin c trong th vin ................................................ 43Hnh 58. c linh kin ln ca s lm vic ..................................................................... 44Hnh 59. Ca s gn chn cho tn hiu xut nhp ........................................................... 45Hnh 60. Hon tt vic v mch....................................................................................... 45Hnh 61. La chn file cu hnh cho project ................................................................... 46Hnh 62. Ca s ci t ModelSim.................................................................................. 49Hnh 63. Ca s ci t ModelSim.................................................................................. 50Hnh 64. Ca s la chn th mc ci t....................................................................... 51Hnh 65. La chn tn th mc cho chng trnh........................................................... 52Hnh 66. Tng hp thng tin ci t ................................................................................ 53Hnh 67. Thanh process ci t........................................................................................ 53Hnh 68. Ca s thng bo license ca phn mm.......................................................... 54Hnh 69. ng k thng tin.............................................................................................. 55Hnh 70. Xem thng tin card mng ca my ................................................................... 56Hnh 71. Ca s thuc tn ca h thng........................................................................... 57Hnh 72. Ca s bin mi trng..................................................................................... 58Hnh 73. Hp thoi to mi mt bin mi trng ........................................................... 58Hnh 74. Ca s lm vic ca ModelSim ........................................................................ 59

Hnh 75. To mi project................................................................................................. 59Hnh 76. Thng tin ca project mi ................................................................................. 60Hnh 77. Thm cc file vo project.................................................................................. 60Hnh 78. Hp thoi to mi file ....................................................................................... 60Hnh 79. Ca s son tho ............................................................................................... 61Hnh 80. To mi file....................................................................................................... 61Hnh 81. Thm file vo project ........................................................................................ 62Hnh 82. Code verilog file testbench ............................................................................... 62Hnh 83. Th vin word................................................................................................... 63Hnh 84. Thc hin simulate............................................................................................ 63Hnh 85. Chn tn hiu sc v dng sng (gin ).................................................. 64Hnh 86. Ca s lnh ....................................................................................................... 64Hnh 87. Gin thi gian ca cc tn hiu..................................................................... 65Hnh 88. Kt thc qu trnh simulate............................................................................... 65Hnh 89. S kt ni mch............................................................................................ 66Hnh 90. Kt ni mch ..................................................................................................... 68


5/83

Hnh 91. Bng thc tr v s mch ............................................................................. 68Hnh 92. S mch........................................................................................................ 69Hnh 93. Bng thc tr v s kt ni ........................................................................... 69Hnh 94. S kt ni ..................................................................................................... 70Hnh 95. Bng thc tr ..................................................................................................... 70Hnh 96. Bng thc tr ..................................................................................................... 71Hnh 97. S kt ni mch............................................................................................ 72Hnh 98. Bng thc tr v s kt ni mch ................................................................. 73Hnh 99. Mch cng 4-bit Full-Adder ............................................................................. 73Hnh 100. To file my trng thi .................................................................................... 76Hnh 101. Ca s lm vic............................................................................................... 77Hnh 102. To cc trng thi............................................................................................ 78Hnh 103. To cc ng chuyn trng thi .................................................................... 78Hnh 104. Thit lp biu thc chuyn trng thi ............................................................. 79Hnh 105. Thit lp tn hiu xut v action ca mi trng thi........................................ 80Hnh 106. My trng thi ................................................................................................. 80Hnh 107. Chuyn my trng thi sang nh dng ca ngn ng thit kt phn cn ...... 81Hnh 108. Code verilog c to ra t my trng thi .................................................... 82Hnh 109. Chng trnh chnh ......................................................................................... 83Hnh 110. Thit lp top-level ........................................................................................... 83Hnh 111. Lu trng thi............................................................................................. 84


6/83

Bui 1. Tng quan v cc phn mm thit k trn FPGAMc tiu

Nm c cng ngh FPGA Lm quen board thc hnh DE2 Cit, v lm quen vi cc phn mm: Quartus II, Nios II

I. Gii thiu Board DE2 ca Altera1. Gii thiu

Board DE2 l board mch phc v cho vic nghin cu v pht trin v cclnh vc lun l s hc (digital logic), t chc my tnh (computer organization)v FPGA.

Hnh 1.Board DE2

2. Thnh phnBoard DE2 cung cp kh nhiu tnh nng h trcho vic nghin cu v pht

trin, di y l thng tin chi tit ca mt board DE2:

FPGA:-

Vi mch FPGA Altera Cyclone II 2C35.- Vi mch Altera Serial Configuration EPCS16.


7/83

Cc thit b xut nhp:- USB Blaster cho lp trnh v iu khin API ca ngi dung; h trc 2 ch

lp trnh JTAG v AS.- Biu khin Cng 10/100 Ethernet.- Cng VGA-out.- B gii m TV v cng ni TV-in.- Biu khin USB Host/Slave vi cng USB kiu A v kiu B.- Cng ni PS/2 chut/bn phm.- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in,

line-out, v microphone.

- 2 Header mrng 40-pin vi lp bo v diode.- Cng giao tip RS-232 v cng ni 9-pin.- Cng giao tip hng ngoi. B nh:

- SRAM 512-Kbyte.- SDRAM 8-Mbyte.- B nhcc nhanh 4-Mbyte (1 s mch l 1-Mbyte).- Khe SD card. Switch, cc n led, LCD, xung clock

-

4 nt nhn, 18 nt gt.- 18 LED , 9 LED xanh, 8 Led 7 on- LCD 16x2- B dao ng 50-MHz v 27-MHz cho ng h ngun.

3. Mt vi ng dng ca board DE2 ng dng lm TV box

Hnh 2. TV Box


8/83

Chng trnh v bng chut USB (paintbrush)

Hnh 3. Chng trnh v (paintbrush)

My ht Karaoke v my chi nhc SD

Hnh 4. My ht Karaoke v my chi nhc tcard SD

II.Cch ci t Quartus II 8.0 v Nios II1. Gii thiu

B phn mm thit ki km vi board DE2 bao gm 2 da: Quartus 2 v

Nios 2 Integrated Development Environment (IDE)

Quartus II l phn mm h tr tt c mi qu trnh thit k mt mch logic,bao gm qu trnh thit k, tng hp, placement v routing (sp xp v chy dy),m phng (simulation), v lp trnh ln thit b (DE2).

Nios II, mi trng pht trin tch hp ca h Nios II (IDE), n l cng cpht trin ch yu ca h vi x l Nios II. Phn mm s l mi trng cung cpkh nng chnh sa, xy dng, debug v m t slc v chng trnh. IDE cn

cho php to cc chng trnh tn nhim (single-threaded) n cc chng


9/83

trnh phc tp da trn mt h iu hnh thi gian thc v cc th vinmiddleware.

2. Ci t Ci t Quartus II v Nios II

Qu trnh ci t Quartus II v Nios n gin ch cn a a vo my v thchin theo hng dn ca chng trnh ci t

Ci t phn mm USB blaster driverV Board DE2 c lp trnh bng cch s dng phn mm USB Blaster

(USB Blaster mechanism). Nn nu USB Blaster driver cha c ci t th qutrnh lp trnh xung board DE2 s khng thnh cng.

Sau khi gn board DE2 vo my tnh thng qua cng USB, nu USB Blasterdriver cha c ci t th hp thoi sau s xut hin, ChnNo, not this time sau nhnNext

Hnh 5. Thng bo cha ci dirver

ChnInstall from a specific location v chnNext


10/83

Hnh 6. Chn cch thc ci t driver

Kt tip bn chnSearch for the best driver in these location v sau nhnBrowse.

Hnh 7. Chn thmc tm kim driver


11/83

Hp thoi mi s xut hin bn tm n v traltera\quartus60\drivers\usbblaster, sau nhn OKv tip tc nhnNext

Hnh 8. Chn thmc cha dirver

Ca s thng bo vic kim tra logo window khng thnh cng, tuy nhinvic ny s khng bnh hng n vic kt ni ca chng trnh sau ny. Bntip tc nhn Continue Anyway

Hnh 9. Thng bo li

Nhn Finish hon tt vic ci t


12/83

Hnh 10. Thng bo ci t hon tt

III. Cch np chng trnh cho Quartus II 8.0:1. To 1 project:

Bc 1. VoMenu > file chnNew Project Wizard


13/83

Hnh 11. To mi mt project

Bc 2. Ta chn th mc cha project v t tn cho project, xem hnhbn di


14/83

Hnh 12. Hp hi thoi to mi projectBc 3. Sau ta chn hng sn xut chip v tn loi chip trn mch


15/83

Hnh 13. Hp thoi la chn chip

Bc 4. Cui cng chn Finish hon tt


16/83

Hnh 14. Hp thoi tng hp cc thng tin ca project

2. Vit chng trnh v bin dch:Bc 1. VoMenu > file chnNew


17/83

Hnh 15. To mi fileBc 2. Sau chn loi file m chng ta mun vit chng trnh. y ta

chn loai file Verilog HDL


18/83

Hnh 16. La chn loi file cn toBc 3. Di y l mt on chng trnh demo: tnh hmf = x1 EX-OR

x2

Hnh 17. Ca s vit codeBc 4. Sau khi vit xong th taphi lu tn file trng vi tn module ca

chng trnh


19/83

Hnh 18. Ca s lp trnh

Hnh 19. Hp thoi lu fileCh : ChnAdd file to current projectBc 5. Sau khi lu file xong phi thit lp cho file l top-levelth mi

bin dch c


20/83

Hnh 20. La chn lop-level cho fileBc 6. Bin dch chng trnh:

Hnh 21. Bin dch chng trnh


21/83

Hnh 22. Thng bo vic bin dch thnh cngCh :n y th c th np trc tip ln board DE2 kim th hoc s dng chngtrnh m phng c trn Quartus II. Phn 3 s trnh by cc bc cn thit to file mphng v tin hnh m phng gin thi gian. Phn 4 s trnh by cc bc cn thit np ln board DE2 kim th trc tip trn board ny.

3. To file m phng (simulate) v bt u simulateBc 1. VoMenu > file chnNew, sau chn Vector Waveform File


22/83

Hnh 23. To mi file testbenchBc 2. Sau nhp chut phi chnInsert, chnInsert Node or bus

Hnh 24. Chn tn hiu sc test

Bc 3. ChnNode Finder


23/83

Hnh 25. Hp thoi la chn tn hiuBc 4. Ca s la chn tn hiu s xut hin (xem hnh 26). hin th ra tt c cc chn :

ChnPins: all. Sau chn ntList hin tt c cc chn.

Nt : Chn tng tn hiuNt : Chn tt c cc tn hiuNt : B tng tn hiu

Nt : B tt c cc tn hiuV d mun chn 3 tn hiu f, x1, x2 ta c 2 cch: Chn tng tn hiu theo nt Nhn nt chn tt c c tn hiu

Nhn OK hon tt vic chn tn hiu

Hnh 26. Ca s la chn tn hiu

Bc 5. Nhn OKn nh cc tn hiu cn chn


24/83

Hnh 27. Xc nhn li vic la chn tn hiu

Bc 6.

Thit lp gi tr cc tn hiu:Ta r chut t khi chng liSau s dng cc nt 0, 1 thit lp gi tr cho chng (xem hnh 28)

Hnh 28. Thit lp gi tr cho cc tn hiuBc 7. Sau khi thit lp gi tr ca cc chn xong ta Save li.


25/83

Hnh 29. Ca s Save As

Bc 8. Nhp vo nt la chn ch simulate (xem hnh 30).

Hnh 30. La chn ch simulateBc 9. Trong khungSimulate mode chn chc nng Functional


26/83

Hnh 31. Ca s thit lp cc thng s ca qu trnh simulateBc 10. VoProcessing > Generate Functional Simulation Netlist tin

hnh qu trnh phn tch v tng hp

Hnh 32. Thc hin chc nng tng hp v phn tch chng trnhBc 11. Hp thoi thng bo qu trnh phn tch v tng hp thnh cng,

chn OKn nh


27/83

Hnh 33. Thng bo thnh cng

Bc 12. La chn file testbench cho chng trnh cn m phng

Hnh 34. Thit lp file testbench cho chng trnh

Bc 13. Nhn vo nt la chn ng dn lu tr file testbench.

Hnh 35. La chn ng dn lu trfile testbenchBc 14. La chn v tr lu tr file testbench trong hp thoiSelect File


28/83

Hnh 36. Chnh v tr lu trfile testbench

Bc 15. ChnProcessing > Start Simulation hoc nhp vo nt tin hnh qu trnh simulation. Nu thnh cng th s c thng bo nh hnh

38, v kt qu qu trnh m phng sc hin th nhhnh 39.

Hnh 37. Tin hnh qu trnh simulation


29/83

Hnh 38. Thng bo simulate thnh cng

Hnh 39. Kt qu qu trnh m phng (simulation)

4. Cu hnh chn v np ln board Cu hnh chn cu hnh chn bn tin hnh ln lt theo cc bc sau:Bc 1. Chn Assignments-> Pins ca s la chn chn s xut hin nh

hnh:


30/83

Hnh 40. Ca s gn chnBc 2. Nhp p vo ct To nh trn hnh. Mt menu cha

danh sch cc chn cn gn sc hin ra. Bn chn chn cn gn (v dy chn tn hiu cn gn x1).

Hnh 41. Cc tn hiu cn gn chnBc 3. Tip theo nhn vo ct Location. Mt menu cha

danh sch cc chn trong FPGA sc hin ra bn chn chn ca FPGA sni vi tn hiu (v dy chn chn PIN_N25).


31/83

Hnh 42. Danh sch cc chn c thc gnBc 4. Lp li qu trnh ny cho n khi gn ht cc chn linh kin.

Hnh 43. Qu trnh gn chn hon ttBc 5. lu li file cu hnh chn bn chn File -> Export, sau nhp

tn file cn lu.


32/83

Hnh 44. Lu li file cu hnh chnBc 6. nhng ln cu hnh sau ta c th load file cu hnh bng cch

(nu ln cu hnh chn ny l hon ton ging vi ln cu hnh trc). Bn

chn. Assignment -> Import Assignments, tip theo bn chn file cu hnhchn ri nhn OK.

Hnh 45. Hp thoi load file cu hnh chnCh : DE2 cung cp mt file cu hnh chun, file ny c tn DE2_pin_assigments.csv trong th mc. File cu hnh chun ny s kt ni tt c cc chn ca DE2. Khi bnch cn t tn tn hiu trng tn vi tn hiu m DE2 quy c. V d: cc nt nhn s ctn l SW, cc n led s c tn l LEDG hay LEDR,

Np ln board

DE2 h tr2 cch np ln board. l ch np l JTAG v AS. Trong chJTAG (Joint Test Action Group) th d liu cu hnh sc np trc tip lnFPGA Trong ch ny th thng tin cu hnh s b mt khi tt ngun ch AS


33/83

FPGA. Trong ch ny th thng tin cu hnh s b mt khi tt ngun. chAS(Active Serial), th d liu cu hnh sc np ln b nhflash. Mi khi mngun(reset) th thng tin cu hnh y sc load ln FPGA, do thng tin cu hnhFPGA s khng b mt mi khi tt ngun. chuyn i gia 2 ch np ny thtrn board DE2 cung cp nt RUN/PROG. RUN tng ng vi ch np JTAG,trong khi PROG l chAS.

Lp trnh theo ch JTAG

Tin hnh theo cc bc:Bc 1. Gt nt RUN/PROG trn board DE2 sang RUN, sau chn

Tools->Programmer, ca s lp trnh cho board DE2 s xut hin nh hnhv.

Hnh 46. Ca s lp trnh (np)Bc 2. Trn ca s lp trnh, ch la chn JTAG trong khung ch lp

trnh (Mode). Tip o nu USB-Blaster khng c chn nh trn hnh, thbn nhn Hardware Setup, ca sHardware Setup s xut hin khi bnchn USB-Blaster la chn cng kt ni vi board DE2.


34/83

Hnh 47. Ca s Hardware SetupBc 3. Tr li ca s lp trnh bn chn vo file lp trnh (light.sof). Nu

file ny cha c th bn c th nhn nt Add File thm file ny vo. Tip bn nhp vo la chn Program/configure

Hnh 48. Ca s lp trnhBc 4. Nhn nt Start bt u vic lp trnh. Trong khi lp trnh th cc

n led trn board DE2 s sng mi. Trn ca s lp trnh, thanh Progess scho thy tin trnh np ln board DE2.

Lp trnh theo ch AS

Bc 1. Gt nt RUN/PROG trn board DE2 sang PROG.Bc 2. Vo Assignment -> Device, chn Device v sau chn thit b l

EP2C35F672C6. Tip nhp vo Device & Pin Options, ca sDevice &Pin Opions s xut hin, bn chn tab Configuration, trong khung

Configuration device chn EPCS16. Nhn OK n nh sau dch lichng trnh.


35/83

Hnh 49. Ca s thit b


36/83

Hnh 50. Ca s Device & Pin OptionsBc 3. Tools->Programmer, ca s lp trnh s xut hin (nh hnh ca

s lp trnh). Tip trong khung Mode bn chn Active SerialProgramming. Mt thng bo s hin ln bn chn Yes.

Hnh 51. Thng bo thay i ch lp trnhBc 4. Ca s lp trnh chAS s hin ra nh hnh bn di. Bn

chn nt Add File thm file cn np vo chng trnh (light.pof, file cu hnh cho chAS s c dng *.pofv file cu hnh cho chJTAG sc dng *.sof).


37/83

Hnh 52. Ca s lp trnh trong ch AS

Hnh 53. La chn file cu hnhBc 5. Nhp vo la chn Program/Configure. Tip bn nhn ntStart np chng trnh cu hnh ln board DE2


38/83

Hnh 54. Qu trnh lp trnh hon tt

Bui 2. Mch t hp v mch tun tMc ch: Nm vng cc kin thc


39/83

Mc ch: Nm vng cc kin thc

Thit kFPGA thng qua s khi/Schematic Mch tun tv mch thp

o Rt gn biu thc i sBoole bng phng php ba Karnaugho Gii thut rt gn Quine McCluskeyo Thit kmch tun to Thit kmch thp

I. Gii thiu1. Gii thiu

Ngoi vic vit chng trnh cu hnh FPGA thng qua code verilog nhtrnh by chng trc th Quartus II cn h trnhiu cch thit k FPGA khc:s dng AHDL, EDIF file, SystemVerilog HDL file, Tcl Script file trong thcch thit k s dng s khi, s dng trc tip cc khi lun l l mt trongnhng cch kh thng dng. Di y s trnh by mt v d thit k FPGA thngqua m hnh s khi.

2. Hng dn thit k FPGA thng qua s khi/Schematic hiu r qu trnh thit k ny, chng ti s trnh by mt v dn gin s

dng s khi/schematic. Chng trnh s hin thc php nor trn 2 tn hiuSW[0] v SW[1] sau xut tn hiu ra LEDR[0]. to mt s mch v cuhnh v d ny ln FPGA bn ln lt thc hin cc bc sau:

Bc 1.

MQuartus II v to mt project mi (thc hin nh bi trc trnh by)Bc 2. Vo File -> New hoc nhp vo biu tng trn thanh cng c.

Ca s la chn loi file s xut hin bn chn BlockDiagram/Schematic File sau nhn OK.


40/83

Hnh 55. Ca s la chn loi fileBc 3. Ca s son tho s hin ra nh hnh bn di.


41/83

Ca s ro ect

Thanh cn c

Ca s lm vic

Hnh 56. Ca s lm vic ca QuartusBc 4. thun tin cho vic son tho ca bn, th y ti s gii thiu

chc nng ca mt vi nt trn thanh cng c:

a. (Select tool): con tr l cng c gip chn la cc thnh phn trnca s lm vic

b. Nt (Text tool) : cng c to cc ra cc dng vn bn trn ca slm vic

c. (Symbol tool): cha linh kin s dng cho qu trnh son tho (cccng lun l, cc megafunction, v cc cha nng khc)

d. (Block tool): cng c h trvic to ra cc khi chc nng. Gipcho vic thit k nhiu cp chc nng.

e. (orthogonal node tool): ni dy tn hiuf. (orthogonal bus tool): ni bus cho cc tn hiug. (Zoom tool): phng to, thu nhh. (Full Screen): La chn ch ca s lm vic l Full Screen hay

khng.

i. (Find): cng c tm kim trn ca s lm vicBc 5. Tip n bn chn nt (Symbol tool) ca s xut hin


42/83

Hnh 57. Hp thoi la chn linh kin c trong thvinBc 6. Trn ca s la chn linh kin bn chn primitives -> logic ->

nor2 sau nhn OK. Tip bn nhn chut tri ln ca s lm vic thc hin vic c mt linh kin cng nor (2 ng nhp). kt thc vicchn cng nor2, bn nhp chut phi vo ca s lm vic v chn Cancel


43/83

Hnh 58. c linh kin ln ca s lm vic

Bc 7. Tip tc chn (Symbol tool), trong ca s la chn linh kinbn chn ng dn primitives -> pin -> input, sau bn c 2 tn hiung nhp. Lp li qu trnh ny c thm mt tn hiu output nh hnh

bn di

Bc 8. Bc k tip l kt ni chn cc linh kin. Bn nhp vo biutng (orthogonal node tool) trn thanh cng c, sau drag chut tv tr mun ni n v tr ch

Bc 9. Nhp p vo tn hiu nhp gn chn cho mch thit k. Nhpgi tr SW[0] vo pin name sau nhn OK.


44/83

Hnh 59. Ca s gn chn cho tn hiu xut nhpBc 10. Tng t nh vy bn thit lp cho tn hiu nhp cn li l SW[1]v tn hiu output l LEDR[0].

Hnh 60. Hon tt vic v mchBc 11. Chn Assignments -> Import Assignments, ca s la chn file

cu hnh chn cho FPGA xut hin, bn chn ng dn cho fileDE2_pin_assignments.csv ri nhn OK


45/83

Hnh 61. La chn file cu hnh cho project

Bc 12. Nhn Ctrl + S hoc nhp vo biu tng trn thanh cng c.Khi hp thoi Save As xut hin bn chn ng th mc cha project hinti ca mnh v lu vi tn trng vi tn project ca mnh, ng thi chnAdd file to current project sau nhn OK

Bc 13. Nhp nt trn thanh cng c hoc chn Processing -> StartComplilation bin dch chng trnh

Bc 14. Sau khi qu trnh compile hon tt bn tin hnh np ln boardDE2. Quy trnh np ny hon ton ging vi quy trnh np ln board DE2phn trc.

II.Bi tpBi 1. Hy hin thc hm F (khng rt gn) ln FPGA bng phng php thit

k s khi, tn hiu nhp c a vo t cc SW, v tn hiu xut l ccLEDR. Rt gn hm F, v m hnh transitor v kim tra li kt qu hm rtgn vi kt qu chng trnh chy trn FPGA. Vi hm F nh sau:

a. ))(( bcadcbaF +++= b. bcddabcaF +++= )(

Bi 2. Ch s dng tnh cht ca hm Boole bin i biu thc F thnh dngtng cc tch (SOP) v tch cc tng (POS), vi F

a.

)()( cacbaF++=

b. bcdcbaF +++= )( Bi 3. S dng phng php Ba Karnaugh

a. Rt gn hm += )13,2()15,11,8,7,4,1,0(),,,( dmdcbaF v dng tngcc tch (SOP)

b. rt gn hm )11,8()15,10,7,6,4,2,0(),,,( dMdcbaF += v dngtch cc tng (POS)

Bi 4. S dng gii thut Quine McCluskey rt gn biu thc sau


46/83

a. )11,8()15,10,7,6,4,2,0(),,,( dmdcbaF +=b.

+=)13,2()15,11,8,7,4,1,0(),,,( dmdcbaF

Bi 5. Hy thit k mt SR-Latch s dng D-Latch v cc cng lun l v hinthc n ln FPGA.

Bi 6. Hy thit k mt D-Latch s dng RS-Latch v cc cng lun l v hinthc n ln FPGA kim th.

Bi 7. Mt mch tun t c 2 D-FlipFlop A v B, cc tn hiu nhp ca mchtun t l X, Y. Tn hiu xut l Z. S kt ni ca mch c biu dinthng qua cc cng thc sau:

BABABABA QQXZQQXDYQQYXD +=+=++= ,)(),)((

Hy hin thc mch tun t ny ln FPGA.

Bui 3. Lp trnh Verilog vi m hnh cu trcMc ch: Nm vng cc kin thc

Gii thiu cng c son tho v m phng ModelSim


47/83

Gii thiu cng c son tho v m phng ModelSim HDLs v Verilog

Hin thc cc mch thp v tun tbng verilog Hin thc cc testbench kim th M phng v kim chng thit ktrn ModelSim

I. Gii thiu ModelSim1. Gii thiu

ModelSim l mi trng m phng v kim th (debug) phn cng rt thngdng hin nay. y chng ti s dng phin bn ModelSim web 6.1g(ModelSim-Altera 6.1g web edition).

2. Ci t tin hnh ci t bn ln lt thc hin cc bc sau:

Bc 1. Nu bn cha c file ci t th c th down load file ci t tihttps://www.altera.com/support/software/download/eda_software/modelsim/msm-

index.jsp. Bn chn phin bn web 6.1gBc 2. Sau khi c file ci t bn nhp p chut vo file ny. Ca s ci t

s xut hin.


48/83

Hnh 62. Ca s ci t ModelSimBc 3. Bn nhn Next tip sang bc k tip.


49/83

Hnh 63. Ca s ci t ModelSimBc 4. Bn nhn Yes chp nhn cc yu cu v license ca Altera


50/83

Hnh 64. Ca s la chn thmc ci tBc 5. Tip theo bn nhn Browse la chn ng dn ci t mi hoc c th

th mc mc nh. Sau nhn Next


51/83

Hnh 65. La chn tn thmc cho chng trnhBc 6. Tip tc bn nhn Next, hoc nhp tn th mc mi vo.


52/83

Hnh 66. Tng hp thng tin ci tBc 7. Trong ca s hin th thng tin th mc ci t bn chn Next thc

hin qu trnh ci t. Thanh process s xut hin cho bit tin trnh ci tphn mm.

Hnh 67. Thanh process ci tBc 8. Sau khi qu trnh ci t kt thc mt bn thng bo s xut hin. Nu

bn c file license.dat th chn Yes v b qua quy trnh download file licenset trang web altera. Ngc li nu cha c file ny th bn chn No v sau tinhnh download file license t altera, theo hng dn sau


53/83

Hnh 68. Ca s thng bo license ca phn mmBc 9. download file license, trc tin bn vo trang ch

https://www.altera.com ng k account, sau bn vo trang web sau:Bc 10. https://www.altera.com/support/software/download/eda_software/modelsi

m/dnl-msim-61g.jsp tin hnh download. Trong trang web ny bn chn phinbn Windows (ModelSim-Altera Web Edition) v nhp vo link requires alicense. Trang web s yu cu bn login vo h thng, bn login vo account to ra (nu cha c th ng k mi mt account) sau vo li trang ny down. Trng hp login thnh cng th bn s thy trang web nh sau:

a ch card mng


54/83

Hnh 69. ng k thng tinBc 11. trang web ny bn nhp a ch card mng ca my mnh vo khung

NIC number. ng thi la chn option Yes, include a free ModelSim-AlteraWeb Edition License v Academic: Only for academic/education/hobby purposes.

Sau nhn Continue n nh. Mt email t server sc gi vo email cabn, vo mail v download file license.

Bc 12. Sau khi download file license bn sa tn file li thnh license.dat v lutrong th mc C:\ModelSim.

Bc 13. bit c a ch card mng ca mnh th bn vo Start-> Run, g vocmd v nhn enter. Trong ca s mi xut hin bn g lnh ipconfig /all a chcard mng ca my sc hin th nh hnh v:


55/83

Hnh 70. Xem thng tin card mng ca myBc 14. Sau khi c file license bn tip tc to 2 bin mi trng chn v

tr ca file license. u tin bn nhp chut phi vo Mycomputer (trn desktop)chn Properties. Trong ca s properties bn chn tab advanced


56/83

Hnh 71. Ca s thuc tn ca h thngBc 15. Tip tc bn nhp nt vo nt Environment Variables, ca s cha cc

bin mi trng sc hin th nh hnh v


57/83

Hnh 72. Ca s bin mi trng

Bc 16. Trong ca s user variables bn chn nt New to mt bin mi trngmi. Ca s to mi s xut hin

Hnh 73. Hp thoi to mi mt bin mi trngBc 17. Tip bn nhp tn bin l LM_LICENSE_FILE v gi tr bin l

C:\ModelSim\license.dat, sau nhn OKn nh. Tng t bn to thm mtbin khc c tn l MGLS_LICENSE_FILE v gi tr l C:\ModelSim\license.dat.n y th vic ci c hon tt, chy chng trnh bn ch cn nhp pvo icon ca ModelSim trn desktop.

3. Hng dnDi y s l quy trnh son tho mt project vi ModelSim.

Bc 1.Nhp p vo icon ca ModelSim trn mn hnh desktop. Ca s lm vicca ModelSim s xut hin nh hnh v.


58/83

Hnh 74. Ca s lm vic ca ModelSimBc 2. to mi mt project bn vo File -> New -> Project (xem hnh).

Hnh 75. To mi project

Bc 3.Trong ca s to mi project bn nhp tn ca project, la chn ni lutr project sau nhn OK to mi project.


59/83

Hnh 76. Thng tin ca project miBc 4. K, mt ca s cho php to thm cc file vo project xut hin

Hnh 77. Thm cc file vo project

Bc 5. Bn chn Create New File, hp thoi to mi mt file s xut hin

Hnh 78. Hp thoi to mi fileBc 6. Tip theo bn nhp tn file, chn Browse chn ni lu tr file nyv

chn kiu file s to ra (chn Verilog, nh trn hnh v). Sau khi to xong bnchn close ng ca s thm file vo project.

Bc 7.Nhp p vo file mi to tin hnh son tho.


60/83

Hnh 79. Ca s son thoBc 8. Hnh v trn cha code verilog hin thc mt cng AND 2 ng nhp. Sau

khi g xong code verilog bn nhp vo nt trn thanh cng c bin dchchng trnh. Ca s lnh s cho bit chng trnh bin dch c thnh cng haykhng (xem hnh).

Bc 9. Tip theo kim th ta phi hin thc thm file testbench. FileTestBench ny s s dng chng trnh chnh (cng AND) nh l mt linh kinth vin, v nhim v chnh ca file testbench l lm sao to ra y cc khnng c th kim tra tnh ng n ca linh kin test. Cc bc tip theo ys l quy trnh to ra file testbench.

Bc 10.To mi mt file bn vo File->New->Source->Verilog to mi fileverilog (xem hnh).

Hnh 80. To mi fileBc 11.Ca s ca file mi to s xut hin, bn nhn Ctrl + S hoc nhp vo biu

tng trn thanh cng c lu li file mi ny. Khi ca s Save As xuthin bn nhp tn file vo sau nhn Save lu tr file

Bc 12.K tip bn thm file mi to ny vo project ca mnh bng cch chnFile->Add to Project->Existing File.


61/83

Hnh 81. Thm file vo project

Bc 13.Trong ca s thm file vo project, bn chn Browse tm v tr ca filecn thm vo. Trong khung ca s kiu file (add file as type) bn chn loi filecn thm vo (verilog), nhn OKn nh

Bc 14.Tip theo bn nhp p vo file va mi thm vo bn ca s project, vnhp hin thc code cho file ny.

Hnh 82. Code verilog file testbench

Bc 15.Bin dch file testbench sau nhp vo tab Library. Ton b file trongproject sc bin dch vo th vin word. Bn m th vin ny s thy ccfile va mi to (xem hnh).


62/83

Hnh 83. Thvin word

Bc 16.Nhp chut phi vo file Testbench v chn Simulate thc hin qutrnh simulate (m phng) file testbench.

Hnh 84. Thc hin simulateBc 17.Ca s Object s xut hin, trong ca s ny bn gi phm Ctrl v nhp

chut tri chn nhng tn hiu sc v trn gin thi gian.


63/83

Hnh 85. Chn tn hiu sc v dng sng (gin )Bc 18.Tip theo trong ca s lnh bn g ln run 199 (nh hn thi gian

simulate 1 n v chng trnh vn cha dng li).

Hnh 86. Ca s lnh

Bc 19.Ca s v gin thi gian s xut hin


64/83

Hnh 87. Gin thi gian ca cc tn hiuBc 20. kt thc qu trnh simulate bn c th vo Simulate -> End Simulate

Hnh 88. Kt thc qu trnh simulate

II.Bi tpBi 1. Hin thc b cng Half-adder bng VerilogBi 2. Hin thc b cng Full-adder t cc b cng Half-adder s dng Verilog.Bi 3. Hin thc cc testbench kim th b cng Half-adderBi 4. Hin thc testbench kim th cho b cng Full-adderBi 5. S dng cc cng primitive thit k mch sau


65/83

Hnh 89. S kt ni mch

Vit testbench kim th chng trnh thit k trn.

Bi 6. Pht trin v kim th bng Verilog mch chuyn i mt m BCD sangm Excess-3 nhchng 3.

Bui 4. M hnh hnh viMc ch:

Cng ckin thc v HDL v Verilog Thc hin vic np v kim thtrc tip trn FPGA


66/83

Nm vng quy trnh thit kFPGA Lm quen vi DE2 Sdng Quartus II

I. Bi tpBi 1. Board DE2 cung cp 18 nt gt (SW0-SW17) v 18 n led (LEDR0-

LEDR17). Hin thc mt module, v np ln board DE2 cho php s dngcc nt gt iu khin mhoc tt cc n led ny.

Hng dn: thc hin lnh gn:

assign LEDR[17] = SW[17]



Bi 2. Hin thc mt b mch chn (Multiplexer), gm 3 tn hiu ng nhp X (8bit), Y (8 bit), s (1 bit) v 1 tn hiu ng xut 8 bit M. Nu s = 0 th tn hiung xut M = X, ngc li (s = 1) th M = Y.

Hng dn: hin thc mt mch chn 2-to-1, ngha l X (1 bit), Y(1 bit), M(1bit). Nu s = 0 th M = X, ngc li M = Y. S mch kt ni nh sau:


67/83

Hnh 90. Kt ni mch

Verilog Code: assign m = (~s & x) | (s & y)Bi 3. Hin thc mt b chn 5-to-1 (Multiplexer) t 4 b chn 2-to-1 cho php

chn tn hiu ra m t 5 tn hiu nhp u, v, w, x, y v 3 tn hiu iu khin s0,s1 v s2 (m, u, v, w, x, v y u l cc tn hiu 1 bit). B chn hot ng theong bng thc tr sau:

Hnh 91. Bng thc tr v s mch

Hng dn:

- Hin thc b chn 2-to-1 tng t nh bi 2 (xy dng chng trnh con).

- Hin thc b chn 5-to-1 bng cch s dng 4 b chn 2-to-1, c kt ninh hnh v:


68/83

Hnh 92. S mch

Bi 4. Hin thc mch decode led 7 on vi tn hiu nhp l c2c1c0 v tn hiuxut l mt led7 hot ng nh bn thc tr sau:

Hnh 93. Bng thc tr v s kt ni

Hng dn:

- Ni c2c1c0 vo cc SW[2:0]- Ni tn hiu xut vo led 7 HEX0[0:6]Bi 5. Hin thc chng trnh verilog thc hin cc chc nng sau:


69/83

Hnh 94. S kt ni

- Tn hiu nhp bao gm cc b 3 bit ln lt l SW[0:2], SW[3:5], SW[6:8],SW[9:11], SW[12:14], cc tp bit ny s ln lt cha d liu 100, 011, 010,001, 000 tng ng vi cc k t blank (tt ht), O, L, E hoc H. Cc tn hiuSW[15:17] cho php s chn d liu no sc hin th ln led 7 on

Bi 6. Mrng bi tp s 5 s dng c 8 led 7 on hin th chui nh sau:

Hnh 95. Bng thc tr

Bui 5. M hnh hnh vi (tt)Mc ch: Nm vng cc kin thc

HDLs v Verilog Quartus II Vit chng trnh v kim th trc tip trn board DE2


70/83

Vit chng trnh v kim thtrc tip trn board DE2I. Bi tp

Bi 1. Hin thc mt chng trnh verilog thc hin cc chc nng sau:- Hin th gi tr ca cc switch SW[0:3], SW[4:7], SW[8:11], SW[12:15] ln

cc led 7 on 0, 1, 2, 3.

- Chuyn nhng gi tr t cc switch ra gi tr trn cc led 7. Nu gi tr cacc switch l t 10 n 15 th khng cn quan tm

Bi 2. Hin thc b gii m 4 bit thp lc phn thnh 2 s thp phn hin th trnled 7:

- Tn hiu nhp l cc switch SW[0:3]- Tn hiu xut l cc led 7 HEX0, HEX1- Hot ng theo bng thc tr sau:

Hnh 96. Bng thc tr


71/83

Hnh 97. S kt ni mch

Hng dn:

- Thit k b so snh: Comparator, s dng kim tra liu tn hiu nhpv3v2v1v0 c ln hn 9 hay khng. Nu gi tr nhp ln hn 9 th tn hiuoutput ca b so snh ny, z, c tn hiu l 1 v trc tip iu khin cc bchn 2-to-1 (Multiplexer) v iu khin led7 th 2.

- Thit k mch A, nhn tn hiu nhp v2v1v0 v tn hiu xut l bng tn hiunhp tri 2.

- Thit k b decode7 nhn tn hiu l m3m2m1m0 v gii m ra led7-

Thit k b mch B mch ny iu khin led7 th 2, nu tn hiu nhp l 1 thtn hiu xut l gi tr 1 trn led7. Ngc li hin th gi tr 0 trn led7

Bi 3. Hin thc b cng 4 bit (4bit-Full-Adder) t cc b cng 2 bit (2bit-Full-Adder)

- Tn hiu nhp l cc switch SW[0:3], SW[4:7], v tn hiu carry-in l SW[8]- Tn hiu xut l cc led n LEDR[0:3], carry-out l LEDR[4]Hng dn:

- Hin thc cc mch cng 2bit-Full-Adder theo mch sau


72/83

Hnh 98. Bng thc tr v s kt ni mch

- Kt ni 4 mch cng 2bit-Full-Adder thnh mch cng 4bit-FullAdder theo s sau

Hnh 99. Mch cng 4-bit Full-Adder

Bi 4. Hin thc b cng y 4 bit BCD (t 0 n 9) vi c t sau:- Tn hiu nhp l SW[0:3] (A) v SW[4:7] (B), carry-in SW[8] (C), cc tnhiu nhp A, B c ni vi cc led n LEDR[0:3], LEDR[4:7] ng thi

c hin th gi tr ln led 7 on l HEX6 v HEX4. C c ni viLEDR[8].

- Tn hiu xut (kt qu php cng) c ni vi LEDG[0:3] (S) ng thic hin th ln 2 led7 l HEX1 v HEX0, v carry-out(Co) c ni viLEDG[4].

Bi 5. Hin thc b chuyn i 6-bit nh phn sang 2 s thp phn v hin thtrn 2 led7 on

Bi 6. Hin thc mt chng trnh verilog thc hin cc chc nng sau:- Cho php nhp vo 2 s 16 bit, v sau hin th gi tr (thp lc phn) ca 2

s ny ln led 7 on

- Tn hiu nhp l SW[0:15], SW[16] cho php quyt nh nhp s no (s thnht hay s th 2). Sau hin th 2 s ny ln led 7, su tin ln HEX0,HEX1, HEX2, HEX3. S th 2 ln 4 led 7 cn li.

Bi 7. Hin thc bm BCD, cho php tng gi tr ni dung bin m c migiy mt ln

- Tn hiu KEY0 l tn hiu reset (xa gi trm xung 0)


73/83

- Cc s BCD sc hin th ln 3 led 7 HEX2-0Bi 8. Hin thc mch trn board DE2, hin th thng tin ngy thng nm- Tn hiu KEY0 l tn hiu reset (xa tt c gi tr xung 0)- Hin th thng tin ln cc led7 on.o Gi: (gi tr t 0 n 23) hin thHEX7-6o Pht: (gi tr t 0 n 59) hin thHEX5-4o Giy: (gi tr t 0 n 59) hin thHEX3-2o Sao: (= 1/100 giy, gi tr t 0 n 99) hin thHEX1-0

Bui 6. My trng thiMc ch:

Thit ksdng m hnh my trng thi Cng ckin thc l thuyt v cc my trng thi Moore v Mealy Bit cch xy dng mch tcc my trng thi


74/83

Nm vng kthut rt gn mt my trng thiI. Gii thiu1. Gii thiu

Quy trnh thit k FPGA thng thng kh phc tp i hi ngi thit kphi thng qua kh nhiu bc phc tp. My trng thi l mt trong nhng bctrung gian gip cho qu trnh thit k v hin thc code verilog trnn d dnghn i vi ngi lp trnh. Thng thng c 2 dng my trng thi: Moore vMealy. Tuy nhin trong Quartus ch h trmy trng thi Moore. Bi thc hnhny s gip cc bn sinh vin tip cn vi cch thit k HDL theo cch thc ny.

2. Hng dn to mt my trng thi cc bn thc hin cc bc sau:

Bc 1. MQuartus v to mi mt project (cch to nh trnh by trong buiu tin)

Bc 2. K tip bn vo File -> New hoc nhp vo biu tng trn thanh cngc, to mi mt file


75/83

Hnh 100. To file my trng thiBc 3. Trong ca s to mi file bn chn loi State Machine file, sau nhn

OK. Ca s son tho s xut hin nh hnh v

Thanh cng c

Ca s project

Ca s lm vic


76/83

Hnh 101. Ca s lm vicBc 4. Di y l mt vi cng c h trcho vic thit k mt my trng thi c

trn thanh cng c

a. (Selection tool): Cng c la chn cc thnh phn trong my trng thib. (Zoom tool): Cng c phng to hay thu nh.c. (State tool): Cng c v trng thid. (Transition tool): Cng c vng chuyn trng thie. (State table): Cng cn/hin bng trng thif. (State machine wizard): Cng c to my trng thi bng ca s wizardg. (Insert input port): cng c thm cng nhph. (Insert output port): cng c thm cng xuti. (Generate HDL file): Cng c chuyn my trng thi thnh code verilog,

HDL,

j. (Transition Equation): Cng c n/hin biu thc trn cc cnh chuyn trngthiCc bc tip theo s l quy trnh to ra mt my trng thi c kh nng nhn

din chui 2 bit 1 lin tip. Sau chuyn file ny thnh code verilog.Bc 5. Bn nhp vo cng c (State tool) sau v 3 trng thi nh hnh v


77/83

Hnh 102. To cc trng thi

Bc 6. Tip theo bn nhp vo cng c (Transition tool) v drag chut t trngthi ny n trng thi state1 n trng thi state2 hnh thnh ng chuyntrng thi t trng thi state1 sang trng thi state2. Tng t ta vc mytrng thi nh hnh v (trng hp nu vng chuyn trng thi vo chnh nth ch cn chn cng c transition tool, sau nhp chut tri vo trng thi ).

Hnh 103. To cc ng chuyn trng thi

Bc 7. Tip theo bn nhp vo biu tng (Insert input port) thm mt tnhiu nhp v click vo biu tng (Insert output port) thm mt tn hiuxut

Bc 8. Nhp vo biu tng (State table) hin th bng trng thi (nu bngny bn i). Trong ca s trng thi ny chn tab Transition (xem hnh)


78/83

Hnh 104. Thit lp biu thc chuyn trng thiBc 9. Nhp tn hiu tn tn hiu nhp vo (input1). Trng hp nu ng

chuyn trng thi ny ch bnh hng bi duy nht mt tn hiu nhp (input1)th:

a. Nu chuyn trng thi xy ra khi gp mt tn hiu 0 th nhp tn tn hiu vo(input1)

b. Nu chuyn trng thi xy ra khi gp tn hiu nhp l 1 th nhp tn tn hiu vpha trc c du ~ (~input1, o tn hiu input1)

Trng hp ng chuyn trng thi bnh hng bi nhiu tn hiu th thmdu & gia cc tn hiu (v d: input1 & input2).Bc 10. Tng t nh vy i vi cc ng chuyn trng thi khc.Bc 11. K tip bn chn trng thi state1 sau nhp chut phi chn properties.

Ca s properties s xut hin, bn chn tab Action (xem hnh)


79/83

Hnh 105. Thit lp tn hiu xut v action ca mi trng thi

Bc 12. Trong ct Output Port bn chn tn hiu xut, ct Output Value bn thitlp gi tr xut ra cho trng thi . Sau nhn OKBc 13. Lp li thao tc ny cho 2 trng thi cn li.

a. State1: Output Port l output1, v Output Value l 0b. State2: Output Port l ouput1, v Output Value l 0c. State3: Output Port l output1, v Output Value l 1

Bc 14. Cui cng bn sc my trng thi nh hnh v:

Hnh 106. My trng thi

Bc 15. Nhn Ctrl + S, hoc nhp vo biu tng trn thanh cng c lu limy trng thi ny vi tn l Machine11.smf. Tip theo bn nhn vo biu tng

(Generate HDL file) trn thanh cng c. Khi bn thng bo sinh file HDL xuthin bn nhp vo la chn Verilog HDL sau nhn OK, Quartus s sinh ra mtfile Verilog (Machine11.v) t s my trng thi ny.


80/83

Hnh 107. Chuyn my trng thi sang nh dng ca ngn ngthit kt phn cn


81/83

Hnh 108. Code verilog c to ra tmy trng thi

Bc 16. K tip bn to mt file mi bng cch nhp vo biu tng to ramt file verilog mi. File ny s l file chnh ca project n s s dng linh kinMachine11 tao ra nh l mt thit b bnh thng.

Bc 17. Hon tt code cho file verilog mi to ra ny (xem code).


82/83

Hnh 109. Chng trnh chnhBc 18. Lu li file ny vi tn trng vi tn ca project, ng thi nhp chut

phi vo file v chn la chn Set as Top-Level Entity.

Hnh 110. Thit lp top-levelBc 19. Import file cu hnh chn DE2_pin_assignment.csv cho project nh

hng dn nhng phn trc. Sau bin dch v np xung board DE2 kim th.

II.Bi tpBi 1. Cho s my trng thi sau:


83/83

Hnh 111. Lu trng thi

a. Hy hin thc my chuyn trng thi ny ln DE2b. Hy v bng trng thi v sd mch ca my trng thi trn.

Bi 2. Thit k mt mch tun t cho php kim tra chui 1001. V hin thcn ln board DE2 kim th.

Documents

Thuc Hanh Thiet Ke Mach So Voi Hdl -