Transistors and Layout 1dkao/chap02a.pdf · 2020-03-20 · CrO2 film Photo resist 0 10 20 30 40 50 60 70 80 90 100 200 250 300 350 400 450 500 Transmittance % Wavelength (nm) Soda

VLSI Design : Chapter 5-1 1

Schedule (1)

01. 03/06/20 Chapter 1 Introduction (Moore’s rule)

02. 03/13/20 Chapter 1 Introduction (Cost and TW)

03. 03/20/20 Chapter 2 (Mask)

04. 03/27/20 Chapter 2 (Processing)

05. 04/03/20 兒童節補假一天

06. 04/10/20 Quiz 1, Chapter 2 (Transistors)

07. 04/17/20 Chapter 2 (Cross-section , latch up)


A Quick Review on Chapter One

VLSI?

Moore’s Law

The Difficulties in VLSI Design

Cost of the VLSI Design

Taiwan VLSI Related Industry

0 3M

quantities

$ Sales revenue

Delay

Company A

Company BSales revenue


Chapter 2: Transistors & Layout

Wafer, Masks

Basic fabrication steps (Next week)

Transistor structures

Basic transistor behavior


Flow

Marketing survey

Specification

Manufacture:

Masks, Die, Packaging

Design:

Architecture, Logic, Circuit

Backend, ….

Testing

English, Idea

GDSII

Dice, Chips


Fabrication Services

Educational services (government funding, free for students) :

U.S.: MOSIS

EC: EuroPractice

Taiwan: CIC

Japan: VDEC

Foundry = fabrication lines for hire (fab)

TSMC, UMC, SMIC, Samsung,

Chartered, IBM (X-Fab)

Jazz, Tower, HHNEC……


MOSIS MPW Program• Winning Enabler for New Designs

• MOSIS engagement model for start-ups and initial prototyping runs

• Validate IBM Model-to-Hardware Correlations and Tech Support on test chips

MOSIS

Information Science Institute

University of Southern California

4676 Admiralty Way, 7th Floor

Marina del Rey, CA 90292-6695

U.S. Rep: Wes Hansford

[email protected]

1-310-448-9316

mailto:[email protected]


2020 MOSIS MPW Schedule and

Deliverables

A) MOSIS Deliverable =

40 dies per each chip

design

B) More MOSIS MPW

information:

https://www.mosis.com/pr

oducts/fab-schedule

1. MPW Schedule for IBM: https://www.mosis.com/db/pubf/fsched?ORG=TSMC


2020 Globalfounfries Schedule

https://www.mosis.com/db/pubf/fsched?ORG=GF&page_type=GF

VLSI Design : Chapter 2-1 9More info: http://www.phy.ntnu.edu.tw/demolab/html.php?html=JavaScript/s_pertab


Wafer

Design Layout Masks Photolithographic

ProcessWaferPackage

Chips


柴可斯基拉晶機

Seed Holder晶種固定器

矽坩堝

石墨基底

固-液接面

氬

晶種 Silicon Seed

晶體 Ingot

熔融液體 Melt

Silica Crucible

熱阻絲

拉升方向

旋轉


Floating Zone

Zone refinement


300mm as-grown Crystal

12”


Single Crystal Production



18 Inches Wafer


https://www.youtube.com/watch?v=AMgQ1-

HdElM


Fabrication Processes

IC built on silicon substrate:

some structures diffused into substrate;

other structures built on top of substrate * (SOI)

Substrate regions are doped with n-type and p-type impurities. (n+, p+ = heavily doped)

Wires made of polycrystalline silicon, silicide, Al, or Cu. (Wu, Ti)

Silicon dioxide (SiO2) is insulator.


Chip


積體電路產業流程

晶圓材料廠

電路設計

電路設計公司

光罩製作

光罩製作廠

積體電路製造

積體電路封裝積體電路測試晶圓製造

封裝廠測試廠客

戶



ProcessWaferPackage

Chips Testing

Testing

Testing and packaging

Foundry

Mask


Mask

Photomask is an

image transfer vehicle

that serve the stepper

(scanner) in Fab to

expose the IC circuit

patterns onto wafers

Light source : I-line (365nm)

KrF (248nm)

ArF (193nm)


ProcessWaferPackage

Chips


Binary Photomask

6 inches

1/4 inch

As usual the transmittance will

physically decrease while the

wavelength of a light source is

shorter then 350nm. So the

Quartz with a high transmittance

is essential to a photomask.

Quarts

Cr film

CrO2 film

Photo resist

0102030405060708090

100

250 300 350 400 450200 500

Transmittance %

Wavelength (nm)

Soda lime

glass

Poly silicate

glass

quartz


ProcessWaferPackage

Chips


Crystal

石英（英語：quartz）是大陸地殼數量第二多的礦石，僅次於長石，其晶體結構是SiO4矽-氧四面體的連續框架，其中每個氧在兩個四面體之間共享，得到SiO2的總化學式，石英的種類有很多，無色全透明的石英稱為水晶。有一些被做為半寶石使用，自古以來石英被廣泛用作製作珠寶和硬石雕刻，尤其在歐洲和中東地區。純淨的石英能夠讓一定波長範圍的紫外線、可見光和紅外線通過，具有旋光性、壓電效應和電致伸縮等性質。石英的完整晶體產於岩石晶洞中，塊狀的產於熱液脈礦中，粒狀的則是花崗岩、片麻岩和砂岩等各種岩石的重要組成部分，石英晶體也可用人工方法生長。

---- from Wiki


Material of Mask

A substrate consisted of a quartz plate

sputtered with a chrome thin film (MOSiON)

and coated with a light sensitive polymer

(photo resist) onto the chrome film.

Cr/CrOx

photo resist

quartz


ProcessWaferPackage

Chips


Mask Profile

QZ

Cr/CrOx

photo resist

Development

chemical : TMAH

Etch

wet : (NH4)2Ce(NO3)6,HClO4,H2O

dry : Cl2 , O2

Resist Strip

wet : NMP , H2SO4


Pellicle

Pellicle is used to prevent the particles in

environment from falling onto the

photomask and assure the defect free

exposure process


ProcessWaferPackage

Chips


Mask Flow

exposure process

defect

inspectioncleaning

pre-cleaning

CD / overlay

& basic inspection

mask

repair

pellicle

mountingparticle inspection

outgoing

check

& package

shipping

data conversion


ProcessWaferPackage

Chips


Binary & HTPSN Photomask

6 inches

¼ inch

Bridge phenomenon

will happen

subsequently if the

distance between Binary

two holes is too short.

HTPSM is an effective

solution for improving

resolution and always

applied for metal layers

such like contact, via

and so on.

Photo resist

CrO2 film

Cr film

MoSiONQuarts

Light

diffraction area

Binary HTPSM

Intensity on wafer

Two images on wafer

Amplitude on mask

Bridge


PSM

Phase Shifting Masks (PSM) etch topography

into mask

Creates interference fringes on the wafer

Interference effects boost contrast Phase

Masks can make extremely small gates

conventional maskglass Chrome

Electric field at mask

Intensity at wafer

phase shifting mask

Phase shifter


Mask to wafer

0.25µ 0.18µ

0.13µ 90-nm 65-nm

Layout


OPC

OPC mask Issues

1. Data Handling burden

2. Long exposure time and Process

3. Defect Inspection

Original Design Design with OPC

OPC Software

Mask

Writing Tool

Conventional

Binary Mask

lithography

Design Image on Mask

OPC Binary Masklithography


ProcessWaferPackage

Chips


OPC (2)

OPC Fracture


OPC (3)

Optical Proximity Correction

(OPC,光學鄰近校正) is a

photolithography enhancement

technique commonly used to

compensate for image errors

due to diffraction or process

effects. we'd like printed on the wafer,

the shape after applying

optical proximity correction,

how the shape actually prints


Fabrication Flow


ProcessWaferPackage

Chips

Iterate fro 20~40+ times

GDSII

Testing

Testing

Design house

Testing and packaging

Foundry

CP

FT


IC Compiler

Initial Layout

Lithography Compliance Check

Lithography Models

Hotspot Detection

Detects & Corrects Lithography

Hotspots

Clean Layout

Hotspot Correction Hotspot

Detected


Alignments

• CD (critical dimension)

line width of pattern geometries on photomask

• registration

(position accuracy)

A

Alignment mark

Bar code

Feducial

main cell

Frame

H0299-4U20A1

title

A A

A


ProcessWaferPackage

Chips


Repair (1)

Ga focused ion beam

Styrene Ionized carbon

Pin hole

Before repair

After repair

The ionized carbon will be diffused onto the pin

hole while the FIB is applied.


ProcessWaferPackage

Chips


Repair (2)

Pin dot

Laser Beam

Before repair

After repair

The pin dot will be removed by laser beam.


ProcessWaferPackage

Chips


Inspection

A:端面接觸痕

B:端面霧化

C:導角連續亮點

D:Pellicle框與Pellicle case接觸痕

E:Pellicle框上原材製程殘留痕跡

F:Mask洗邊不完整

G: Case 接觸痕

H:Mask 邊緣數字符號未解析

I:G面亮紋(距離 Edge5mm內)

J:膜面亮紋(距離 Edge5mm內)

K:夾具接觸痕

L:原材端面刻字


ProcessWaferPackage

Chips


N-P Type

Si

Si

Si

P

Si Si

Si

Si

Si

Si

Si

Si

B

Si Si

Si

Si

Si

HoleExtra electron

N type P type

VLSI Design : Chapter 2-1 42More info: http://www.phy.ntnu.edu.tw/demolab/html.php?html=JavaScript/s_pertab


N-P Type

Si

Si

Si

N

Si Si

Si

Si

Si

Si

Si

Si

P

Si Si

Si

Si

Si

HoleExtra electron

N type P type

B 硼P 磷


Diode

PN


Diode 2

PN

V

Depletion region

+ _


Transistor


Schedule

01. 03/06/20 Chapter 1 Introduction (Moore’s rule)

02. 03/13/20 Chapter 1 Introduction (Cost and TW)

03. 03/20/20 Chapter 2 (Mask)

04. 03/27/20 Chapter 2 (Processing)

05. 04/03/20 兒童節補假一天

06. 04/10/20 Quiz 1, Chapter 2 (Transistors)

07. 04/17/20 Chapter 2 (Cross-section , latch up)


Quiz Next Week

15%

Covered From Chapter 1 to today’s material

Time: 19:20 ~ 19:40

Please bring color pens and Photo ID

Seat will be arranged



ProcessWaferPackage

Chips Testing

Testing

Foundry

Fab Processes


● 亂流清淨空氣從過濾器吹出口，由地板附近吸入。

空調機

●


晶片

Wafer

薄膜形成

Thin Film Deposition

微影術Photolithography

光罩Mask Set 蝕刻

Etch

晶片完成Completed Wafer

雜質滲入Dopant Diffusion/ Implantation

積體電路製造之流程圖 Integrated Circuit Process Flow


積體電路生產流程 Integrated Circuit Process Flow

● 第一層光罩1st masking step

● 蝕刻機Etcher ● 離子植入機Ion Implanter● 氧化爐 Furnace

● 晶圓Wafer ● 初步氧化

Oxidation

● 蝕刻 Etching

● 金屬濺鍍機 Sputter● 擴散爐 Furnace

● 氧化爐 Furnace ● 第三層光罩3rd masking step

重覆前述製程數次

Process repeats

● 金屬濺鍍Sputtering

● 氧化Oxidation● 擴散 Diffusion ● 微影蝕刻Lithography Etching

● 微影蝕刻Lithography Etching

● 晶圓針測

Wafer Probing

● 晶粒黏著Dice Attachment

● 打線連接Bonding

● 完成裝配及測試

外包廠代工Subcontractor

● 晶圓切割Wafer Sawing Finished IC Package● 金屬層微影蝕刻

Metal layer Litho/Etching

● 第N 層光罩Nth masking step

● 第二層光罩2nd masking step

● 微影製程Photo Lithography

● 離子植入Ion Implantation


●垂直層流清淨空氣自屋頂至地板的流通方式。

空調機





Clean-room Standard


Photolithography

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).


ProcessWaferPackage

Chips

Etch

Wet

Dry

CVD

Ion Imp

上光阻液軟烤曝光硬烤顯影

Etching





ProcessWaferPackage

Chips


Photolithography

Mask patterns are put on wafer using photo-

sensitive material:


ProcessWaferPackage

Chips




ProcessWaferPackage

Chips



Die Size and Yield

Test Keys



ProcessWaferPackage

Chips


Doping


ProcessWaferPackage

Chips







SiO2

O2HSiOO2SiH 22

C 450

24

22

C 500~300

24 2HSiOOSiH


Search for the “VLSI manufacture”NXP

https://www.youtube.com/watch?v=gBAKXvsaEiw

GF

https://www.youtube.com/watch?v=UvluuAIiA50

TSMC

https://www.youtube.com/watch?v=4Q_n4vdyZzc

https://www.youtube.com/watch?v=gBAKXvsaEiw

https://www.youtube.com/watch?v=UvluuAIiA50


Photolithography

oxidation

opticalmask

processstep



photoresist

stepper exposure

development




ProcessWaferPackage

Chips


Processes

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

Photoresist

SiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO

2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch


ProcessWaferPackage

Chips

cross

section


Processing II-1


ProcessWaferPackage

Chips


Processing II-2Design Layout Masks Photolithographic

ProcessWaferPackage

Chips

Ex: Metal, poly, ……


Basic fabrication steps

Transistor structures

Basic transistor behavior


Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2


ProcessWaferPackage

Chips

Transistor level

Gate level

Gate level

Gate level


From Design to Layout


ProcessWaferPackage

Chips

Layout

level

level


Process steps

First place tubs to provide properly-doped

substrate for n-type, p-type transistors:

p-tub (p-well) n-tub (n-well)

Substrate (p--)

Substrate (p--)

Cross-section


Process steps, cont’d.

Pattern polysilicon before diffusion regions:

Self-alignment

p-tub n-tub

poly polygate oxide

Substrate (p--)


Process steps, cont’d

Add diffusions, performing self-masking:

p-tub n-tub

poly poly

n+n+ p+ p+

All the PMOS and NMOS have been built now!!

Substrate (p--)



Start adding metal layers:

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

contact via

Substrate (p--)


The Cross Section of an IC

substraten+ n+

p

substrate

metal1

poly

SiO2

metal2

metal3

transistor contact

via


The Cross Section of an Inverter

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2




Transistor layout

n-type (tubs/well may vary):

w

L p-well

poly

n-diffcontact


NMOS Transistor


Transistor structure

n-type transistor: (Angstrom) Å , A, AU

1/10 mµ , 10-10m, 10-8cm


Quick Look Again (1)

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO

2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)


ProcessWaferPackage

Chips



SiO2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and V

Tpadjust implants

n

(f) After p-well andV

Tnadjust implants

p


ProcessWaferPackage

Chips



(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2


ProcessWaferPackage

Chips

Self-alignment again!!



(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO

2


ProcessWaferPackage

Chips









Photolithography

Oxidation / metal / poly

opticalmask

processstep



photoresist

stepper exposure

development




ProcessWaferPackage

Chips


Metal Lines


ProcessWaferPackage

Chips

Let’s have a look at

the real process


IC Cross Section and 3D View


44

SEM X-section

- DeviceHV-NMOS

X 6000

N+

N-grade N-drift N-driftN+

N-grade

HV-PMOS

X 6000

P-grade P-gradeP+ P+

P-drift P-drift

DDD structureX 20000

N-grade

N+




Quiz Next Week

15%

Covered From Chapter 1 to today’s material

Time: 19:20 ~ 19:40

Please bring color pens and Photo ID

Seat will be arranged

Documents

Transistors and Layout 1dkao/chap02a.pdf · 2020-03-20 · CrO2 film Photo resist 0 10 20 30 40 50 60 70 80 90 100 200 250 300 350 400 450 500 Transmittance % Wavelength (nm) Soda