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Bi tpBi 1:
Thanh ghi biu din sthc di dng chun IEEE FP 754 (single
precision) nhsau:
1 1000 0101 10111000100000000000000
Xc nh gi trsthc.
Bi 2:
Xem xt mt chng trnh chy trn mt bxl MIPS. Ngi ta thng k c ktquca
chng trnh ny nhbng sau:
Loi lnh Tlthc thiLoad (lw) 15%
Store (sw) 10%
Cc lnh shc R-Format (ALU) 45%Lnh rnhnh (beq) 30%
Gisthi gian thc thi ca cc khi chc nng nhsau: Memory (c v ghi):
150ps
Register File (c v ghi): 30ps
ALU v cc bcng: 40ps
Bqua thi gian thc thi i vi cc khi chc nng cn liKin trc ca bxl
MIPS c thit ktin ha qua cc phin bn sau:Kin trc A: bxl MIPS c thit
ktheo kin trc single-cycle(mi lnh cthc hin trong mt chu kn),
single-clock (xung nhp dng chung cho tt c cclnh).Kin trc B: bx l
MIPS c thit ktheo kin trc single-cycle(mi lnh cthc hin trong mt chu
kn), multi-clock(xung nhp c ththay i cho tng lnh).Kin trc C: bx l
MIPS c thit k theo kin trc multi-cycle (cc lnh cthc hin trong nhiu
chu k), single clock (xung nhp dng chung cho tt ccc lnh).Kin trc D:
bx l MIPS c thit k theo kin trc multi-cycle (cc lnh cthc hin trong
nhiu chu k), single clock (xung nhp dng chung cho tt ccc lnh).Cc
lnh c thc hin theo k thut pipeline(Gischng trnh trn khi thc thi
pipelinekhng gy ra stallhoc harzards).a) Xc nh tc xung nhp
(clock rate) ti a c thcp cho bxl MIPS theo kin
trc A.b) Xc nh speedup gia cc kin trc A v B, C v D.
Bi 3:
Xt bxl thc hin lnh theo pipeline 5 giai on.
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a) Xc nh tt cph thuc d liu (data dependency) trong on chng trnh
sau.Ph thuc no trong cc ph thuc trn c th c gii quyt bng k
thutforwarding?
add $s2,$s5,$s4
add $s4,$s2,$s5
sw $s5,100($s2)
add $s3,$s2,$s4
b) Trong on chng trnh sau, thanh ghi no c c trong chu kclock
th5,thanh ghi no c ghi khi kt thc chu kclock th5?
add $s1,$s2,$s3
add $s4,$s5,$s6
add $s7,$s8,$s0
add $t0,$t1,$t2add $t3,$t4,$t5
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Bi giiBi 1:
Thanh ghi single precision l
1 1000 0101 10111000100000000000000
S = 1Ereal= E bias = 133 127 = 6
Sthc l: 1.101110001 x 2^6= -110.125
Bi 2:
a) Xc nh tc xung nhp (clock rate) ti a c thcp cho bxl MIPS theo
kintrc A.
Lnh load c thi gian thc thi lu nht nn CC = thi gian thc hin lnh
load
Lnh load qua 5 giai on: np lnh + Thao tc trn register file
(read) + thaotc ALU + Bnh+ Thao tc trn register file (write)
Thi gian = 150 + 30 + 40 + 150 + 30 = 400ps
CC = 400ps => Clock rate = 1/CC = 2.5GHz
b) Xc nh speedup gia cc kin trc A v B, C v D.
Execution Time (A) = 400 * IC
Execution Time (B) = (0.15 * 400 + 0.1 *370 + 0.45 * 250 + 0.3 *
220) * IC =275.5 * IC
=> speedup (B vs A) = 1.45
Execution Time (C) = CPI * IC * CC = (0.15 * 5 + 0.1 *4 + 0.45 *
4 + 0.3 * 3) * IC* CC
= 3.85 * IC * CC
Vi kin trc D, v khng c stall v harzards nn CPI = 1
Execution Time (D) = 1 * IC * CC
=> speedup (D vs C) = 3.85
Bi 3:
a) Xc nh tt cph thuc d liu (data dependency) trong on chng trnh
sau.Ph thuc no trong cc ph thuc trn c th c gii quyt bng k
thutforwarding?
add $s2,$s5,$s4
add $s4,$s2,$s5 # phthuc lnh 1 (v S2)
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sw $s5,100($s2) # phthuc lnh 1 (v S2)
add $s3,$s2,$s4 # phthuc lnh 1 (v S2)
# phthuc lnh 2 (v S4)
Tt ccc phthuc trn u c thgii quyt bng kthut forwarding
b) Trong on chng trnh sau, thanh ghi no c c trong chu kclock
th5,thanh ghi no c ghi khi kt thc chu kclock th5?
add $s1,$s2,$s3
add $s4,$s5,$s6
add $s7,$s8,$s0
add $t0,$t1,$t2
add $t3,$t4,$t5
Thanh ghi t1, t2 c c trong chu kclock th5
Thanh ghi s1 c ghi khi kt thc chu kclock th5
