Microelectronic Technology

Thermal Oxidation (III)

Film Thickness (Å) Colour

500 Tan

700 Brown

1000 Dark violet to red violet

1200 Royal blue

1500 Light blue to metallic blue

2000 Light gold or yellow slight metallic

2700 Red-violet

3100 Blue

3400 Light green

3600 Yellow-green

3900 Yellow

Colour Chart for Thermally Grown SiO2 Films

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

Basic Concepts• SiO2 is amorphous even though it grows on a crystalline substrate.

• Four types of defects or charges are associated with Si/SiO2 interface.

++++ +xxxxxx

+++ -

--

K+

TransitionRegion

Na+SiO2

Qm

Qot

Qf

QitSilicon

• Qf - fixed oxide charge• Qit - interface trapped charge• Qm - mobile oxide charge• Qot - oxide trapped charge

C-V Measurements

• Powerful technique for characterizing semiconductor / insulator structures.

• DC bias + small AC high frequency signal applied.

Accumulation

• Electric field lines pass through the “perfect” insulator and Si/SiO2 interface, into the substrate where they control charge carriers.

• Accumulation, depletion and inversion result.

C-V Measurements

Depletion

Inversion

C-V Measurements

Ideal LF

Ideal HF

Deep Depletion

C

Cox

DC Gate VoltageVTH

CMin

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

Gate voltage

Capacitance

Co

Capacitance-Voltage curve for MOSFET and shift in V

Metal

Silicon

Oxide +Na+Na

+Na

++ +

+

+Na + + + +X X X X X

Mobile ionic charge (Q )o

Radiation induced charge (N )ot

Fixed oxide charge (Q )s

Interface traps (N )st

otPhysical origin of N , Q and Ns st

Electrical defects in Si-SiO system2

Co

CoCsAccumulation Depletion

CoCs,min

Inversion

0

+VFB

Ideal

FB

Determination of Fixed Oxide Charge Density

VFB=φ ms- Qf /COX

Determination of Fast Interface States

C-V Measurements

• HF curve - inversion layer carriers cannot be generated fast enough to follow the AC signal so C is the resultant of Cox and CD. Thus, it remains at minimum value.

• LF curve - inversion layer carriers can be created and recombine at AC signal frequency so C is just Cox and reached at maximum value.

• Deep depletion - “DC” voltage is applied fast enough that inversion layer carriers cannot follow it, so CD must expand to balance the charge on the gate.

• C-V measurements can be used to extract quantitative values for:

tox - oxide thickness NA or ND - the substrate doping profile

Qf, Qit, Qm, Qot - oxide, interface charges

Advanced Models

• Some advanced models have been developed that include the effect of other parameters such as: pressure, crystal orientation, mixed ambient, substrate doping etc. on growth kinetics.

• An advanced point defect based model for oxidation has been developed which gives results matching very closely with experimental data.

• The model for 2D SiO2 growth kinetics has also been developed.

Advanced Point Defect Model

Why?• OED ( Oxidation Enhanced Diffusion)• ORD ( Oxidation Retarded Diffusion)

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

SUPREM Modeling for Oxidation Processing

2D Oxidant Diffusion

• Expected oxide thickness: Convex > Planar > Concave• Experimental Result: Planar> Convex > Concave• 2-D Diffusion can,t explain the thinning effects.• It does play some role

Stress Due to Volume Expansion

• Oxide layers on Si are under compressive stress -- Volume Expansion -- Difference in TCE• On shaped Si surfaces: Stress can be much larger -- Dimensionally confined

Simulation Result using ATHENA

Recessed LOCOS Isolation Structure

Oxidation Simulation Results Using ATHENA

Oxidation simulation showing the effects of including stress effects in oxidation .A 20nm SiO2 pad oxide is first grown and a 150nm Si3N4 layer is then deposited. A 90min 100C H2O oxidation was then performed.

Left: No stress dependent parameterRight: With stress dependent parameter

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

High Temperature Furnace Wafer Loading

Dr. G. Eranna Integrated Circuit Fabrication Technology © CEERI Pilani

OXIDIZING SPECIES ARE CHARGED OR NEUTRAL IS STILL A SUBJECT OF

CONTROVERSY