Voltage Controlled Oscillator Design - Short Course at NKFUST, 2013

壓控振盪器設計李健榮助理教授國立臺北科技大學電子工程系

Department of Electronic EngineeringNational Taipei University of Technology

Outline

• Resonator• Feedback, Two-port Reflection, and Negative Resistance• Feedback Loop Analysis• Amplifier Configurations• Capacitor Ration with Colpitts Oscillators• ADS Simulation Tips• Phase Noise and Lesson’s Model• Summary

Department of Electronic Engineering, NTUT2/60

Introduction

• An oscillator is a circuit that generates a periodic waveform.• Oscillators are used with applications in which a reference

tone is required. In most RF applications, sinusoidal references with a high degree of spectral purity (low phase noise) are required.

90

I t

cos ct

Q t

Low Noise Amplifier(LNA)

Bas

eban

d Pr

oces

sor

LPF

LPF

90

I t

cos ct

Q t

ms t

Power Amplifier(PA)

Antenna

Bas

eban

d Pr

oces

sor


LC Resonator

• An LC resonator determines the oscillation frequency and often forms part of the feedback mechanism.

If i (t) = Ipulsed (is applied to the parallel resonator, the system time response:

2

2 2

2 1 1cos4

tRC

pulseout

I ev t t

C LC R C

2 2

1 14osc LC R C

1

osc LC

L C R

outv t

i t

TimeA

mpl

itude

R

pulsedi t I t


Adding Negative Resistance Through Feedback

• In any practical circuit, oscillations will die away unless feedback is added to generate a negative resistance in order to sustain the oscillation.

L C pR nR

L C sr

nr

feedback active device

Parallel RLC Resonator Series RLC Resonator

feedback active device


Design Method: Feedback System

• The oscillator can be seen as a linear feedback system.• The gain of the system:

• Barkhausen’s Criterion: For sustained oscillation at constant amplitude, the poles must be on the jω axis

which states that the open-loop gain around the loop is 1 and the phase around the loop is 0 or some multiple of 2π.

• To find the poles of the closed-loop system, one can equate this expression to zero, as in .

1

out

in

V s G sV s G s H s

1 0G s H s

1G j H j 1G j H j 2G j H j n and

Department of Electronic Engineering, NTUT

G s

H s

outV s inV s

6/60

Design Method: Two-port Reflection

• Two-port Reflection'11 1G S

'22 1L S

If the two-port network is oscillating at one port, it must be simultaneously oscillating at the other port.

Sine the resonator is passive, thus 1G


Design Method: Negative Resistance

• One-port Negative Resistance:

0DR R

0DX X

Z j R jX

D D DZ j R jX


Current Limiting

• If the overall resistance is negative, then the oscillation amplitude will continue to grow indefinitely. In a practical circuit, this is, of course, not possible.

• Current limiting (power rails, or nonlinearity) eventually limits the oscillating magnitude to some finite value effect of the negative resistance in the circuit until the losses are just canceled, which is equivalent to reducing the loop gain to 1.

v

growth

t

limited


Implementations of Feedback

• Feedback (or Gm ) is usually provided in one of three ways: Colpitts oscillator:

Using a tapped capacitor and amplifier to form a feedback loop Hartley oscillator:

Using a tapped inductor and amplifier to form a feedback loop Gm oscillator:

Using two amplifiers in a positive feedback configuration

G

amplifier

G

amplifier

amplifier

G

L

buffer


Common Oscillator Configurations

bici

C

E

B

1C

2C

3Lbi

ci

C

E

B

1L

2L

3C

bici

C

E

B

1C

2C

3Lbi

ci

C

E

B

1C

2C

3L

Colpitts Hartley

Clapp Siler


Amplifier Configuration (Colpitts or –Gm)

• The Gm oscillator has either

A CC amplifier made up of Q2 , and Q1 forms feedback A CB amplifier consisting of Q1, and Q2 forms feedback

• Colpitts and Hartley oscillators can be made either CB or CC.

C L

1Q

2Q1C

2CL

1Q1C

2C

1Q

L

CB Colpitts CC ColpittsGm Oscillator

CC

CB


Loop Analysis (I)

• Loop analysis gives information about the oscillator : (1) Determine the frequency of oscillation(2) The amount of gain required to start the oscillation

1C

2CL

1Q

Common base

2C

1C

LpRer

evc m ei g v

At the collector, 1 11 1 0c e m

p

v sC v sC gR sL

At the emitter, 1 2 11 0e ce

v sC sC v sCr

1 1

1 1 2

1 1001

mp c

e

e

sC sC gR sL v

vsC sC sC

r


cv

ev

cv

13/60

Loop Analysis (II)

• The conditions for oscillation:

where ωconr is the corner frequency of the HPF formed by the capacitive feedback divider.

1 1 2 1 11 1 1 0m

p e

sC sC sC sC sC gR sL r

1 23 2 11 2 1 1 2

1 0mp e p e e

L C C LC Ls LC C s LC g s C CR r R r r

1 2

1 2 1 2

1 1

e p

C CC C L r R C C L

pL

RQ

L

2

2 00 0 0

1 2 1 2

1 11 1e p p e L conr

L Lr R C C R r C C Q

1 2m

L

C Cg

Q

Tells us what value of gm (and corresponding value of re) will result in sustained oscillation. For a real oscillator gm would have to be made larger than this value to overcome any additional losses not properly modeled.


, , and

14/60

Capacitor Ratios with Colpitts (I)

• The capacitive divider (C1 , C2 , and re) affects oscillation frequency and feedback gain, which acts like a HPF.

1 1

1 2 1 21 1e e cor

c e

cor

jv j r C Cv j r C C C C j

L pR1C

2C erev

cv

Frequency

1

1 2

CC C

Gain

0A

cor

10

1 2

CAC C

1 2

1cor

er C C

1tan2 c

If the frequency of operation is well above the corner frequency ωcor , the gain is given by the capacitor ratio and the phase shift is zero.

90

0

Phase

Frequencycor


Capacitor Ratios with Colpitts (II)

• re is transformed to a higher value through the capacitor divider, which effectively prevents this low impedance from reducing the Q of the LC resonator.

• The resulting transformed circuit as seen by the tank

2

2,tank

1

1e eCr rC

L pR1C

2C,tanker

cv

1 2

1 2

1

T

C CLC CLC

(make C2 large and C1 small to get the maximum effect of the impedance transformation)


Negative Resistance

• Negative resistance of CB Colpitts oscillator

• Input impedance:

• A necessary condition for oscillation:This is just a negative resistor in series with the two capacitors.

where rs is the equivalent series resistance on the resonator.

2i me

vi g v j C v

r

1m

e

gr

2

iivj C

1

i mce

i g vv

j C

1 2

1 m ice i

g iv ij C j C

21 2 1 2

1 1i ce mi

i i

v v v gZi i j C j C C C

21 2

ms

grC C

ii

iv

cev

ver

1C

2Cmg v


where , , and

17/60

Negative Resistance for Series/Parallel Circuits

• Since the resonance is actually a parallel one, the series components need to be converted back to parallel ones.

• However, if the equivalent Q of the RC circuit is high, the parallel capacitor Cp will be approximately equal to the series capacitor Cs , and the above analysis is valid. Even for low Q, these simple equations are useful for quick calculations.

2C

1C

LpRer

xvm xg v

cvsr negR

L TC


Example

• Assume L = 10 nH, Rp = 300 Ω, C1 = 2.5 pF, C2 = 10 pF, and the transistor is operating at 1 mA, or re = 25 Ω and gm = 0.04. Using negative resistance, determine the oscillator resonant frequency and apparent frequency shift.

( |negative resistance| > original resistance,

the oscillator should start up successfully)

This is a frequency of 1.2353 GHz, which is close to a 10% change in frequency. Further refinement should come from a simulator.

1 1 7.07 Grad/s10 nH 2 pFTLC

2 pFTC

221 2

0.04 32 7.07107 Grad/s 2 pF 10 pF

ms

gr

C C

1 1 2.20977.07107 Grad/s 32 2 pFs T

Qr C

2 2par 1 32 1 2.2097 188 sr r Q

0 1.1254 GHzf

par 2

2

2 pF 1.66 pF1 1 1 2.20971

sCC

Q

par

1 1 7.7615 Grad/s10 nH 1.66 pFLC


Negative Resistance of Gm Oscillator

• Assume that both transistors are biased identically, then gm1 = gm2 , re1 = re2 , vπ1 = vπ2 , and solve for Zi = vi /ii .

• Input impedance:

• Necessary condition for oscillation:

where Rp is the equivalent parallel resistance of the resonator.

1 1 2 21 2

ii m m

e e

vi g v g v

r r

2i

m

Zg

2m

p

gR

ii

iv1 1mg v

1v

2v

1er

2er

2 2mg v


Minimum Current for Oscillation (I)

• Using a 5-nH inductor with Q = 5 and assuming no other loading on the resonator, determine the minimum current required to start the oscillations of 3 GHz if a Colpitts oscillator is used or if a –Gm oscillator is used.

To find the minimum current, we find the maximum rneg by taking the derivative with respect to C1.

The maximum obtainable negative resistance is achieved when the two capacitors are equal in value, C1 = C2 = 1.1258 pF, and twice the Ctot.

22

1 1 562.9 fF2 3 GHz 5 nH

totosc

CL

1 2

1 2tot

C CCC C

12

1

tot

tot

C CCC C

neg 2 2 2 21 2 1 1

m m m

tot

g g grC C C C C

neg2 2 2 3

1 1 1

2 0m m

tot

dr g gdC C C C

1 2 totC C


Minimum Current for Oscillation (II)

Now the loss in the resonator at 3 GHz is due to the finite Q of the inductor. The series resistance of the inductor is

Therefore, rneg = rs = 18.85 Ω. Noting that gm = Ic /vT ,

In Gm oscillator, there is no capacitor ratio to consider. The parallel resistance of the inductor is

A Gm oscillator can start with half as much collector current in each transistor as a Colpitts oscillator under the same loading conditions.

2 3 GHz 5 nH18.85

5sLr

Q

2 221 2 neg 2 3 GHz 1.1258 pF 25 mV 18.85 212.2 AC TI C C v r

2 3 GHz 5 nH 5=471.2 pR LQ

m C Tg I v 2 2 25 mV 471.2 106.1 AC T pI v R


Basic Differential Topologies

• Take two single-ended oscillators and place them back to back.

1C1C

CCV

1Q 2Q

2 2C

biasV

biasI biasI

L

CCVCCV

1Q 2QL

1C 1C

2 2C

biasI biasI

CCV

L

C

1Q 2Q

biasI

Copitts CB Copitts CC Gm


Modified CC Colpitts with Buffering

• Oscillators are usually buffered (use emitter follower) in order to drive a low impedance. Any load that is a significant fraction of the Rp of the oscillator would lower the output swing and increase the phase noise.

• CC oscillator is modified slightly by placing resistors in the collector. The output is then taken from the collector. Since this is a high-impedance node, the resonator is isolated from the load. However, the addition of these resistors will also reduce the headroom available to the oscillator.

CCV

L

1C

1Q 2Q

biasI

1C

biasI2 2C

LR LR

CCV


Several Refinements to the Gm Topology (I)

• Decouple the base from the collector with capacitors to get larger swings.

• The bases have to be biased separately. • Rbias have to be made large to prevent loss

of signal at the base. However, these resistors can be a substantial source of noise.

biasV

L

C

1Q2Q

biasI

biasR

CCV

biasV

biasR

cpC cpC


Several Refinements to the Gm Topology (II)

1Q 2Q

pL

CCV

CsL

biasV

biasI

• Use a transformer to decouple the collectors from the bases.

• Since the bias can be applied through the center tap, no need for the RF blocking.

• A turns ratio of greater than unity is chosen, there is the added advantage that the swing on the base can be much smaller than the swing on the collector to prevent transistor saturation.


Several Refinements to the Gm Topology (III)

• Since the tail resistor is not a high impedance source, the bias current will vary dynamically over the cycle of the oscillation (highest when voltage peaks and lowest during the zero crossings).

• Since the oscillator is most sensitive to phase noise during the zero crossings, this oscillator can often give very good phase noise performance.

biasV

L

C

1Q2Q

tailR

biasR

CCV

biasV

biasR

cpC cpC


Time

Amplitude

1ci t 2ci t

AVEIdcI

27/60

• Using a noise filter in the tail can lead to a very low-noise bias, thus low-phase-noise designs.

• Another advantage is that, before startup, the transistor Q3 can be biased in saturation, because during startup the 2nd harmonic will cause a dc bias shift at Q3 collector, pulling it out of saturation and into the active region.

• Since 2nd harmonic cannot pass through Ltail, there is no ‘‘ringing’’ at Q3 collector, further reducing its headroom requirement.

biasV

L

C

1Q2Q

tailL

biasR

CCV

biasV

biasR

cpC cpC

3QtailCbiasV


Several Refinements to the Gm Topology (IV)

28/60

The Effect of Parasitics on the Frequency

• The first task in designing an oscillator is to set the frequency of oscillation and hence set the value of the total inductance and capacitance in the circuit.

• To increase output swing, it is usually desirable to make the inductance as large as possible (this will also make the oscillator less sensitive to parasitic resistance). However, it should be noted that large monolithic inductors suffer from limited Q. In addition, as the capacitors become smaller, their value will be more sensitive to parasitics.


Oscillating Frequency Summary

1 2 1

1 2

1osc

C C C CL CC C C

1 2 2

1 2

1osc

C C C CL CC C C

1

22

oscCL C C

1C

2CL

1Q1C

2C

1Q

L


CB CC Gm

C L

1Q

2Q

30/60

• VCO is an oscillator of which frequency is controlled by a tuning voltage.

• VCO is a simple frequency modulator

Voltage Controlled Oscillator (VCO)

Vtunevcof

tuneV

tuneV


tuneV

oscs t

31/60

Making the Oscillator Tunable

• Varactors in a bipolar process can be realized using either the base-collector or the base-emitter junctions or else using a MOS varactor in BiCMOS processes.

CCV

CCV

LL

1C 1Q 2Q 1C

R

1BR

2BR

varC varC

CBSubs

CBSubs

Tuning port

CCV

biasIL

varCvarCconR

conV

1Q 2Q

CCV

biasI

L

varCvarC

LR

conV

1Q 2Q

CCV

LR

1C

biasI

1C


• Frequency Range• Frequency tuning characteristics

Tuning sensitivity (Hz/V) : Linearity

VCO Sensitivity and Tuning Linearity

VK f V

vcof

tuneV,0tV

0f

maxf

minf,mintV ,maxtV

vf

Ideal (perfect)Piecewise goodPiecewise good

Poor


Important Figures

• Output power (50 Ohm)• Frequency stability: frequency drifting• Source pushing and load pulling figures• Harmonics• Phase noise in frequency-domain (or Jitter in time-domain)


Small-Signal Simulation – Use OscTest

• It is based on small-signal operation and only for prediction.• When the simulation fails, try to reduce the value of Z in the

OscTest simulator (do not use 1 or 0, there would be a problem of convergence, lower impedance values usually seem to work better) or to reverse OscTest direction.

VB

VoutVE

VE VEVres

1.8 GHz Voltage-Controlled OscillatorS-PARAMETER OSCTEST for Loop Gain

LL2

R=L=2 nH

LR1

R=422L=100 nH

V_DCSRC2Vdc=-5 V

V_DCSRC3Vdc=12 V

LR2

R=681-RbiasL=100 nH

RR3R=50 Ohm

CC2C=1000 pF

I_P robeICC

CC1C=10 pF

ap_dio_MV1404_19930601D1

LL1

R=L=1000 nHV_DC

SRC1Vdc=4.0 V

OscTestOscTicklerZ=1.1 OhmStart=0.5 GHzStop=4.0 GHzPoints=201

VARVAR1Rbias=50

EqnVar

RR4R=Rbias

pb_hp_AT41411_19921101Q2

Resonator Active Part(include load network)

Varactor: Voltage-controlled capacitor

OscTest

OscTest is a controller base on S-parametersimulation to determine if the circuit oscillates.


Small-Signal Simulation – Oscillating Condition

• S(1,1) is the predicted loop gain by OscTest. By showing it on the polar plot, you can find that the locus goes beyond the circle with radius of 1 (S11>1) 。

• The blue point is (1+j0), which is the target when steady oscillating occurs.

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2-1.4 1.4

freq (500.0MHz to 4.000GHz)

S(1,1

)

Readout

m1

m1freq=S(1,1)=1.172 / 0.975

1.410GHz

Setup the dataset named: osc_test, and datadisplay named: osc_basics.

Show S(1,1) ona Polar-plot

When the x-axis value of1.0 is circled by thetrace(because S11 > 1), itmeans that the circuitoscillates. This is thepurpose of the OscTestcomponent.

S11 > 1


Small-Signal Simulation – Oscillating Condition

• S(1,1)=1 25o @885 MHz• S(1,1) > 1 above 885 MHz• S(1,1)=1.1 0o @1.445 GHz• S(1,1)=1.08 6.6o @1.8 GHz (Target frequency)

1.0 1.5 2.0 2.5 3.0 3.50.5 4.0

-20

-10

0

10

20

30

-30

40

freq, GHz

phas

e(S(

1,1))

Readout

m4

Readout

m5

m4freq=phase(S(1,1))=0.005

1.445GHzm5freq=phase(S(1,1))=-6.604

1.795GHz

1.0 1.5 2.0 2.5 3.0 3.50.5 4.0

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.5

1.3

freq, GHz

mag

(S(1

,1))

885.0M1.013

m2

3.982G1.009

m3

m2freq=mag(S(1,1))=1.013

885.0MHzm3freq=mag(S(1,1))=1.009

3.982GHz

Around 1.8 GHz (Marker m5), the phase is not 0o, but this is OK atthis time. The harmonic-balance simulation will be performed later.

S11 > 1 above 880 MHzThe device is unstable and has a chance to oscillate.

Possibility!


Large-Signal Simulation

• Harmonic-Balance (HB)

VEVE VEVres

VB

HarmonicBalanceHB1

OscPortName="Osc1"OscMode=yesStatusLevel=2Order[1]=7Freq[1]=1.0 GHz

HARMONIC BALANCE

OscPortOsc1

MaxLoopGainStep=FundIndex=1Steps=10NumOctaves=2Z=1.1 OhmV=

V_DCSRC1Vdc=4.0 V

LL1

R=L=1000 nH

ap_dio_MV1404_19930601D1

CC1C=10 pF

LL2

R=L=2 nH

LR1

R=422L=100 nH

V_DCSRC2Vdc=-5 V

pb_hp_AT41411_19921101Q2

OscPort

Enable the oscillation analysiswith “Use Oscport” method.

Oscport HB simulationattempts to find the correctoscillating frequency usingloop gain and current(Barkhausen’s Criteria).

3


Setting Up the Parameters

• V:

It is the initial voltage. Leave it when you don’t know the initial value, the HB will run AC analysis to get that.

• NumOctaves:

The frequency range in which you want to search the oscillating condition. In this example, Freq[1] = 1 GHz, and NumOctaves = 2. This means that the frequency range is from 0.5 GHz to 2 GHz.

• Steps:

It is set to show how many points you like to run the prediction with in the range per octave. In this example, the simulator use 20 points from 0.5 GHz to 2 GHz to search the condition. If you are designing a high-Q oscillator, the step should be finer.

• FundIndex

FundIndex = 1 means that the oscillating frequency Freq[1] is found by OscPort prediction, but not as your preset Freq[1] = 1.0 GHz. You should tell OscPort that which frequency to predict by using the frequency index.

• HB Simulator Settings:

Usually, we use the order of harmonicas equal to 3, 7, 15, 31. When the DC term is included, the data memory would be 4, 8, 16, 32, that are numbers by 2N and they are good for computation. StatusLevel = 3 to show more information when the simulation is running, and turn on the OscMode while the OscPortName is assigned to the OscPort name.


VEVE VEVres

VB

HarmonicBalanceHB1


HARMONIC BALANCE

OscPortOsc1


V_DCSRC1Vdc=4.0 V

LL1

R=L=1000 nH

ap_dio_MV1404_19930601D1

CC1C=10 pF

LL2

R=L=2 nH

LR1

R=422L=100 nH

V_DCSRC2Vdc=-5 V

pb_hp_AT41411_19921101Q2

VEVE VEVres

VB

HarmonicBalanceHB1


HARMONIC BALANCE

OscPortOsc1


V_DCSRC1Vdc=4.0 V

LL1

R=L=1000 nH

ap_dio_MV1404_19930601D1

CC1C=10 pF

LL2

R=L=2 nH

LR1

R=422L=100 nH

V_DCSRC2Vdc=-5 V

pb_hp_AT41411_19921101Q2

39/60

Simulated Results

• freq[1] is the oscillating frequency, which is 1.806 GHz in the example.

• Use dBm( ) function to show the spectral values.

Eqn loop_current=real(ICC.i[0])

Eqn osc_freq=freq[1]loop_current

-0.011osc_freq

1.806E9

m6harmindex=dBm(Vout)=7.318

1

1 2 3 4 5 60 7

-30

-20

-10

0

-40

10

harmindex

dBm

(Vou

t)

17.318

m6

m6harmindex=dBm(Vout)=7.318

1

harmindex01234567

freq0.0000 Hz1.806 GHz

3.611 GHz5.417 GHz7.222 GHz9.028 GHz10.83 GHz12.64 GHz

harm_power<invalid>7.318

-2.208-17.501-17.061-27.317-27.815-35.340

Eqn harm_power=dBm(Vout[0::1::7])

2 4 6 8 10 120 14

-30

-20

-10

0

-40

10

freq, GHz

dBm

(Vou

t)

Fundamental Frequency (oscillation frequency)

Use dBm( ) to show the signal power(Note: x-axis is “harmonic index”)

Use plot_vs( )to show the signalpower versus frequency.(Note: x-axis is now “frequency”)


Simulated Results

• Use ts( ) function to show the time-domain waveform

-600-500-400-300

-700

-200

ts(Vr

es),

mV

-400-200

0200

-600

400ts(

VB),

mV

-600-500-400-300

-700

-200

ts(VE

), m

V

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.10.0 1.2

-0.5

0.0

0.5

-1.0

1.0

time, nsec

ts(Vo

ut), V


Tuning Sensitivity: KV (MHz/V)

Vres

HarmonicBalanceHB2

Step=Tune_StepStop=Tune_StopStart=Tune_StartSweepVar="Vtune"OscPortName="Yes"OscMode=yesStatusLevel=3Order[1]=7Freq[1]=1.8 GHz

HARMONIC BALANCE

VARVAR2

Tune_Step=0.25Tune_Stop=10Tune_Start=0Vtune=4 VRbias=50

EqnVar

HarmonicBalanceHB1


HARMONIC BALANCE

V_DCSRC1Vdc=Vtune

OscPortOsc1


LL1

R=L=1000 nH ap_dio_MV1404_19930601

D1

CC1C=10 pF

Pass the variable “Tune_Step” to dataset Plot oscillating frequency v.s. Tuning voltage

“Osc1”


We already know the oscillating frequency is around 1.8 GHz by previous simulation.

Sweep the tuning voltage of the varactor.

42/60

Simulated Results

Eqnosc_freq=freq[1]

m7indep(m7)=plot_vs(freq[1], Vtune)=1.806E9

4.000m8indep(m8)=plot_vs(freq[1], Vtune)=1.903E9

6.500

1 2 3 4 5 6 7 8 90 10

1.75

1.80

1.85

1.90

1.95

2.00

2.05

1.70

2.10

Vtune

freq[1

], GH

z

4.0001.806E9

m7

6.5001.903E9

m8



6.500

EqnTuning_Sensitivity=diff(freq[1])/Tune_Step[0]

1 2 3 4 5 6 7 8 90 10

6.0E7

8.0E7

1.0E8

1.2E8

1.4E8

1.6E8

4.0E7

1.8E8

Vtune

Tunin

g_Se

nsitiv

ity

1.75E9 1.80E9 1.85E9 1.90E9 1.95E9 2.00E91.70E9 2.05E9

6.0E7

8.0E7

1.0E8

1.2E8

1.4E8

1.6E8

4.0E7

1.8E8

osc_freq[0::1::(tune_pts-1)]

Tunin

g_Se

nsitiv

ity

Eqnf_pts=sweep_size(osc_freq)

f_pts41

tune_pts40

Eqntune_pts=sweep_size(Tuning_Sensitivity)

EqnTuning_Sensitivity_band=(m8-m7)/(indep(m8)-indep(m7))Tuning_Sensitivity_band

3.904E7m7

1.806E9m8

1.903E9

Oscillating frequency v.s. Tuning voltage Calculate tuning sensitivity frommakers m7 and m8

Calculate sensitivity by usingdiff() function.Note: Since no “padding” with diff(),there will be 1 point less than freq[1]points.

Sensitivity v.s. Vtune Sensitivity v.s. Frequency


Over-tuned : Varactor Breakdown

VARVAR2

Tune_Step=0.25Tune_Stop=18Tune_Start=0Vtune=4 VRbias=50

EqnVar

2 4 6 8 10 12 14 160 18

1.7

1.8

1.9

2.0

2.1

1.6

2.2

Vtune

freq[

1], G

Hz

4.0001.806E9

m7

12.0002.134E9

m8



12.000

Sweep Vtune up to 18 V

The diode is breakdownabove 12 V (acts like aresistor), it no longer actslike a variable capacitor.

Diode = Varactor

Maximum oscillatingfrequency is 2.13 GHz


Source Pushing

• Sweep the supply voltage from 5 V to 20 V with a 0.25 V step.

Vres

VARVAR2

Tune_Step=0.25 VTune_Stop=20 VTune_Start=5 VVtune=4 VVbias=12 VRbias=50

EqnVar

HarmonicBalanceHB2

Step=Tune_StepStop=Tune_StopStart=Tune_StartSweepVar="Vbias"OscPortName="Yes"OscMode=yesStatusLevel=3Order[1]=7Freq[1]=1.8 GHz

HARMONIC BALANCE

HarmonicBalanceHB1


HARMONIC BALANCE

V_DCSRC1Vdc=Vtune

LL1

R=L=1000 nH

ap_dio_MV1404_19930601D1

CC1C=10 pF

Vout

V_DCSRC3Vdc=Vbias

LR2

R=681-RbiasL=100 nH

RR3R=50 Ohm

CC2C=1000 pF

I_ProbeICC

Change the supply voltageto a variable “Vbias”Sweep the supply voltage “Vbias” from 5 V to

20 V while Vtune is now held constantly at 4 V.(In practice, Vtune is set to a voltage that oscillator oscillatesat “target” center frequency.)


Simulated Results

• Source pushing is measured around the normal supply voltage (12 V in this example). This example shows that the source pushing figure is 21.77 MHz/V.

m9indep(m9)=plot_vs(freq[1], Vbias)=1.825E9

13.000m10indep(m10)=plot_vs(freq[1], Vbias)=1.781E9

11.000

6 8 10 12 14 16 184 20

0.5

1.0

1.5

0.0

2.0

Vbias

freq[

1], G

Hz

13.0001.825E9

m9

11.0001.781E9

m10

m9indep(m9)=plot_vs(freq[1], Vbias)=1.825E9

13.000m10indep(m10)=plot_vs(freq[1], Vbias)=1.781E9

11.000

Eqn Source_pushing=(m9-m10)/(indep(m9)-indep(m10))

Source_pushing2.177E7

Plot freq[1] v.s. Vbias toshow the source pushingresults. Here, use makersand equations to calculatethe pushing figure aroundVbias = 12 V. As we can see,this oscillator has the sourcepushing figure equals to21.77 MHz/V.


Load Pulling

• Frequency pulling figure illustrates the frequency variation subjection to load impedance (normally, the load impedance is 50 Ω).

Vout VARVAR1

VSWRval=1phi=0nvw=11vw2=2vw1=1

EqnVar

HarmonicBalanceHB3

Step=0.1Stop=2Start=0SweepVar="phi"OscPortName="Y es"OscMode=yesStatusLevel=3Order[1]=7Freq[1]=1.8 GHz

HARMONIC BALANCE

VARVAR7

rho=(VSWRval-1)/(VSWRval+1)iload=rho*sin(pi*phi)load=rho*exp(j*pi*phi)rload=rho*cos(pi*phi)

EqnVar

ParamSweepSweep1

Lin=nvwStop=vw2Start=vw1SweepVar="VSWRval"

PARAMETER SWEEP

S1P_EqnBuff erLoadS[1,1]=load

CC2C=1000 pF

vw1: VSWR sweep startvw2: VSWR sweep stopnvw: num. of VSWR sweep

real part of loadsweep loadImage part of load

Sweep load for different constant VSWR circles in Smith chart.

Save these variables in dataset


Load Pulling

• Move maker m12 to change VSWR. In this example, we observed the frequency variation corresponding to VSWR=1.2.

• Find the peak frequency change to 1.806 GHz (df_peak).

m12indep(m12)=vs([0::sweep_size(VSWRval)-1],VSWRval)=2.000

1.200

Eqn refl=rload+j*iloadEqn vswr_k=(nvw[0,0]-1)*(indep(m12)-vw1[0,0])/(vw2[0,0]-vw1[0,0])Eqn VSWR=vswr_k*(vw2[0,0]-vw1[0,0])/(nvw[0,0]-1)+(vw1[0,0])Eqn LoadRefl=mag(refl[::,1])Eqn df_peak=max(abs(freq[vswr_k,::,1]-1.806e9))

df_peak3.202E7

Load Pulling Figure @ VSRW=1.200

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.91.0 2.0VSWR

1.2002.000

m12


1.200

Write down these equations for load pulling figure measurement@certain VSWR value. (You can change VSWR by scrolling marker m12)

Find peak frequency that deviatesfrom center frequency 1.086 GHz.

phi (0.000 to 2.000)

refl[v

swr_

k,::]


1.200

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.91.0 2.0VSWR

1.2002.000

m12


1.200

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0

0.65

0.70

0.75

0.80

0.85

0.60

0.90

phi ( *pi radians)

mag

(Vou

t[vsw

r_k,:

:,1])

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0

1.7800G

1.7900G

1.8000G

1.8100G

1.8200G

1.8300G

1.7700G

1.8400G

phi ( *pi radians)

freq[v

swr_

k,::,1

], Hz

Eqnrefl=rload+j*iloadEqnvswr_k=(nvw[0,0]-1)*(indep(m12)-vw1[0,0])/(vw2[0,0]-vw1[0,0])EqnVSWR=vswr_k*(vw2[0,0]-vw1[0,0])/(nvw[0,0]-1)+(vw1[0,0])EqnLoadRefl=mag(refl[::,1])

Frequency variation for VSWR = 1.20

Eqndf_peak=max(abs(freq[vswr_k,::,1]-1.806e9))

df_peak3.202E7

Load Pulling Figure @ VSRW=1.200

Constant VSWR circleVout amplitude variations

Frequency variationsuse @VSWR in the text to show the number


Oscillator Phase Noise

V f

f1f

V f

f1f

v t

t

1

1f

v t

t

1

1f

Time Domain Frequency Domain


Jitter Phase noise

mf

49/60

Phase Disturbance Due to Thermal Noise (I)

• Modeling the noise with the phasor diagram

nP

sP

sP

Phase disturbance

Amplitude disturbance

FkTB

avsP

Noise-free amplifier

f0f 0 mf f

1 Hz1 Hz 1nRMSFkTV

R2nRMS

FkTVR

avsavsRMS

PVR

The input phase noise in a 1-Hz bandwidth at any frequency from the carrier produces a phase deviation.

0 mf f


Phasor Diagram

50/60

avsRMS avsV P R

FkTR FkTR

(noise from )

Phase Disturbance Due to Thermal Noise (II)

• RMS phase deviation

avsavsRMS

nRMSpeak P

FkTVV

1

avsRMS P

FkT2

11

avsRMS P

FkT2

12

2 2 1 2RMS total RMS RMS

avs

FkTP

m

12 nRMSV

2 avsRMSVpeak

(total phase deviation)

02 cososc avsRMSv t V t t


mf(noise from )

mf

51/60

Lesson’s Phase Noise Model (I)

• The spectral density of phase noise :

Due to Thermal Noise

Consider Flicker Noise (modeled)

2m RMS

avs

FkTBS fP

1)(B dBm/Hz 174 kTB

(due to theoretical noise floor of the amplifier)

1)(B 1)(

m

c

avsm f

fP

FkTBfS

noise floor flicker noise

mS f

Noise-free amplifierPhase modulatoravs

FkTBP

mf

mS f

cf


Lesson’s Phase Noise Model (II)

• The oscillator may be modeled as an amplifier with feedback

0

121

mL m

LQj

220 B

QL

012out m in m

L m

f fj Q

2

0 ,2

112out m in m

m L

fS f S ff Q

, 1 cin m

avs m

FkTB fS fP f


Noise-free amplifier

Phase modulator

,in mS f

Output

Feedback

Resonator

Resonator equivalent low-pass

in mf

0

2 in mL m

fj Q

out mf

mL

53/60

Lesson’s Phase Noise Model (III)

• Lesson’s phase noise model:

2

0 2

1 11 ( )2 2m in m

m L

fL f S ff Q

, 1 c

in mavs m

FkTB fS fP f

Open-loop


Closed-loop w/ Resonator

22

3 2 2

1 1 12 4 2

o c o cm

avs m L m l m

FkTB f f f fL fP f Q f Q f

Up-convert 1/f noise

Thermal FM noise Flicker noiseThermal noise floor

54/60

Lesson’s Phase Noise Model (IV)


Low-Q oscillator

Phase perturbation

1mf

3mf

2mf

0mf

mf

mf

Resulting phase noise

cf

cf 0 2f Q

High-Q oscillator

Phase perturbation

1mf

1mf

0mf

3mf

mf

mf

Resulting phase noise

cf

cf0 2f Q

55/60

Design Example of Phase Noise Limits (I)

• A 5-GHz receiver including an onchip phase-locked loop (PLL) is argued to be implemented with the VCO requirements: 1.8V supply, <1 mW DC power, and phase noise performance of 105 dBc/Hz at 100-kHz offset. It is known that, in the technology to be used, the best inductor Q is 15 for a 3-nH device. Assume that capacitors or varactors will have a Q of 50.

Assume a Gm topology will be used: 2 5 GHz 3 nH 15 1413.7 pr L LQ Parallel resistance due to the inductor:

Required capacitance: 22

1 1 337.7 fF2 5 GHz 3 nH

totosc

CL

50 4712.9

2 5 GHz 337.7 fFptot

Qr CC

Parallel resistance due to the capacitor:

Equivalent parallel resistance of the resonator is 1087.5 Ω

Current limit: 1.8-V VCC and PDC< 1 mW: 555.5 μA

Peak voltage swing:

tank2 2 555.5 A 1087.5 0.384 Vbias pV I R


Design Example of Phase Noise Limits (II)

Assume all low-frequency upconverted noise is small and active devices add no noise to the circuit (F=1), we can now estimate the phase noise.

22tank 0.384 V

67.8 W2 2 1087.5 RF

p

VPR

337.7 fF1087.5 11.533 nH

totp

CQ RL

This is 98.5 dBc/Hz at 100-kHz offset, which is 6.5 dB higher than the promised performance. Thus, the specifications given to the customer are most likely very difficult. This is an example of one of the most important principles in engineering.

RF output power:

Oscillator Q:

222 2310

3 2 2

1.12 2 5 GHz1 1 1 1.38 10 J/K 298 K 1 Hz100 kHz 1 1.79 102 4 2 2 67.8 W 2 11.53 2 100 kHz

o c o c

avs m L m l m

FkTB f f f fLP f Q f Q f


~ 0 far from carrier

97.5 dBc Hz@100 kHz offset

dominant around carrier

57/60

1.4

1

98.5

Phase Noise Simulation

HarmonicBalanceHB1

OscPortName="Osc1"OscMode=yesSortNoise=Sort by valueNoiseNode[1]="Vout"PhaseNoise=yesNLNoiseDec=5NLNoiseStop=10.0 MHzNLNoiseStart=1.0 HzOversample[1]=4StatusLevel=3Order[1]=15Freq[1]=1.8 GHz

HARMONIC BALANCE

Phase Noise Simulation Setup

7 in most cases

Agilent suggests

Turn onTurn on

Set noise (1) Set noise (2)


Simulated Results

• Plot the “pnmx” (PSD of the phase noise).• This oscillator has the phase noise = 78.39 dBc/Hz@10 kHz,

98.34 dBc/Hz@100 kHz, and 118.08 dBc/Hz@1 MHz 。m11noisefreq=pnmx=-78.390

10.00kHz

m13noisefreq=pnmx=-98.340

100.0kHz


1.000MHz

1E1 1E2 1E3 1E4 1E5 1E61 1E7

-120

-100

-80

-60

-40

-20

0

-140

20

noisefreq, Hz

pnmx

, dBc

Readout

m11

100.0k-98.34

m13

Readout

m14


10.00kHz


100.0kHz


1.000MHz


Summary

• In this presentation, few kinds of popular oscillator topologies were introduced. The CB and CC configurations are good for high frequency operation while the CE is good for high power application and has good buffering characteristics.

• The active device is configured as feedback loop to provide a negative resistance for resonator.

• For a voltage-controlled frequency application, an oscillator is usually designed with variable capacitors, or varactors, to provide frequency-tuning capability.

• Lesson’s phase noise model gives an intuitive way to understand the behavior of the phase noise generated from the oscillator.
