嵌入式系统讲义第 4 章 S3C2410X 系统结构

4 S3C2410X

2007.3

23571012

1S3C2410X2S3C2410X3S3C2410X4S3C2410XFlash5S3C2410XDMA6S3C2410XA/D7S3C2410XA/D0100A/DA/DAIN0---AIN9

8S3C2410X9S3C2410XIRQCPU10EINT0CC1#define rGPCDAT (*(volatile unsigned *)0x56000024)2int *rGPCDAT=0x56000024;3int *rGPCDAT; rGPCDAT=0x56000024;11S3C2410X

12timer010KHz1/2f pclk=50MHztimer013S3C2410XPWMtimer110KHzf pclk=50MHztimer0t0 2*t0 tv0

4 S3C2410X

4.1 S3C2410X4.2 4.3 DMA4.4 ADC4.5 4.6 I/O4.7 PWM4.8 UART4.9 RTC4.10 IIC4.11 SPI4.124.134.14

4.14

1 USB2 LCD3 SD4 IIS

4.1 S3C2410X

4.1 S3C2410XS3C2410X16/32RISCCPUARM920T

16KBCache 16KBCacheMMU8128MB1GBNand flash

551244DMA3UART16TX/RX FIFOIrDA1.02SPI1IIC1IIS2USB1USB4PWM16116810A/D500kB/s117I/O24

MMCSDRTCLCD4KSTN256KTFTDMAPLL203MHz1.8/2.0V3.3VI/O

ARM920T

1ARM920T

ARM9ARM9TDMI32KBCacheMMU

2AHBAPB

S3C272-FBGAaddr0---addr26Data0---data31GPA0---GPA22GPB10GPC15GPD15GPE15GPF7GPG15GPH10EINT23nGCS0nGCS7AIN7IICSPIOM0---OM3

4.2 S3C2410X

FlashFlash

4.2 4.2.1 S3C2410X

S3C2410X26328/S3C2410X81GBbank0---bank5128MBbank6bank7248163264128MBbank7bank6bank0ROM1632OM0OM181632S3C2410X

S3C2410X139

1STnnUB/LB1UB/LBnBE[30]0UB/LBnWBE[30]WSn/nWAIT1WAIT0WAITDWnn0080116103211

TacsnGCSn000011102114TcosnOE000011102114Tacc00010012010301141006101811010111142BANKn---n=0--5

TcohnOE000011102114Tcah nGCSn000011102114Tacp002013104116PMC001014108111600

0x0700

MT00ROMSRAM[30]TacpPMC11SDRAM [30]TrcdSCAN 0110Trcd002013104 SCAN0080191010 3BANK6/7---6/7

14131211109876543210TacsTcosTaccTcohTcahTacp/TrcdPMC/SCAN

31171615MT

REFEN10TREFMD10TrpSDRAM002013103114TsrcSDRAM004015106117 SDRAM= Trp + TsrcRefresh_count4REFRESH---

1514131211109876543210 Refresh_count

31242322212019181716 REFENTREFMDTrpTsrc

Refresh_count=211- Refresh_count+1/HCLK=15.6sHCLK=60MHz=211+1-6015.6=11131113=0x459=0b10001011001

24BURST_ENARM01SCKE_ENSCKESDRAM01SCLK_ENSCLKSDRAMSCLK0SCLK1SCLKBK76MAPBANK6/75BANKSIZE---BANK6/7

76543210BURST_ENXSCKE_ENSCLK_ENXBK76MAP

BK76MAPBANK6/71002MB1014MB1108MB 11116MB00032MB00164MB010128MB

WBL01TM00CL000101020113BT01BL00016MRSRB6/7---BANK6/7

1514131211109876543210WBLTMCLBTBL

4.2.2 Nand Flash

1Nand Flash234

4.2.2 Nand FlashNor flash Nand flashNor flashNand flashSDRAM

Nand Flash

S3C2410XNand flashSteppingstone SRAM Nand flash4KByte SDRAMNand flashS3C2410XECCNand flash

Nand Flash

Nand Flash//Nand flash Steppingstone Steppingstone ECC4KBSRAMSteppingstoneNand flash

Nand Flash 6CLER/nB /

Nand Flash

NFCON0x4E000000Nand Flash/-NFCMD0x4E000004Nand Flash/-NFADDR0x4E000008Nand Flash/-NFDATA0x4E00000CNand Flash/-NFSTAT0x4E000010Nand Flash/-NFECC0x4E000014Nand Flash/-

NFENNF01IECCECC/0ECC1ECCNFCENFnFCE0 nFCE0 nFCETACLECLE/ALE0---7 HCLK * (TACLS + 1)CLE/ALE /1NFCON---Flash

1514131211109876543210NFENXIECCNFCETACLEXTWRPH0XPWRPH10-000-0-0

TWRPH007 HCLK * (TWRPH01) TWRPH1CLE/ALE07 HCLK * (TWRPH11)2NFCMD---Flash

1514131211109876543210

2483NFADDR---Flash4NFDATA---Flash248Flash

1514131211109876543210

1514131211109876543210 /

RnBNand Flash015NFSTAT---Flash6NFECC---Flash

1514131211109876543210 RnB

1514131211109876543210#1#0

31302928272625242322212019181716 #2

Nand Flash

1 Nand flash4KSteppingstone SteppingstonenGCS0BANK0 CPUSteppingstone4-KB ECCNand flash4KB Nandflash

2Nand FLASH

NFCONFNand flashNand flashNFCMDNand flashNFADDRNFSTATNand flash R/nB/

3 Nand FLASH

OM[1:0] = 00bNand flash OM[30]bank0 OM[1:0] = 01b10bbank01632OM[1:0]=11bNand flash512 NCON Nand flash 0314

4Nand Flash

S3C2410A/5123ECC(24) 24 ECC 18 6

ECC MCUNandECCECC MCUNandECCECC ECC

4.3 DMA

123

S3C2410X4 DMA DMA 1 2 3 4 DMACPUDMA

DMA

1DMA

DMA4DMADMA 4-1 4-1 DMA

2DMA

DMA 1 DMAC 2DMACHOLD CPU 3CPUHLDA4DMACDMA 5DMAC6DMACHOLDCPUHLDA12453

2DMA

S3C2410XDMA1DMA DMA2DMA ACKINT REQ0 2DMA ACK1CURR_TCDCON[19:0]DMA ACK13DMACURR_TCDSTAT1CURR_TC0

CURR_TC0DMACINT REQDCON[29]1 DMA ACK CURR_TC0

DMAC3DMA REQDMA REQCURR_TC0

DMA4

3DMA/

DMAC3DMA/1single service demand2single service handshake3whole service handshakeDMADMAdemand handshakeDMAxnxDREQDMAdemandDMAxnxDREQhandshakeDMADMADMAxnxDACKDMADMA

4DMA

DMASetupdelay DMAsetupDMADMADMACPUDMADMA

DMA

DMA 9 4 36 6 DMA 3 DMA

1DISRCn---DMA

DMA10

3130 00S_ADDR---CURR_SRC0DMA ACK1CURR_SRC

LOC---0AHB1APBINC---012DISRCCn---DMA

R/W DISRCC0 0x4B000004 R/W DMA0 0x00000000 DISRCC1 0x4B000044 R/W DMA10x00000000 DISRCC2 0x4B000084 R/W DMA20x00000000 DISRCC3 0x4B0000C4 R/W DMA30x00000000

31 21 00LOC---INC---

3DIDSTn---DMA

DMA

R/W DIDST0 0x4B000008 R/W DMA0 0x00000000 DIDST1 0x4B000048 R/W DMA10x00000000 DIDST2 0x4B000088 R/W DMA20x00000000 DIDST3 0x4B0000C8 R/W DMA30x00000000

3130 00D_ADDR---CURR_DSTCURR_DST0 DMA ACK 1

LOC---0AHB1APBINC---014DIDSTCn---DMA

R/W DIDSTC0 0x4B00000C R/W DMA0 0x00000000 DIDSTC1 0x4B00004C R/W DMA10x00000000 DIDSTC2 0x4B00008C R/W DMA20x00000000 DIDSTC3 0x4B0000CC R/W DMA30x00000000

31 21 00LOC---INC---

5DCONn---DMA

313029282726252423222120DMD_HSSYNCINTTSZSERVMODEHWSRCSELSWHW_SELRELOADDSZ

1918171615141312111098876543210TC---

DMD_HS---DMA0DREQ1DREQ DREQSYNC---DREQ DACK0DREQDACKPCLK(APB clock) 1DREQDACKHCLK(AHB clock) INT---CURR_TC0CURR_TC1CURR_TC TSZ---0 1


SERVMODE---0DREQ1DREQ

HWSRCSEL ---DMA


HWSRCSEL0000010100111000nXDREQ0UART0SDITimerUSBEP11nXDREQ1UART1IISSDISPI0USBEP22IISSDOIISSDISDITimerUSBEP33UART2SDISPI1TimerUSBEP4

SWHW_SEL--- DMA0softwareDMADMASKTRIGSW_TRIG1[26:24]DMADMARELOAD---00DMA1DMADSZ---00011011


STAT---DMA0001DMA1XCURRTC---1DCONn206DSTATn---DMA/DMA

R/W DSTAT0 0x4B000014 RDMA0/ 0x00000000 DSTAT1 0x4B000054 RDMA1/0x00000000 DSTAT2 0x4B000094 RDMA2/0x00000000 DSTAT3 0x4B0000D4 RDMA3/0x00000000

21201918171615141312111098876543210STATCURRTC---

CURR_SRC--- 1DMA(124)2CURR_SRC0DMA ACK1S_ADDR7DCSRCn---DMA

R/W DCSRC0 0x4B000018 RDMA0 0x00000000 DCSRC1 0x4B000058 RDMA10x00000000 DCSRC2 0x4B000098 RDMA20x00000000 DCSRC3 0x4B0000D8 RDMA30x00000000

3130 00CURR_SRC---

CURR_DST---1DMA(124) 2CURR_DST0DMA ACK1D_ADDR8DCDSTn---DMA

R/W DCDST0 0x4B00001C RDMA0 0x00000000 DCDST1 0x4B00005C RDMA10x00000000 DCDST2 0x4B00009C RDMA20x00000000 DCDST3 0x4B0000DC RDMA30x00000000

3130 00CURR_DST---

9DMASKTRIGn---DMA(Mask)

R/W DMASKTRIG0 0x4B000020 R/WDMA0 0x00000000 DMASKTRIG1 0x4B000060 R/WDMA10x00000000 DMASKTRIG2 0x4B0000A0 R/WDMA20x00000000 DMASKTRIG3 0x4B0000E0 R/WDMA30x00000000

31 321 00STOPON/OFFSW_TRIG

STOP---DMA1DMACURR_TC0ON/OFFOFFDMAON/OFF---DMA01DCONn[22]DMASTOP1DMADMASTOPSW_TRIG DMA1DMADCONn[23]DMA

DMA

DMADISRCnDIDSTnDCONnTCDMA

4.4 A/D

1234

S3C2410XA/D

S3C2410X10 A/D A/D S3C2410XA/D A/D101LSB 1.5---2.0LSB500KSPS0~3.3v/X/Y

A/D

S3C2410 A/D 1

681A/D

3

1A/D PCLK 50MHz4910 A/D =50MHz /49+1=1MHz=1/1MHz/5 =1/200KHz=5usA/D 2.5MHz 500KSPS

23

XXPX+XMX-YPnYPON=1nYMON=0nXPON=0nXMON=1YX

YYPY+YMY-XPnYPON=0nYMON=1nXPON=1nXMON=0YX

3S3C24120X A/D

5X/YX/Y2---41A/DADCDAT0XPDATA2X/YX/YADCDAT0XPDATAADCDAT1YPDATAINT_ADC3X/YXYADCDAT0XPDATAADCDAT1YPDATAINT_ADC

4INT_TCX/YX/YXP=XM=YP=AIN[5]YM=5ADCCONSTDBM1A/D

ADC

5

Register Address R/W Description Reset Value ADCCON0x58000000 R/W ADC 0x3FC4 ADCTSC 0x58000004 R/W 0x058 ADCDLY0x58000008 R/W ADC0x00FF ADCDAT00x5800000CRADC0-ADCDAT10x58000010 RADC1-

ECFLG---01PRSCEN---01PRSCVL---N1---2551N+1 2N

SEL_MUX ---000AIN0001AIN1010AIN2011AIN3111AIN7STDBM---01A/DREAD_START---01ENABLE_START---01A/D0READ_START1

543210SEL_MUXSTDBMREAD_STARTENABLE_START

YM_SEN---YMON00YM=1 1YM=GNDYP_SEN---nYPON00YP=11YPAIN[5]XM_SEN---XMON00 XM=1 1XM=GNDXP_SEN---nXP00XP=11XPAIN[7]2ADCTSC---ADC

8765432100YM_SENYP_SENXM_SENXP_SENPULL_UPAUTO_PSTXY_PST

PULL---0XP1 XPAUTO_PST---XY0A/D1X/YXY_PST---XY0001X10X11

8765432100YM_SENYP_SENXM_SENXP_SENPULL_UPAUTO_PSTXY_PST

X/YX/Yms3ADCDLY---ADC

UPDOWN---01AUTO_PST---X/Y01X/YXY_PST---X/Y0001X10Y11XPDATA[90]XADC0---0x3FF4ADCDAT0---ADC011

1514131211109 0UPDOWNAUTO_PSTXY_PST0XPDATAADC

UPDOWN---01AUTO_PST---X/Y01X/YXY_PST---X/Y0001X11Y11YPDATA[90]10Y0---0x3FF 5ADCDAT1---ADC1

1514131211109 0UPDOWNAUTO_PSTXY_PST0YPDATA

3100x400000AREA ADCCODEREADONLYENTRYSTART

#define rADCCON (*(volatile unsigned *)0x58000000)#define rADCDAT0 (*(volatile unsigned *)0x5800000c)#define pref 49#define ch 3void adc(void){int adc_data[10], i; rADCCON=(1

S3C2410X5624DMAUARTIICS3C2410XARM920TIRQFIQCPU

S3C2410X

1

4

85

Register Address R/W Description Reset Value SRCPND0x4A000000 R/W 0x00000000 INTMOD 0x4A000004 R/W 0x00000000 INTMSK0x4A000008 R/W 0xFFFFFFFF PRIORITY0x4A00000CR/W 0x7FINTPND0x4A000010 R/W 0x00000000 INTOFFSET0x4A000014R0x00000000 SUBSRCPND0x4A000018R/W 0x00000000INTSUBMSK0x4A00001CR/W 0x7FF

1001.1SRCPND---

31INT_ADC23INT_UART115INT_UART27nBATT_FLT30INT_RTC22INT_SPI014INT_TIM4629INT_SPI121INT_SDI13INT_TIM35EINT8_2328INT_UART020INT_DMA312INT_TIM24EINT4_727INT_IIC19INT_DMA211INT_TIM13EINT326INT_USBH18INT_DMA110INT_TIM02EINT225INT_USBD17INT_DMA09INT_WDT1EINT12416INT_LCD8INT_TICK0EINT0

FIQIRQ1FIQ0IRQ2INTMOD---


103INTMSK---


4PRIORITY---ARB_SELn---n00REQ0, 1, 2, 3, 4, 5 01REQ0, 2, 3, 4, 1, 510REQ0, 3, 4, 1, 2, 5 11REQ0, 4, 1, 2, 3, 5ARB_MODEn---n0 1REQ0REQ5

31:21 12:11ARB_SEL24ARB_MODE420:19ARB_SEL610:9ARB_SEL13ARB_MODE318:17ARB_SEL58:7ARB_SEL02ARB_MODE216:15ARB_SEL46ARB_MODE61ARB_MODE114:13ARB_SEL35ARB_MODE50ARB_MODE0

10010SRCPND5INTPND---


INTPND1INTPNDSRCPNDINTPND006INTOFFSET---

INT_ADC31INT_UART123INT_UART215nBATT_FLT7INT_RTC30INT_SPI022INT_TIM4146INT_SPI129INT_SDI21INT_TIM313EINT8_235INT_UART028INT_DMA320INT_TIM212EINT4_74INT_IIC27INT_DMA219INT_TIM111EINT33INT_USBH26INT_DMA118INT_TIM010EINT22INT_USBD25INT_DMA017INT_WDT9EINT1124INT_LCD16INT_TICK8EINT00

7SUBSRCPND---1010

31:11 7INT_TXD23INT_RXD110INT_ADC6INT_RXD22INT_ERR09INT_TC5INT_ERR11INT_TXD08INT_ERR24INT_TXD10INT_RXD0

8INTSUBMSK---10

31:11 7INT_TXD23INT_RXD110INT_ADC6INT_RXD22INT_ERR09INT_TC5INT_ERR11INT_TXD08INT_ERR24INT_TXD10INT_RXD0

2410init.s

bResetHandler bHandlerUndef;handler for Undefined modebHandlerSWI;handler for SWI interruptbHandlerPabort;handler for PAbortbHandlerDabort;handler for DAbortb.;reservedbHandlerIRQ;handler for IRQ interrupt bHandlerFIQ;handler for FIQ interrupt12

LTORG ;HandlerFIQ HANDLER HandleFIQHandlerIRQ HANDLER HandleIRQHandlerUndef HANDLER HandleUndefHandlerSWI HANDLER HandleSWIHandlerDabort HANDLER HandleDabortHandlerPabort HANDLER HandlePabort

; MACRO$HandlerLabel HANDLER $HandleLabel;Label=IRQ , ( HandlerIRQ )$HandlerLabelsubsp,sp,#4stmfdsp!,{r0} ldr r0,=$HandleLabel ldr r0,[r0]str r0,[sp,#4]ldmfd sp!,{r0,pc}MEND

IRQIsrIRQ subspsp#4 ;reserved for PCstmfdsp!{r8-r9}

ldrr9=INTOFFSET;ldrr9[r9]ldrr8=HandleEINT0;addr8r8r9lsl #2ldrr8[r8]strr8[sp#8]ldmfdsp!{r8-r9pc}

;IntVectorTableHandleEINT0 # 4HandleEINT1 # 4HandleEINT2 # 4HandleEINT3 # 4HandleEINT4_7# 4HandleEINT8_23# 4HandleRSV6# 4HandleBATFLT # 4HandleTICK # 4HandleWDT# 4HandleTIMER0 # 4HandleTIMER1 # 4

S3C2410X117/AGPA23BGPB11/CGPC16/DGPD16/EGPE16/FGPF8/GGPG16/HGPH11/I/O

4

Register Address R/W Description Reset Value GPXCON0x560000x0 R/W X X GPXDAT 0x560000x4 R/W XX GPXUP0x560000x8 R/W XX RESERVED0x560000xCR/W X-

GPADAT

23[220]

1A 21A

Register Address R/W Description Reset Value GPACON0x56000000 R/W A 0x7FFFFF GPADAT 0x56000004 R/W A- RESERVED0x56000008 -A- RESERVED0x5600000C-A-

1A

:0 1 :0 122GPA22nFCE10GPA10ADDR2521GPA21nRSTOUT9GPA9ADDR2420GPA20nFRE8GPA8ADDR2319GPA19nFWE7GPA7ADDR2218GPA18ALE6GPA6ADDR2117GPA17CLE5GPA5ADDR2016GPA16nGCS54GPA4ADDR1915GPA15nGCS43GPA3ADDR1814GPA14nGCS32GPA2ADDR1713GPA13nGCS21GPA1ADDR1612GPA12nGCS10GPA0ADDR011GPA11ADDR26FCE:Flash

GPBDAT---11[100]GPBUP---B[100] 01

B/2B

Register Address R/W Description Reset Value GPBCON0x56000010 R/W B 0x0 GPBDAT 0x56000014 R/W B- GPBUP0x56000018 R/W B0x0RESERVED0x5600001C- B-

B

:00 01 10 1121,20GPB10nXDREQ0Reserved19,18GPB9nXDACK0Reserved17,16GPB8nXDREQ1Reserved15,14GPB7nXDACK1Reserved13,12GPB6nXBACKReserved11,10GPB5nXBREQReserved9,8GPB4TCLK0Reserved7,6GPB3TOUT3Reserved5,4GPB2TOUT2Reserved3,2GPB1TOUT1Reserved1,0GPB0TOUT0Reserved

GPCDAT---16[150]GPCUP---C[150] 01

C/3C

Register Address R/W Description Reset Value GPCCON0x56000020 R/W C 0x0 GPCDAT 0x56000024 R/W C- GPCUP0x56000028 R/W C0x0RESERVED0x5600002C- C-

C

000110110001101131,30GPC15VD715,14GPC7LCDVF229,28GPC14VD613,12GPC6LCDVF127,26GPC13VD511,10GPC5LCDVF025,24GPC12VD49,8GPC4VM23,22GPC11VD37,6GPC3VFRAME21,20GPC10VD25,4GPC2VLINE19,18GPC9VD13,2GPC1VCLK17,16GPC8VD01,0GPC0VEND

GPDDAT---16[150]GPDUP---D[150] 01[1512][110] D/4D

Register Address R/W Description Reset Value GPDCON0x56000030 R/W D 0x0 GPDDAT 0x56000034 R/W D- GPDUP0x56000038 R/W D0xF000RESERVED0x5600003C- D-

D

000110110001101131,30GPD15VD23nSS015,14GPD7VD1529,28GPD14VD22nSS113,12GPD6VD1427,26GPD13VD2111,10GPD5VD1325,24GPD12VD209,8GPD4VD1223,22GPD11VD197,6GPD3VD1121,20GPD10VD185,4GPD2VD1019,18GPD9VD173,2GPD1VD917,16GPD8VD161,0GPD0VD8

GPEDAT---16[150]GPEUP---E[150] 01 E/5E

Register Address R/W Description Reset Value GPECON0x56000040 R/W E 0x0 GPEDAT 0x56000044 R/W E- GPEUP0x56000048 R/W E0x0RESERVED0x5600004C- E-

E

000110110001101131,30GPE15IICSDA15,14GPE7SDDAT029,28GPE14IICSCL13,12GPE6SDCMD27,26GPE13SPICLK011,10GPE5SDCLK25,24GPE12SPISI09,8GPE4IISSDO23,22GPE11SPISO07,6GPE3IISSDI21,20GPE10SDDAT35,4GPE2CDCLK19,18GPE9SDDAT23,2GPE1IISSCLK17,16GPE8SDDAT11,0GPE0IISLRCK

GPFDAT---8[70]GPFUP---F[70] 01 F/6F

Register Address R/W Description Reset Value GPFCON0x56000050 R/W F 0x0 GPFDAT 0x56000054 R/W F- GPFUP0x56000058 R/W F0x0RESERVED0x5600005C- F-

F

0001101115,14GPF7EINT713,12GPF6EINT611,10GPF5EINT59,8GPF4EINT47,6GPF3EINT35,4GPF2EINT23,2GPF1EINT11,0GPF0EINT0

GPGDAT---16[150]GPGUP---G[150] 01[15:11] G/7G

Register Address R/W Description Reset Value GPGCON0x56000060 R/W G 0x0 GPGDAT 0x56000064 R/W G- GPGUP0x56000068 R/W G0xF800RESERVED0x5600006C- G-

GLCD-PEN:POWER_ENABLEnSS0:SPI0_SELECT

000110110001101131,30GPG15EINT23nYPON15,14GPG7EINT15SPICLK129,28GPG14EINT22YMON13,12GPG6EINT14SPISI127,26GPG13EINT21nXPON11,10GPG5EINT13SPISO125,24GPG12EINT20XMON9,8GPG4EINT12LCD-PEN23,22GPG11EINT19TCLK17,6GPG3EINT11nSS121,20GPG10EINT185,4GPG2EINT10nSS019,18GPG9EINT173,2GPG1EINT917,16GPG8EINT161,0GPG0EINT8

GPHDAT---11[100]GPHUP---H[100] 01

H/8H

Register Address R/W Description Reset Value GPHCON0x56000070 R/W H 0x0 GPHDAT 0x56000074 R/W H- GPHUP0x56000078 R/W H0x0RESERVED0x5600007C- H-

HUCLKUSB

:00 01 10 1121,20GPH10CLKOUT1Reserved19,18GPH9CLKOUT0Reserved17,16GPH8UCLKReserved15,14GPH7RXD2nCTS113,12GPH6TXD2nRTS111,10GPH5RXD1Reserved9,8GPH4TXD1Reserved7,6GPH3RXD0Reserved5,4GPH2TXD0Reserved3,2GPH1nRTS0Reserved1,0GPH0nCTS0Reserved

9

Register Address R/W Description Reset Value MISCCR0x56000080 R/W 0x10330 DCLKCON0x56000084 R/W D0x0

nEN_SCKE---SCLKSDRAM0 1nEN_SCLKx---SCLKxSDRAM0SCLKx= SCLK 1nRSTCON---nRSTOUT0nRSTOUT01nRSTOUT11MISCCR---

151413121110987USBSUSPND1 USBSUSPND0 CLKSEL1

3120191817160nEN_SCKE nEN_SCLK1 nEN_SCLK0 nRSTCON

65432 10CLKSEL0 USBPAD MEM_HZ_CONSPUCR_L SPUCR_H

USBSUSPND1---USB101USBSUSPND0---USB001CLKSEL1 --- CLKOUT1000MPLL CLK001UPLL CLK 010FCLK011HCLK100PCLK 101DCLK111xCLKSEL0 --- CLKOUT0000MPLL CLK001UPLL CLK 010FCLK011HCLK100PCLK 101DCLK011x

151413121110987USBSUSPND1 USBSUSPND0 CLKSEL1

USBPAD---USB0USB1USBMEM_HZ_CON---MEM0Hi-Z 1SPUCR_L---16[150]01SPUCR_H---16[3116]01

65432 10CLKSEL0 USBPAD MEM_HZ_CONSPUCR_L SPUCR_H

2DCLKCON---DDCLK1(0)CMP---DCLK1(0)mm< DCLK1(0)DIVm+1DCLK1(0)DIV-m DCLK1(0)DIV---DCLK1(0) DCLK1(0) frequency = source clock / ( DCLK1(0)DIV + 1 )

151211109876543210DCLK0CMPDCLK0DIVDCLK0SelCKDCLK0EN

3128272625242322212019181716DCLK1CMP DCLK1DIV DCLK1SEL DCLK1EN

2DCLKCON---DDCLK1(0)SelCK---DCLK1(0) source clock 0 PCLK1UCLK ( USB )DCLK1(0)EN---DCLK1(0) Enable01

151211109876543210DCLK0CMPDCLK0DIVDCLK0SelCKDCLK0EN

3128272625242322212019181716DCLK1CMP DCLK1DIV DCLK1SEL DCLK1EN

10

Register Address R/W Description Reset Value EXTINT00x56000088 R/W 00x0 EXTINT10x5600008C R/W 10x0 EXTINT20x56000090 R/W 20x0

EINT0~7---00000101x10x11x37111519232731---1EXTINT0---0

1514131211109876543210XEINT3XEINT2XEINT1XEINT0


EINT8~15---00000101x10x11x37111519232731---2EXTINT1---1



EINT16~23---00000101x10x11x37111519232731---FILTEN013EXTINT2---2

1514131211109876543210F19EINT19F18EINT18F17EINT17F16EINT16

31302928272625242322212019181716F23EINT23F22EINT22F21EINT21F20EINT20

11

Register Address R/W Description Reset Value EINTFLT00x56000094 R/W - EINTFLT10x56000098 R/W - EINTFLT20x5600009C R/W 20x0EINTFLT30x560000A0R/W30x0

FLTCLK16~19---16~190PCLK1/OMEINTFLT16~19---16~191EINTFLT2---2

15148760FLTCLK17EINTFLT17FLTCLK16EINTFLT16


FLTCLK20~23---20~230PCLK1/OMEINTFLT20~23---20~232EINTFLT3---3



12

Register Address R/W Description Reset Value EINTMAK0x560000A4 R/W 0x00FFFFF0 EINTPEND0x560000A8 R/W 0x0

01 EINT0--- EINT3SRCPND

23EINT2315EINT157EINT722EINT2214EINT146EINT621EINT2113EINT135EINT520EINT2012EINT124EINT419EINT1911EINT11318EINT1810EINT10217EINT179EINT9116EINT168EINT80

0110.

23EINT2315EINT157EINT722EINT2214EINT146EINT621EINT2113EINT135EINT520EINT2012EINT124EINT419EINT1911EINT11318EINT1810EINT10217EINT179EINT9116EINT168EINT80

GSTATUS340

13

Register Address R/W Description Reset Value GSTATUS00x560000AC R GSTATUS10x560000B0 RID()0x32410000GSTATUS20x560000B4 R/W0x1GSTATUS30x560000B8R/W0x0GSTATUS40x560000C0R/W0x0

nWEIT---nWEIT

nCON---nCON

RnB---R/nB

nBATT_FLT---nBATT_FLT

011GSTATUS0---

3143210 nWEITnCONRnBnBATT_FLT

WDTRST---10OFFRST---10PWRST---102GSTATUS2---13

313210 WDTRSTOFFRSTPWRST

static void __irq Eint0Int(void){ ClearPending(BIT_EINT0); Uart_Printf("EINT0 interrupt is occurred.\n");}

static void __irq Eint1Int(void){ ClearPending(BIT_EINT1); Uart_Printf("EINT1 interrupt is occurred.\n");}

void Test_Eint(void){ int i; int extintMode;//

Uart_Printf("[External Interrupt Test]\n");

Uart_Printf("1.L-LEVEL 2.H-LEVEL 3.F-EDGE 4.R-EDGE 5.B-EDGE\n"); Uart_Printf("Select the external interrupt type.\n"); extintMode=Uart_Getch();

//extintMode='3'; rGPFCON = (rGPFCON & 0xfffa)|(1

switch(extintMode) { case '1': rEXTINT0 = (rEXTINT0 & ~((7

case '4': rEXTINT0 = (rEXTINT0 & ~((7

Uart_Printf(Press the EINT0/1 buttons or Press any key to exit.\n);//

pISR_EINT0=(U32)Eint0Int;// pISR_EINT1=(U32)Eint1Int;;// rEINTPEND = 0xffffff; //EINTPND EINTPND rSRCPND = BIT_EINT0|BIT_EINT1; //to clear the previous pending states rINTPND = BIT_EINT0|BIT_EINT1;

rINTMSK=~(BIT_EINT0|BIT_EINT1);

Uart_Getch();

rEINTMASK=0xffffff; rINTMSK=BIT_ALLMSK;} void Test_Eint(void)#define BIT_ALLMSK (0xffffffff)

1S3C2410X

5162824PWMS3C241051603PWM4028240 1 8 234 1/21/41/81/164

2 PWM

PWM01PWM PWM

2PWMTCMPBTCNTTCMPBTOUTTCMPBTOUT

3S3C2410timer0

4DMAS3C2410DMA5DMADMADMA DMADMADMAnDMA_REQACKACKDMADMA

3

1f Tclk f Tclk=[f pclk(Prescaler+1)] Prescaler0---2551/21/41/81/16 2PWM PWM= f Tclk TCNTBn3PWMPWM = TCMPBn TCNTBn

PCLK50MHz4-7-1

4-7-1

(=0TCNTBn=1)(=255TCNTBn=65535)(=0TCNTBn=65535)(=0TCNTBn=255)1/225.00MHz(0.04s)0.6710s381Hz976561/412.50MHz(0.08s)1.3421s191Hz488281/86.250MHz(0.16s)2.6843s95Hz244141/163.125MHz(0.32s)5.3686s48Hz12207

617TCNTBn---Timern16TCMPBn---Timern16TCNTOn---Timern16

Register Address R/W Description Reset Value TCFG00x51000000 R/W 00x00000000 TCFG10x51000004 R/W 10x00000000 TCON 0x51000008 R/W 0x00000000TCNTBn0x510000xx R/W (5)0x0000TCMPBn0x510000xxR/W(4)0x0000TCNTOn0x510000xxR(5)0x0000

Dead zone length---N 0~255timer0N+1timer0Prescaler1---timer234N 0~255PCLK N+1Prescaler0--- timer01N 0~255PCLK N+11TCFG0---

31242316158700Dead zone lengthPrescaler1Prescaler0

2TCFG1---DMADMA mode---DMA0000DMA0001timer00010timer10011timer20100timer30101timer4011XMUX4~ MUX0---timer4~timer000001/200011/400101/8 00111/1601XXTCLK01timer01TCLK0timer432TCLK1

31 2423 20191615121187 43 00DMA modeMUX4MUX3MUX2MUX1MUX0

TL4~TL0--- 010TUP4~TUP0---01TCNTBnTCNTn3TCON---

121110987543210TR2TL1TO1TUP1TR1DZETL0TO0TUP0TR0

312322212019181716151413TL4TUP4TR4TL3TO3TUP3TR3TL2TO2TUP2

TR4~TR0---TIMER4~TIMER001TIMERTO3~TO0--- TIMER4~TIMER001DZE---TIMER0013TCON---

121110987543210TR2TL1TO1TUP1TR1DZETL0TO0TUP0TR0

312322212019181716151413TL4TUP4TR4TL3TO3TUP3TR3TL2TO2TUP2

1

1TCFG0Timer02TCFG1DMA3TCNTBnTCMPBn4TCON5TCON

2TCON

3

1TCNTBn=160(50+110)TCMPBn=110TCNTBn=80 TCMPBn=402,3480405TCMPBn=60810

int variable0,variable1,variable2,variable3,variable4;void __irq Timer0Done(void){ rSRCPND = BIT_TIMER0; //Clear pending bit rINTPND = BIT_TIMER0;//Clear serve bit variable0++; }void __irq Timer1Done(void){ rSRCPND = BIT_TIMER1; //Clear pending bit rINTPND = BIT_TIMER1; variable1++; }rINTPND; //Prevent an double interrupt pending

void Test_TimerInt(void){ variable0 = 0;variable1 = 0;variable2 = 0; variable3 = 0;variable4 = 0;

rINTMSK = ~(BIT_TIMER4 | BIT_TIMER3 | BIT_TIMER2 | BIT_TIMER1 | BIT_TIMER0);

// pISR_TIMER0 = (int)Timer0Done; pISR_TIMER1 = (int)Timer1Done; pISR_TIMER2 = (int)Timer2Done; pISR_TIMER3 = (int)Timer3Done; pISR_TIMER4 = (int)Timer4Done;

Uart_Printf("\n[ Timer 0,1,2,3,4 Interrupt Test ]\n\n");

rTCFG0 = rTCFG0 & ~(0xffffff) | 0x000f0f; //Dead zone=0,//Prescaler1=15(0x0f),Prescaler0=15(0x0f) rTCFG1 =rTCFG1 & ~(0xffffff) | 0x001233; //All interrupt,//Mux4=1/2,Mux3=1/4,Mux2=1/8,Mux1=1/16,Mux0=1/16

//Timer input clock frequency = PCLK/(prescaler value+1)/(divider value) rTCNTB0 = 0xffff; // (1/(50MHz/16/16)) * 0xffff (65535) = 0.334s rTCNTB1 = 0xffff; // (1/(50MHz/16/16)) * 0xffff (65535) = 0.334s rTCNTB2 = 0xffff; // (1/(50MHz/16/8 )) * 0xffff (65535) = 0.163s rTCNTB3 = 0xffff; // (1/(50MHz/16/4 )) * 0xffff (65535) = 0.078s rTCNTB4 = 0xffff; // (1/(50MHz/16/2 )) * 0xffff (65535) = 0.039s

rTCON = rTCON & ~(0xffffff) | 0x6aaa0a; //Auto reload, Inverter off, Manual update, Dead zone disable, Stop

rTCON = rTCON & ~(0xffffff) | 0x599901; //Auto reload(T0=One-shot),Inverter off,No operation,Dead zone disable,Start while(variable0 == 0);

Delay(1); //To compensate timer error(

Uart_Printf("Press any key to exit Timer interrupt test\n"); while(!Uart_GetKey());

rTCON = 0x0; //One-shot, Inverter off, No operation, Dead zone disable, Stop Uart_Printf("Timers interrupt number is as below:\n");

Uart_Printf("Timer0 - %d ,Timer1 - %d ,Timer2 - %d ,Timer3 - %d ,Timer4 - %d \n", variable0,variable1,variable2,variable3,variable4);

rINTMSK |= (BIT_TIMER4 | BIT_TIMER3 | BIT_TIMER2 | BIT_TIMER1 | BIT_TIMER0);}

#define BIT_TIMER0 (0x1

4.8 UART

S3C2410 UARTI/O UART0UART1UART2DMA UART230.4kbpsUART PCLKUCLK116 FIFO S3C2410 3UART1.0 UART0UART1MODEMFIFO TxDnRxDnFIFO

2

115 8 112ULCONn0 0 FIFO FIFO

2UART S3C2410 PCLKUCLK UBRDIVnUBRDIVn UBRDIVn=(int)CLK/bps*16 1 CLKbps115200bps PCLK UCLK 40MHz,UBRDIVn UBRDIVn =int(40000000)(115200*16))-1 = (int)(21.7)-1 = 21-1 = 20

3

UART10bit1.873/160t_true = (UBRDIVn + 1)1610 / PCLK10bit t_ideal = 10 / baud-rate10UART error( ( t_true t_ideal ) / t_ideal )100%

4UART0UART1UMCONnnRTSnCTSFIFOnRTSnCTSnRTSnCTSUARTMODEM

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嵌入式系统讲义 第 4 章 S3C2410X 系统结构

嵌入式系统讲义第 4 章 S3C2410X 系统结构