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1-D DCT 專題. 分散式算術 (Distributed Arithmetic: DA) 1-D DCT Design. 1-D DCT 專題. 分散式算術 Distributed Arithmetic (DA). Often used for inner products , e.g. DCT. Multiple-In Multiple-Out (MIMO). Multiple-In Single-Out (MISO). Inner products c i are M-bit constants and x i are W-bit numbers. - PowerPoint PPT Presentation
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H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT 專題
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT 專題
分散式算術 (Distributed Arithmetic: DA) 1-D DCT Design
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
分散式算術Distributed Arithmetic (DA)
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
• Often used for inner products, e.g. DCT
Multiple-In Multiple-Out (MIMO)
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
• Inner products
– ci are M-bit constants and xi are W-bit numbers
Multiple-In Single-Out (MISO)
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
N=3, W=3
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Y
Multiple-In Single-Out (MISO)
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Multiple-In Multiple-Out (MIMO)
Add
ress
de
code
r
yi(0)
yi(2)
yi(3)
Y(0)Y(2)Y(3)
+/- sh +/- sh +/- sh
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
2N word ROM
REG
0 0
+/-
Output
Input
10...00 A’ /S
shift-right
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT Design
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Simplified 1-D DCT Algorithm
1,....,1,0,)()(1
0
NkCnykYN
n
nkN
Where {y(n), n = 0, 1, …., N-1} : input sequence
CNnk (i.e., ) : coefficients)
2cos(
N
nk
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT Algorithm & MAC Architecture
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
94
64
34
04
64
44
24
04
34
24
14
04
04
04
04
04
y
y
y
y
CCCC
CCCC
CCCC
CCCC
Y
Y
Y
Y
MAC
)(( ny )(kYD
Input data MAC processing stage Output buffer
Nclk
nkNC
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT Algorithm & MAC Architecture (cont.)
Y0m
+n-p
m m Y(k)
ACC
*
n/2
CNnk
y(n)
MAC
m-(n-p)
n[n-p-1]
n/2n/2
n/2
n/2
n/2
[n/2-1]
n-p[n/2-1]
• 乘法器及累加器位元數目之決定• 每經過一個 clock 完成一次 MAC運算
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT Algorithm & DA Architecture
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
94
64
34
04
64
44
24
04
34
24
14
04
04
04
04
04
y
y
y
y
CCCC
CCCC
CCCC
CCCC
Y
Y
Y
Y
PISO DA Unit
)(( ny )(kY
Input buffer
Output buffer
Input stage DA processing stage Output stage
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
1-D DCT ROM-based DA Architecture (cont.)
PISO DA Unit
)(( ny )(kY
Input buffer
Output buffer
Input stage DA processing stage Output stage
piso_load
Out_buf_load
Out_buf_clkpiso_DA_clkIn_buf_clk
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
ROM-based DA 1-D DCT Architecture (cont.)
?
PISO DA Unit
)(( ny )(kY
Input buffer
Output buffer
Input stage DA processing stage Output stage
piso_load
Out_buf_load
Out_buf_clk
clk
因為 DCT 點數與輸入資料位元數相同
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Design for Control
s0 s1 s2 s300 00 00 00s4 s5 s6 s710 00 00
s8 s900 10
01reset
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Input Buffer and Output Buffer
y(n)
D
D
D
Dy(0)
y(1)
y(2)
y(3)
Y(k)
D
D
D
DY(0)
Y(1)
Y(2)
Y(3)
Out_buf_load
• Input BufferWord-level SIPO
• Output BufferWord-level PISO
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
Word Parallel-In and Bit Serial-Out (PISO) for DA input
y(0)
y(2)
y(3)
yi(0)
yi(2)
yi(3)
piso_load
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
ROM-based DA Design for Inner Product
Add
ress
de
code
r
yi(0)
yi(2)
yi(3)
Y(0)Y(2)Y(3)
+/- sh +/- sh +/- sh
H. C. Chen / NUU, Taiwan
Verilog HDL & Lab
參考資料
Stanley A. White, “Application of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review,” IEEE ASSP Magazine, pp. 4-18, 1989.
