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ABSTRACT

This paper presents a balanced receiver structuresuitable for wireless infrared data communications. Thereceiver provides a fixed photodiode bias voltage with theuse of a regulated cascode input stage. Together with anactive feedback loop used to eliminate dc photocurrents,the receiver implements ac coupling without the need formatching capacitors. Differential sensing of thephotodiode current improves sensitivity. Designed for a0.35m digital CMOS process, simulation results showthat the circuit consumes 12mW at 3V, provides 40ktransimpedance gain over a bandwidth of 200 MHz, andhas a minimum power supply rejection ratio of 40 dBover the entire operating bandwidth.

I. INTRODUCTION

Practically every new laptop computer, PDA(personal digital assistant), and digital camera comesequipped with an infrared (IR) wireless port. Over shortdistances, IR free-space links offer an industry-standardwireless solution unmatched in low cost and high speed.Digital CMOS is the preferred technology because of itslow cost and high potential for system integration.However, building single-chip optical receivers in CMOStechnology is challenging because low supply voltages,

small transconductances, and substrate noise make itdifficult to achieve high bandwidth and good sensitivity.IR wireless receivers must also be able to reject dcphotocurrents generated by ambient light. Sometimesthese photocurrents are much larger than the signalcurrent, resulting in reduced swing or even saturation atthe optical receiver.

Previously reported implementations [1] [2] sensedthe photocurrent single-endedly. In addition, in order toreject noise from the photodiode bias source, anadditional dummy capacitor was used [1] to match thephotodiode capacitance. In this paper, we present animproved receiver structure that realizes differential

sensing of the photodiode and eliminates the need for amatching capacitor. It uses a truly differential feedbackstructure for improved power supply rejection. Thephotodiode bias circuit has also been incorporated intothe receiver. The resulting circuit is an IR wirelessreceiver front-end with improved gain, bandwidth, andpower supply rejection.

II. PREAMPLIFIER ARCHITECTURE

Fig. 1 shows the simplified schematic of theproposed preamplifier structure. The circuit is comprisedof three sections: the photodiode bias input stage, thetransimpedance amplifier, and the dc photocurrentrejection feedback loop. Transistors Mf3 and Mf6 regulatethe reverse bias voltage across the photodiode. Regulatedcascode circuit (RGC) [3] is employed to reduce theinput impedance seen at the sources of M f5 and Mf6.These transistors provide a common-gate input bufferstage to the transimpedance amplifier. Transistor Mf4 is

added to improve the symmetry of the signal path. Mf3and Mf4 are just for level shifting and as shown in Fig.3they will be bypassed by C1 and C2 at our frequencies ofinterest.

Although, the proposed receiver structure does notimpose any constraints on the design of thetransimpedance amplifier, we present here a differentialtransimpedance amplifier that uses local shunt feedbackin the second stage. The amplifier is similar to thetwo-stage design presented in [1], but uses a n-channelinput differential pair similar to the design in [4] toachieve higher bandwidth and reduced thermal noise.

Fig. 1 Basic structure of proposed optical preamplifier.

The dc rejection feedback loop consists of an erroramplifier and a differential pair made up of transistors

Rf2

Rf2

Mf2

Mf3

Mf4 Mf6

Mf5

Ib Ib

2Ib

out-

out+

Vdd

I1 I2

I3

is + Io

Ib + Io

Ib - Io

is

Error Amplifier

Photodiode Bias

Input Stage

DC photocurrent rejection circuit

Mf1

RGCFixed

TransimpedanceAmplifier

Bias

432 1

TRANSIMPEDANCE AMPLIFIER

WITH DIFFERENTIAL PHOTODIODE CURRENT SENSING

Bahram Zand, Khoman Phang, and David A. Johns

Dept. of Electrical and Computer Engineering

University of TorontoToronto, Ontario, M5S 3G4, CANADA

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Mf1 and Mf2. The error amplifier functions as anintegrator and determines the average difference in thedifferential outputs. Current sources I1 and I2 bias thecascode transistors Mf3-6. In the absence of any dcphotocurrent, all currents sourced by I1 and I2 will bedrawn away from the transimpedance amplifier by thedifferential pair. The presence of a dc photocurrent, Io,

results in a negative differential offset voltage at theoutput of the transimpedance amplifier. This offset causesthe error amplifier to change the differential voltageapplied to the differential pair. In steady state, the biascurrent increases by Io for Mf1 and decreases by Io forMf2 as illustrated in Fig. 1. In essence, the dcphotocurrent has been steered into the differential pair,away from the transimpedance amplifier. In contrast, thedifferential pair appears as a high impedance path to thesignal current, . As a result, passes through to thetransimpedance amplifier where it is sensed differentially,resulting in a transimpedance gain of 2Rf2.

The proposed structure offers several advantages overthe original structure reported in [1] and shown in Fig.2.The most significant advantage is that the proposedstructure is fully differential. In the original structure,only the transimpedance amplifier is differential. As well,the sensing of the photodiode current is single-ended, sothat only photocurrent sourced from the anode of thephotodiode is used. This has two disadvantages: first, thecurrent being sunk by the cathode of the photodiode is notput to use, effectively halving the signal current.Secondly, driving a differential transimpedance amplifiersingle-endedly creates an asymmetry in the differentialstructure. As a result, an additional capacitor, , isrequired at the other input terminal of the transimpedanceamplifier in order to match the photodiode capacitance,effectively rebalancing the circuit. Perfect matchingensures that noise injected at the bias voltage, ,appears only as a common-mode signal which iseffectively rejected by the differential transimpedanceamplifier. Unfortunately, achieving good matching isdifficult since the photodiode is an external device, and itscapacitance varies with the applied reverse bias voltage.

Fig. 2 Active dc photocurrent cancellation circuit presented in [1].

is is

Cd

Vre f

TransimpedanceAmplifier

ErrorAmplifier

Mctl

Cd

out+

out-

Vref

Rf2

Rf2

With the proposed differential structure, thephotocurrent is sensed differentially. Since thephotodiode is placed across the differential inputs of thetransimpedance amplifier, the resulting circuit isinherently balanced, eliminating the need for a dummymatching capacitor.

Unlike the dc photocurrent rejection circuit in Fig.2,

the bandwidth of the proposed receiver structure isindependent of the dc photocurrent level. The lowercut-off frequency is not affected because the differentialpair is already biased with a current of Ib which isdesigned to be much larger than the maximum dcphotocurrent. The upper cut-off frequency is not affectedbecause the bias currents of transistors Mf3 and Mf6 areregulated by the feedback loop to Ib regardless of thevalue of Io.

III. PHOTODIODE BIAS INPUT STAGE

The photodiode biasing circuit including thecommon-gate and RGC transistors is shown in Fig. 3.The reverse bias voltage on the photodiode is determinedby the voltage differences at the sources of Mf3 and Mf6.For a 3V supply, the applied bias voltage ranges from aminimum of the threshold voltage of an NMOS device toa maximum of about 1V which is required to keep allMOSFETs in the active region. To explain the operationof the RGC blocks, we refer to the equivalent half-circuitschematic shown in Fig.4.

Fig. 3 Regulated cascode (RGC) circuits.

Fig. 4 Equivalent half-circuit of RGC block.

The input impedance of this circuit is

Rd

Rd

Vdd

12

4 3

Mf5

Mf6

Mf3

Mf4

Mc1

Mc2

Ig

0.8V 1.8V

2.8V

2.8V

1.8V

RGC

2.1V

1.8V 2.1V

1

C2

a c

b d

RdMc2

Vdd

IoutMf6

Rin

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(1)

Basically, it is the input impedance of a simplecommon-gate stage reduced by the factorwhich is one plus the loop gain of feedback circuit made

up of and . Some design considerations whichlimit the minimum achievable input impedance includethe allowable voltage drop across , powerconsumption, and frequency response of the feedbackcircuit. For the differential configuration, the impedancelooking into the bias circuit will be twice that given inequation (1). The frequency pole resulting from thedepletion capacitance of the photodiode, , and thedifferential input impedance is

(2)

To illustrate the design process, if we assume aphotodiode capacitance of 5 pF and wish to have a pole

at 250 MHz, the differential impedance of the input stagemust be kept about 125. This means that, for atransconductance of 4.5 mA/V at the cascode device,Mf5, we need a minimum RGC loop gain of 2.55. Thiscan be achieved by choosing and

. Other poles such as the polecreated by the feedback network, Rf2 and Cf2, as well ascomplex poles introduced by the second stage ofdifferential transimpedance amplifier (Fig.7) will limitthe total bandwidth to about 200 MHz. The simulateddifferential input impedance of the input bias stage isshown in Fig.5. Note how the impedance is maintained ataround 125 only up to the required bandwidth. Whilethe photodiode capacitance as well as pad and packaging

parasitic effects at nodes a and d of Fig.3 create anasymmetry in the circuit, capacitors C1 and C2 willalleviate this problem by bypassing transistors Mf3 andMf4 at high frequencies. These capacitors are off-chipcapacitors in the range of a few nF.

Fig. 5 Simulated input impedance of the RGC input bias stage.

Rin1

gmMf6

1 gmMc2

Rd+

--------------------------------------------------

1 gmMc 2Rd+( )

Mc2 Rd

Rd

CPD2Rin

P11

2RinCPD----------------------=

Rd 600=gmM c1 4.25mA V=

InputImp

edance()

1MHz

160

120

80

40

200

10KHz 1MHz 100MHz 10GHz

InputImpedance()

IV. DIFFERENTIAL TRANSIMPEDANCEAMPLIFIER

Fig. 6 shows the schematic diagram of thetransimpedance amplifier. Diode-connected transistorM13 is used to level-shift the output common-modevoltage to about 2.1V. The transimpedance gain of thecircuit is given by

(3)

where is the open-loop voltage gainof differential amplifier and is the transconductanceof the input differential pair[1].

Fig. 6 Differential transimpedance amplifier circuit.

The bandwidth of this transimpedance amplifier isdependent on the capacitance seen at the input terminalsas well as the frequency response of second stage.Because the photodiode bias input stage has isolated the

transimpedance amplifier from the large photodiodecapacitance, non-dominant poles of the total circuit aredetermined by the second stage of the above circuit. Asmall-signal model for the second stage oftransimpedance amplifier is shown in Fig. 7 where Cf1 isthe total shunt feedback capacitance bridging the drainand gate of M11 or M12 and Ci and Co are the input andoutput capacitance respectively.

Fig. 7 Simplified model for second stage.

Because of the presence of two capacitors, Ci and Co,the second stage exhibits a second-order response. Shuntfeedback capacitor, Cf1, can be used to tune the polelocations and to maximize the bandwidth [1].

2Avd

1 Avd+------------------Rf2 2Rf2= for Avd 1

Avd gmiRf1=gmi

in-in+

out+

out-

bias1

bias2

M1 M2

M3 M4

M5 M6M7 M8

M9 M10

M11 M12

M13

Rf1 Rf1

Cf1 Cf1

Avd

out+out-

in+

in-

Rf2

Rf2

Cf2

Cf2

ii

Cf1

Ci

+

_Vi Co

+

_

voutgm12 Vi

Rf1

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V. SIMULATION RESULTS

The simulated frequency response of the completereceiver circuit is shown in Fig. 8. The preamplifier has abandwidth from 180 KHz up to 200 MHz with gain of40k (92dB), and a minimum input noise currentdensity of 5 . It consumes 12mW using a single3V supply. In comparison with [1], the proposed circuit

exhibits four-fold improvement in the gain-bandwidthproduct with the same technology and power dissipation.

Fig. 8 Frequency response of entire receiver circuit.

Fig.9 shows the differential output steady statetransient response to a 10A input pulse stream after thecancellation of dc components.

Fig. 9 Pulse response of optical receiver.

Because of the symmetric configuration, this circuitis highly immune to substrate noise and power supplymodulation. Fig. 10 shows the Power Supply RejectionRatio (PSRR) of the receiver. The PSRR is at least 40 dBover the entire bandwidth of the receiver for C1=C2=10nF.

pA Hz

100

80

60

40

20TransimpedanceGain(dB)

10z 1MHz 100MHz 10GHz

0 10n 20n 30n 40n

2.1

2.0

2.2

DifferentialOutputsVoltages(V)

Fig. 10 Power supply rejection vs. frequency.

VI. SUMMARY

This paper proposes a balanced fully differentialreceiver structure for use in infrared wireless datacommunications. The structure rejects dc photocurrentsusing negative feedback around the transimpedanceamplifier. Input common-gate transistors operating asregulated cascodes reduce the input impedance of thereceiver, moving the dominant pole away from thetransimpedance stage. Differential sensing of the signalcurrent doubles the overall transimpedance gain and thebandwidth has also been improved. The proposedsymmetric configuration is robust to common-modeinterference. This circuit is designed for a 3V, 0.35 mCMOS process. Simulation results show the preamplifierprovides a gain of 40 k over a bandwidth of 180 kHz to200 MHz with a minimum PSSR of 40dB.

VII. REFERENCES[1] K. Phang and D.A. Johns, A 3-V CMOS Optical

Preamplifier with dc Photocurrent Rejection, IEEE Proc.

ISCAS, TAA8-8, June 1998.

[2] R.G.Swartz, Y.Ota, M.J.Tarsia, and V.D.Archer, A Burst

Mode, Packet Receiver with Precision Reset and Automatic

Dark Level Compensation for Optical Bus

Communications, Symp. on VLSI technology, Kyoto,

Japan, pp.67-68, May 1993.

[3] S.M. Park and C. Toumazou, Low Noise Current-Mode

CMOS Transimpedance Amplifier for Giga-bit Optical

Communication, IEEE Proc. ISCAS, TAA8-4, June 1998.

[4] R. Coppoolse, J. Verbeke, P. Lambrecht, J. Codenie, and J.Vandewege, Comparison of a Bipolar and a CMOS FrontEnd in Broadband Optical Transimpedance Amplifiers,Proc. 38th Midwest Symp. on Cir. and Sys., Brazil, pp.1026-1029, Aug. 1996.

80

70

60

50

40100KHz 1MHz 10MHz 100MHz 1GHz

PSRR(dB

)

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