2017 第4回半導体技術の概要と動向kobaweb/news/pdf/2017/2017-10-24...MOS トランジスタ(FET)の構造 MOSﾄﾗﾝｼﾞｽﾀの基本構造はバイポーラトランジスタに比べてシンプル。P型MOSとN型MOSがある。

1)

2)

MPUDRAMNAND

3)

ITRSITRS

3D FinFET

NAND3D

3

3

PoP,TSV

4

H29

339

2017.10.24

2017

1

MOS(FET)MOSPMOSNMOS

NMOS

PN

N

PMOS

NMOS

N(P)P(B)

2

NN

P

1-2nm

(SiO2)

CMOS

MOS: Metal Oxide SemiconductorCMOS: Complementary MOS

VDD

H VDD)

3

CMOS

GND

CL CL

H HL L

DRAM

DRAMMOS11

MOS

4GDRAM401

MOS

MOS

4

25fF

Dynamic Random Access Memory

SiO2

3,00020nm

5

19651824(1

1965

LSI

1000

100

10

DRAM

Intel

LSI)

Gordon E. Moore :Intel

6

http://japan.intel.com/contents/museum/processor/

10

1000

22

19712,300

2017iPhone8A11 43 (10nmFinFET

2017(xBoxone x)70(16nmFinFET

7

GPU(NVIDIA)210

GPU:

http://ascii.jp/elem/000/000/906/906770/index-2.html

DRAM

100

80

60

40

20

0

(%)

8Gbit

4Gbit2Gbit

1Gbit

512Mbit

DRAM

2013Intel IDF

DRAM22

20164Gbit8Gbit

DRAM16Gbit

8

9

DRAM16nm

DRAMSamsung

DRAM

http://eetimes.jp/ee/articles/1709/01/news046.html

1X:18nm

1Y:15nm

10

ISSCCNAND

768GbVLSI96

2010 32Gb MLC 32nm

2011 64Gb MLC 24nm

2012 64Gb MLC 19nm

2013 128Gb TLC 20nm

2014 128Gb MLC 16nm

2015 128Gb TLC 323D NAND



2017/6 768Gb QLC 643D NAND

2017/6 256Gb TLC 963D NAND

NAND

64512Gb3D NAND

ISSCC2017

2016128Gbit(MLC)14nm

33D NAND32128Gb(TLC)2

2017ISSCC64512Gbit20176

20176QLC(4bit/cell)768Gbit/chip

768Gbit/chip16

1.5TByte(12.3Tbit)/

SLC:1bit/cell

MLC:2bit/cell

TLC:3bit/cell

QLC:4bit/cell

http://techon.nikkeibp.co.jp/article/MAG/20150306/407702/

200320093x0.7

32

32nm201615nm(NAND)

11

LSI(MPUSoCITRS

12

ITRSITRS

International Technology Roadmap for Semiconductors

ITRS

15

20162ITRS

15

ITRS2013 Edition

1.System Integration

2.Heterogeneous Integration

3.Heterogeneous Components

4.Outside System Connectivity

5.More Moore

6.Beyond CMOS

7.Factory Integration

ITRS2.0 2015 Edition

IoT

ITRS

2016

2

13

Memory Trends:ITRS2.0 2015 EditionITRS ITRS

ITRS2.0 2015 Edition Executive Report

NANDHP=14nm3D NAND

DRAMHP=20nm

14

Logic Trends:ITRS2.0 2015 Edition

ITRS2.0 2015 Edition Executive Report

2016Logic14/16nm FinFETITRSHP(=28nm

201710nmFinFETITRSHP=18nm

ITRS

ITRS

ITRS Research, Development, Production

Production(122/

5

12

2/22/4Intel

ITRS

ITRS2013 Executive Summary

9~12

tool

ITRSPIDS/FEP

8

15

ITRSDRAMMPU/ASIC

http://jaco.ec.t.kanazawa-u.ac.jp/edu/micro1/pdf/1.2.pdf


DRAM

DRAMMPU/ASIC1/2Pitch

M1)1/2

ITRS

MPU/ASIC

Leff FET

L

20nm

Intel 14nm

ITRS26nm

16

17http://pc.watch.impress.co.jp/docs/column/kaigai/20160315_748146.html

ITRS

M1(Metal 1)M10(Metal 10)M1

ITRSM11/2(HP)

Source

18

GLOBALFOUNDIESGFIntelSamsungTSMCCPPContacted Poly PitchMMPMinimum Metal Pitch


Industry Strategy SymposiumISS20171811

ITRSITRS

Intel10nmITRS20nmIntel10nm(Samsung,TSMC,GF)7nmIntel7nm5nm

ITRSNAND

http://jaco.ec.t.kanazawa-u.ac.jp/edu/micro1/pdf/1.2.pdfITRS2011 Executive Summary

NAND1/2Pitchhp)

1/2

NAND

poly-si

ITRS

15nm

19

nm

ITRS (

CAGR(2 yrs) = -15.9%

.7x/2yrs

ITRS

12x0.7

ITRSNAND

MPUSOC)LSI22nm,16nm,14nmITRS

3D FinFET M1

20

R. Dennard (1974

S

1/S

1/S

L)

Device/Circuit parameter Scaling Factor

Device dimensions L, W, Tox 1/S

Doping concentration SS1.5

Voltage 1/S

Field 1

Current 1/S

Gate Delay 1/S

Power dissipation/device 1/S3 1/S2

tox

L

W

Scaling 2S

LSI

1/S

1/S

21

100 nm

30nm

LSI1

LSI20nm

1nm

100nm

10nm

1um

10um

100um

1mm

10mm

100mm

1m

1

10m

22

MOS FET

SiO2

130nmMOS FET

L

CoSiO2

MPUSOC

23

MOS FET90nm47.5nm

Chipworks 2004.1


ON/OFF

3

Intel 2007 Intel 2009

Intel 2003

High-k/

SOI SOI

FinFET

Tri-Gate

Intel 2011

90nm

90nm45nmHigh-k/

22nm3D(MuGFET)

24

Intel

Intel

High-k MG3DTri-Gate(FinFET)3

2014TSMCSamsung

Intel25

Intel4(32nm)

SiGeGe

GeSi Si,Si

NMOSPMOS

SiN2

NMOSPMOS

PMOS

MOS

IEDM2009PMOS

SiGe

SiGe

GateMetal

26

60 70 80 90 2000 100.001

0.01

0.1

1

10

100

1000

Po

wer

co

nsu

mp

tio

n(W

)

Dynamic current

Leak current

CPU

fCLVddIleak

ddleakddLd VIVfCP 2

CL

CMOSDynamic current

27

Ioff Ioff

28

HKMG(High-k/Metal Gate)

SiO2(

Si3N4(

HfSiO(

HfO(

High-k

(1nm)High-KSiO22

High-k

SiO2

MG(Metal Gate):

MOS

29

Ioff

(NMOS

SOISilicon on Insulator)SOIBOX)

Si

FD SOI (SOI)

SiO2

90nm

SOIIBMAMDSTMIntelSOI

30

3D Tri-Gate/FinFET

FET

Tri-Gate

FinFET

Trigate/FinFET

SiO2

3D Tri-Gate/Fin FET

3

3

Gate

Drain

Source

SiO2

FinFET

2FETS-DON/OFF

Trigate/FinFET3

31

Intel 22nmFinFET214nmFinFET

http://electronics360.globalspec.com/article/4469/intel-presents-broadwell-cpu-14nm-finfet-process

22nm FinFET 14nm FinFET

60nm Fin 42nm Fin

42nmFin 34nm Fin

Si Si

SEM

FinFET

20132011

Fin

Gate90nm80nm

Gate70nm52nm

32

2Fin

33http://pc.watch.impress.co.jp/docs/column/kaigai/1076333.html#11_s.jpg

IntelFinFET

Fin34nmFin60nmFin8nm

Fin42nmFin42m

Fin53nmFin34nm

2(201312011 3(2017

Gate

Drain

Source

SiO2

FinFETIntelIEDM200622nmTri-Gate

201122nm1201314nm2

201710nm3

Intel10nm34nm53nm

36nm54nm

Intel10nmFinFET 7nm

FinFET

vs Intel22nm/14nm

3D FinFET

FinFET

Intel20142FinFET

22nm14nm

FinFET

/W

Intel

Server

Mobile

Server

Mobile

34

NANDNAND

NAND16nm3D

20149NAND15nm3D

200920112012NAND

3D34

http://eetimes.jp/ee/articles/1312/06/news054_3.htmlNAND

20nm

20nm

21nm

25nm

24nm

20nm

19nm

18nm 16nm

18nm

16nm

15nm

1(Y)nm

Intel+

Micron

35

WinPC 201311

NAND

2013NAND201410nmNAND

20153D256GbitNAND

20143D NAND

2013Samsung32128Gbit

2017NAND50%3D NAND(64256Gbit) 20166

2016

36

3D NAND2007BiCS

20073NANDBiCS

BiCS

Bit Cost Scalable

3D

NAND

2009.837

3D NANDBiCS

BiCS

RIE

() ()

NAND

BiCS

3D

NAND

38

Vertical Channel 3D NAND

Flash Memory Summit 2012SK Hynix

3NAND2007BiCS

Samsung,Hynix,MicronBiCS

Samsung2009BiCSTCAT20138V-NAND

V-NAND2013

3D

NAND

39

40

Samsung3D NAND BiCS 512Gbit 64

ISSCC2017 11.1 & 11.4

3D NAND BiCS 512Gbit 64

Samsung 3D NAND ISSCC20173D

NAND

64512Gbit(TLC)

41

3D

NAND 3D NAND

http://pc.watch.impress.co.jp/docs/column/semicon/1076106.html

3D NAND

AI2017

NAND3Samsung,/WDMicron-Intel)64256G512Gbit(TLC)

64768Gbit(QLC)(2017.6)

96512Gbit(TLC)

http://pc.watch.impress.co.jp/img/pcw/docs/1076/106/html/photo005.jpg.htmlhttp://pc.watch.impress.co.jp/img/pcw/docs/1076/106/html/photo005.jpg.htmlhttp://pc.watch.impress.co.jp/img/pcw/docs/1076/106/html/photo007.jpg.htmlhttp://pc.watch.impress.co.jp/img/pcw/docs/1076/106/html/photo007.jpg.html

Intel+Micro 128Gbit 3D

X,Y20nm128G6402ReRAMNAND1000DRAM810NAND1000


20nm128Gbit 3D XPoint

3D

XPoint

42

Intel+Micron3DXPoint

3(3D)

STRJ/ITRS

TSV

PoP

3PoP

WL :

Wafer Level

3D3D

43

PoPPackage on PackageA92GB DRAMiPhone 6S

DRAMPoP

PoP

3PoP(Package on Package)3D

44

NAND

18mNAND33

DBG

(Dicing before grinding)18m

15m18m

TSVNAND

TSVDRAM

3D

2009

45

SDXC512GB128Gbit Chip33256Gbit Chip17

2009.3

(Top Tire)

25um

(Bottom Tire)

700nm

M2

M1

TSV liner

120nm

Cu-Cu(

IMD (Inter-Metal Dielectric) PMDPre-Metal Dielectric

3TSVThrough silicon Via:3D

TSV

TSVSiSi

TSV

TSV

46

3D NAND+TSV16 1TByte NAND


201773D

TSV

47http://eetimes.jp/ee/articles/1707/14/news027.html 20170718

483D NAND TSV

2

512G bit(TLC)161T

BiCS FLASHNAND Dual x8 BGA-152Toggle DDR

512GB81TB16

512GB14181.35mm14181.85mm

2017

FOWLP (Fan-out Wafer Level Package)

AppleA10 (iPhone7)BGAFOWLP

http://techon.nikkeibp.co.jp/atcl/mag/15/398081/020800027/?rt=nocnt

http://electronicdesign.com/boards/package-interconnects-can-

make-or-break-performance

48

3D

FOWLP

3

TSMC

http://pc.watch.impress.co.jp/img/pcw/docs/662/558/html/23.png.html

Thrue Chip Interface (TCI)

Chip1

Chip n

4 turn

(DRAM4m

860m

TSVESD

Coil diameter D=3 x Z

3D

49

PEZYchipTCI

More MooreMore than Moore

SoC

CMOS

SiP

Analog/RF PassivesHV

PowerSensors

ActuatorsBiochips

50

More MooreMoore

3More Moore

More than Moore


More than Moore

Documents

2017 第4回 半導体技術の概要と動向kobaweb/news/pdf/2017/2017-10-24...MOS トランジスタ(FET)の構造 MOSﾄﾗﾝｼﾞｽﾀの基本構造はバイポーラトランジスタに比べてシンプル。P型MOSとN型MOSがある。

2017 第4回半導体技術の概要と動向kobaweb/news/pdf/2017/2017-10-24...MOS トランジスタ(FET)の構造 MOSﾄﾗﾝｼﾞｽﾀの基本構造はバイポーラトランジスタに比べてシンプル。P型MOSとN型MOSがある。