3 Edk Intro Mb Speedway 131

5/20/2018 3 Edk Intro Mb Speedway 131

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Introduction to MicroBlazeHardware Development

Featuring ISE Embedded Design Suite 13


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Course Objectives

Understand the MicroBlaze development flow andhow to use the Xilinx embedded systems tools

Introduce the new AXI Interface Specification Explore AXI Plug-and-Play IP

Utilize the Xilinx embedded systems tools to Design a MicroBlaze System

Develop a Software Application

Simulate and Debug an Embedded System

Create a bootloader and program serial flash


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Agenda

Overview and Xilinx Development Tools Review

Xilinx MicroBlaze Architecture Overview

Creating an Embedded Design

Lab 1- Adding a Processor to a ISE Design Exploring EDK IP Catalog

Lab 2 - Adding EDK IP

AXI Interface Introduction

Lab 3 - Adding Custom AXI IP

Embedded Simulation

Lab 4 Simulating a MicroBlaze Design

Debugging AXI peripherals with ChipScope

Lab 5 ChipScope Debugging

Using SPI Flash

Lab 6 SPI Programming


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Agenda




Lab 1- Adding a Processor to a ISE Design Exploring EDK IP Catalog



Lab 3 - Adding Custom AXI IP Embedded Simulation




Using SPI Flash



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Difficult to Find the Required Mix of Peripherals inOff the Shelf (OTS) Microcontroller Solutions

Even with variants, compromises must still be made

Why integrate a processor on an FPGA ?Ideal mix of peripherals

2@ UART

SystemRequirements

Core

Core

FLASHFLASH

RAMRAM

UARTUART

UARTUART

Microcontroller #1

Core

Core

FLASHFLASH

DDRDDR

UARTUART

CANCAN

Microcontroller #2

1

Must decide between inventory impact of multipleconfigurations or device cost of comprehensive IP

I2C

SPI

GPIO

FLASH

DDR SDRAM

CPU

CPU

GPIOGPIO SPISPI

TimerTimer

Lacks I2C & IncludesRAM vs. DDR SDRAM

CPU

CPU

SPISPI

TimerTimer

GPIOGPIO

I2CI2C

Lacks a Second UART &Includes Unnecessary IP

FPGAs flexibility allows ideal mix ofperipherals for YOUR application


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Selecting a Single discrete Processor Core withLong Term Solution Viability is Difficult at Best

Future proofing system requirements is difficult at

best

Why integrate a processor on an FPGA ?Changing Requirements

150 MHz

2@ UART

Future SystemRequirements

Core

Core

FLASHFLASH

DDRDDR

UARTUART

UARTUART

Microcontroller

100 MHz

2@ UART

Todays SystemRequirements

2

Changing discrete processor cores to accommodatenew requirements consumes valuable designresources

TIMER

I2C

SPI

GPIO

FLASH

DDR SDRAM

10/100 Ethernet

?100M

Hz

100M

Hz

SPISPI

TimerTimer

GPIOGPIO

I2CI2C

Completely meets currentsystem requirements

TIMER

I2C

SPI

GPIO

FLASH

DDR SDRAM

Xilinxs processor cores offer Performance scaling YOU control!


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Why integrate a processor on an FPGA ?Avoiding Obsolescence

Without Direct Ownership of the ProcessingSolution, Obsolescence is Always a Concern

A single core is used to create a family of Cs

3

PU

Core

PU

Core

FLASHFLASH

RAMRAM

GPIOGPIO

CANCAN

UARTUART

SPISPI

Microcontroller Variant #1 - High Volume Automotive

ore

ore

FLASHFLASH

RAMRAM

SPISPI

UARTUART

Microcontroller Variant #2 - Moderate Volume Consumer

FLASHFLASH I2CI2CMicrocontroller Variant #3 - Lower Volume Niche

The sheer number of C configurations can lead toobsolescence of lower volume configurations/variants

TimerTimerCP

U

CP

U

GPIOGPIO SPISPI

TimerTimerCPU

Co

re

CPU

Co

re

RAMRAM

GPIOGPIO

UARTUART

SPISPI

TimerTimer

?

Longevity of FPGAs Approaches

Longest Available Microcontrollers inthe Market


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Why integrate a processor on an FPGA ?Reducing cost, board complexity

Many Microprocessor Based Solutions ProvideLimited On-Chip Peripheral Support

Manufacturers create I/O devices to extend the functionality of

the base processor core

4

cessor

cessor

Interface

Interface

ParallelParallel

SerialSerialMicroprocessor

Chip-Set

An external, pre-defined interface between a P and its supportdevice limits overall system performance

Micropr

Micropr

MPU

MPU

PWMPWM

I/O Expansion Device

Pre-defined interfacelimits performance

FPGA Integration is next logical step


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Xilinx System on a Chip

Xilinx embedded processor innovation

Processor sub-system

Optional off-chip memory

Application-specific FPGA logic Interface to the real world

System Synchronization

MicroBlazeProcessorSubsystem

CustomFPGA

Application

DDR3 FLASH

MemoryController

UARTEthernet

ClockSynthesis

OSC

I/O andSignal

ConditioningProcessor

Related I/O


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Xilinx Spartan-6 LX9 MicroBoard

Compact Embedded Platform

USB-stick form factor card

Many reference design systems and tutorialsavailable

Software development and ChipScope licensesincluded

Expansion Interfaces


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MicroBoard Peripherals

Xilinx Spartan-6FPGA XC6SLX9-2CSG324

USB JTAG Circuitry 10/100 Ethernet Micro USB-UART

port Pushbuttons and

LEDs 4-bit DIP Switches


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MicroBoard Clock Generation and Memory

Programmable clock chip Texas Instruments CDCE913 3 outputs, upto 230MHz

64-MB LPDDR SDRAM(on back) Micron MT46H32M16

128 Mb Multi-I/O SPI Flash Micron N25Q128


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MicroBoard Power and Protection

Very compact 3-railPower 5x5 mm

USB over-voltageand ESD protection

Hi-Speed JTAGAccess Requires External Cable


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TE Interconnect Solutions for the Xilinx Spartan-6 FPGA LX9 MicroBoard

TE Connectivity designs, manufactures and marketsengineered electronic components for a broad array ofindustries and applications.

These solutions include circuit protection, switches, cablesand board-to-board and integrated magnetics I/O connectors as shown on the LX9.


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USB JTAG Circuit

No external programming cable required.

Compatible with iMPACT, ChipScope, SDK

Debugger

Full-speed

Av f

Module and chip solutions available


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Expansion Boards

Two PMOD sockets

Many low-cost add-onperipheral modules, as low

as $10 ADC

Wireless/Bluetooth

SD Card LCD


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Lab Equipment and Setup

UART interface through MicroUSB cable

JTAG interface through USB extension cable


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Lab Setup and Design Tools

Xilinx ISE Design tools

ISE

EDK

XPS SDK

ChipScope

m


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ISE Design Suite Software Products

SystemGenerator

EDK

SystemGeneratorEDK

EmbeddedEdition

DSPEdition

SystemEdition

Lo ic

ISEWebPACK

Limited Devices

Lo icLo ic

Logic

Edition

ChipScopePROSerial I/O Toolkit

Included in Spartan-6LX9 MicroBoard Kit

..

Edition

TargetedStandaloneProducts

Software

Developers

Debug Embedded

Developers

EDK SystemGenerator

ChipScopeSDK

ISE FoundationISim Light

PlanAhead

EditionEditionPlanAhead

ISE FoundationISim Full

DSP

Developers


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Operating System Support

Many OS options including Windows and Linux

ISE Design Suite 13.xOperating Support

WindowsXP

Pro

32/64

Windows7Pro

32/64

Windows

Serve

r2008

RedH

atLinux

Enter

prise4

WS32

/64

RedH

atLinux

Enter

prise5

WS32

/64

SUSE

Linux

Enter

prise11

32/64

ISE Design Suite

ISE WebPack

Chipscope Pro

EDK

SDK

SYSGEN


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Design Tool Flow

XilinxEmbedded

EDK

==

XPS

SDK

IP

Project Navigator Synthesis

Place & Route

Must have EDKand ISEfor embedded systems development. ChipScopeadds debugging capability

Value of using Xilinx embedded systems One tool chain for hard and soft microprocessors Reduces board complexity and cost Allows users focus on theirintellectual property

Software Developers only need SDK

Microprocessors

Ecosystem

DocumentationDocumentation

HW Debug

Cross-probingto software


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Whats in the Embedded Development Kit?

Xilinx Embedded Edition /Embedded Development Kit (EDK)

ProcessorsProcessors PlatformsPlatforms IPIPMicroBlae

%eference &esi'ns

am*les&oc+mentation

S+**ort

,- . Xilin Platform St+dio (XPS)

S- . Softare &e0elo*ment Kit (S&K)

Processor IP Library (PLB)

Tools S+iteTools S+ite cosystemcosystem&oc+mentation&oc+mentation

EDK Provides Comprehensive Support

!"#$PoerP1

%TOS

2rd

*arty deb+''ers2rd *arty traceEDK includes both toolsSDK can be purchased separately


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EDK Tool Suite

Xilin Platform St+dio (XPS)

Design environment for processor subsystem

Xilinx Microprocessor Project (XMP) file

Microprocessor Hardware pecification(M,S) file

!us "unctional Model (B3M) imulation

#$ipcope Pro logic analy%er integration

Softare &e0elo*ment Kit (S&K)

Project wor&space

Hardware platform definition (XML)

!oard upport Pac&age (BSP) oftware application

oftware debugging

XP

Hardware

Design

oftware

Design ' D

H*

Debug

H*

imulation


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Detailed EDK Design Flow

Processor IP

MP& 3iles

M,S 3ile

system4m5s

Plat6en

&I3

So+rce 1ode

(7,&L/7erilo')

Synt5esis

Board

1om*ile

Ob8ect 3iles

So+rce 1ode

(1 code)

MSS 3ile

system4mss&ri0er M&&

3iles

Lib6en

Softare "low,ardare "low

1reate 3P6A Pro'rammin'

(system4bit)

3P6A Im*lementation

(IS/Xflo)

,ardare

donload4bit

IP #etlists

&ata9Mem

IP:XA1T 3iles

system4+cf Link

ec+table

Libraries

Library ML&

3iles

Design Starts withHardware

And Transistionsto Software

Covered more in Introduction

to MicroBlaze SoftwareDevelopment Speedway


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Xilinx Platform Studio (XPS)System Assembly View Bus Interface Tab

Project +nformation

,rea -ists project files .abs select Project

files and +P #atalog

Panel $ows interface

connections

#onsole $ows Messages

and .#- commands


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Xilinx Platform Studio (XPS)System Assembly View Ports Tab

ystem

.abs/

' !us +nterfaces

' Ports

' ,ddress

,ssembly0iew


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XMP File

The XMP file is the projectsupport file for XPS

Takes on the name of theproject, .xmp

In the labs, mb_system.xmpis used

Contains and controls

es a ma e up e pro ec ; a s, e e

Tools settings

GUI settings

The XMP file is typically the embedded source file that containsthe XPS component in Project Navigator

Is the file type that identifies the embedded processor componentsource

Alternative to using system_stub.vhd/v


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Checkpoint!

What EDK tool is used to create and define theMicroBlaze Processor?

XPS Hardware

What EDK tool is used to create MicroBlazeSoftware?

o tware

What is the XMP File?

Contains files that make up XPS Project including tool settings


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Agenda

Overview and Xilinx Development Tools Review Xilinx MicroBlaze Architecture Overview


Lab 1- Adding a Processor to a ISE Design

Exploring EDK IP Catalog







Using SPI Flash



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MicroBlaze Processor Block Diagram

Optional Features


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The Processor Core

InstructionFetch &Decode

ProgramCounter

Processor Core

ExecutionUnit

Register files of32 registers by 32-bit

Add, Subtract, Shift,Logical Operations,

Multiply, MAC

2 execute

I-Cache

File

D-CacheCache sizes rangefrom 2KB to 64KB

*Typical pipeline stages, functions, quantities & sizes

Primary BusPrimary Bus

3fetch &decode memory/

writeback

3 to 5 stage pipeline


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Instruction Pipelining

Instruction pipelining overlaps multipleinstructions as they are executed

fetch execute writebackfetch execute writeback

fetch execute writeback

Inst #1Inst #2

Inst #3

Improves the utility of the various functionalblocks in the processor core - fetch/decode,register file, ALU

Dramatically Improves the performance of the core

Increases the complexity of the processor core

Incorrect prediction requires pipeline flushing


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MicroBlaze Processor Basic Architecture

Embedded soft RISC processor (version 8.10a) 32-bit address and data buses

32-bit instruction word (three operands and two addressing modes)

32 registers (32-bit wide)

Three or five pipeline stages (three stages if area optimization isselected)

Big-endian format

Full Harvard architecture AXI4 interface

LMB for connecting to local block RAM (faster), instruction, and data(user selectable)

AXI4 streaming interface: dedicated, unidirectional point-to-point datastreaming interfaces; support for up to 16 streaming interfaces

Dedicated master AXI ports for instruction and data caching with four(eight)-word cache line size and critical word-first access capability


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MicroBlaze Processor Features

ALU Hardware multipliers/DSP48

Barrel shifter

Floating Point Unit (FPU)

Implements IEEE 754 single-precision, floating-point standards

Supports addition, subtraction, multiplication, division, andcomparison

Program counter Instruction decode

Instruction cache

Direct mapped

Configurable caching with CacheLink Configurable size: 2 kB, 4 kB, 8 kB, 16 kB, 32 kB, 64 kB


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MicroBlaze Processor v8.10a PerformanceMicrocontrollerConfiguration

MicroBlaze with localmemory and debugger,

external memory controller,UART, FSL link, 2K I-Cache, 8K D-Cache

DMIPS Configuration


UART, timer

MicrocontrollerConfiguration


external memory controller,UART, FSL link

DMIPSConfiguration

MicroBlaze with local

memory and debugger,UART, timer

With Performance-Optimized MicroBlaze(1.19 DMIPs/MHz) * Note (1)

With Area-Optimized MicroBlaze(0.95 DMIPs/MHz)

Virtex-6 FPGA (-3)

z z z z

5788 LUTs 365.3 DMIPs 5118 LUTs 229 DMIPs

Spartan-6 FPGA (-3)

129 MHz 154 MHz 111 MHz 131 MHz

3157 LUTs 183.3 DMIPs 2447 LUTs 125 DMIPs

(1): Adding Branch Optimizations to Performance Optimized

MicroBlaze increases performance to 1.30 DMIPs/MHz)


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New MicroBlaze Processor v8 Features

High-performance AXI4 interface and AXI4 peripherals

Memory Management Unit (MMU) implements virtualmemory management

PPC405 processor MMU compatible Virtual memory management provides greater control over memory

protection, which is especially useful with applications that can usean RTOS

Processing improvements New float-integer conversion and float-square root instructions Speeds up

FP Int conversion Int FP conversion

FP square root

Enhanced XMD support


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New MicroBlaze Processor v8 Features

MicroBlaze offers Fault Tolerant features ECC (Error Correction Code) support on LMB BRAMs

Parity support on internal BRAMs

Detects and correct soft errors in BRAMs

Significantly reduces overall failure susceptibility

Must click here and here


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MicroBlaze Fault Tolerance in 13.1 (continued)

See AR# 40863 for more details


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AXI Stream Link Interfaces

AXI4 streaming interface to/from MicroBlaze processor Was FSL link.

Unidirectional, point-to-point FIFO-based communication

Built-in programmable depth FIFO

Simplex connectionprocessor to/from FIFO

Direct connection to CPU core, internal pipeline

Native to MicroBlaze processor hardware Enable up to 16 in/out pairs (channels)

Dedicated register to/from FIFO assembler instructions

Mi Bl P M S


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MicroBlaze Processor Memory Space

Memory and peripherals The MicroBlaze processor uses

32-bit addresses

Special addresses

MicroBlaze processors must haveuser-writable memory from0x00000000 through 0x0000004F

Each vector consists of two instructions

4x""""5""""

,X+ Memory

,X+ Perip$erals

IMM followed by a BRAI instruction toaddress full memory range

All instructions take one clock cycle,except the following

Load and store (two clock cycles) Multiply (two clock cycles)

Branches (three clock cycles,can be one clock cycle)

4x444454444

4x444454446

4x444454414

4x444454416

7eset ,ddress

8xception ,ddress

+nterrupt ,ddress

LMB Memory

7eserved

4x444454424

4x444454426

4x44445449"

!rea&

Hardware 8xception

Ch k i t!


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Checkpoint!

Name a few optional features of MicroBlaze.

AXI Support , Fault Tolerance, MMU/VPU, FPU improvements

What is typical performance for MicroBlaze in

Spartan-6 (in MHz)?110-130 MHz

Where do the reset, interru t and exce tion vectors

reside in the MicroBlaze processor?0x00000000 through 0x00000020

What is the starting address of the Local Memory(LMB)?

Immediately above the reserved address space, 0x0000004F

S


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Summary

The MicroBlaze processor balances executionperformance against implementation size

The MicroBlaze v8 processor supports the AXI4 interfacestandard and offers an MMU

Being a soft core processor, many features areimplemented on demand

Simplex; up to 16 in and 16 out AXI stream interface on fabric side

Fault Tolerance significantly reduces overall failuresusceptibility


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(Take a Break)

Agenda


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Agenda

Overview and Xilinx Development Tools Review Xilinx MicroBlaze Architecture Overview









Lab 5 ChipScope Debugging Using SPI Flash


System Architecture Considerations


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At minimum, MicroBlaze requires 2-3 interfaces JTAG optional but used in nearly every design.

ResetControl

ResetInput

ClockSynthesis

OSC MicroBlazeProcessor

FPGA

MDM(Debug)

JTAG



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Choice of single or dual processor system MicroBlaze processor (soft core)

ZYNQ (ARM-based hard core processor)

PowerPC (hard core processor, Virtex-5) System reset

Clocking circuitry

JTAG connectivity for hardware/software debug XPS bus interfaces

AXI-4

AXI-4 Streaming

AXI-4 Lite

PLB

MicroBlaze Architecture


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RESET: PROC SYS RESET Component


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RESET: PROC_SYS_RESET Component

A reset control circuit is neededto coordinate reset behaviorbetween the system reset inputs,processor, bus, and peripheralresets.

A Processor System ResetModule is a required componentn an em e e sys em o

accomplish this task.

Xilinx Processor System Resetmodule design allows you totailor the design to suit yourapplication by setting certainparameters to generate thedesired reset

PROC SYS RESET Component


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PROC_SYS_RESET Component

Asynchronous external reset input issynchronized with the clock

Asynchronous auxiliary external resetinput is synchronized with the clock

Both the external and auxiliary reset

inputs are selectable active highor active low, default = high.

Selectable minimum pulse width for resetinputs to be recognized

Selectable load equalizing

DCM-locked input Power-on reset generation

Sequencing of reset signals coming out of reset First: Bus structures come out of reset

Second: Peripherals come out of reset 16 clocks later UART, SPI, and IIC, for example

Third: The CPUs come out of reset 16 clocks after theperipherals

PROC SYS RESET Block Ports


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PROC_SYS_RESET Block Ports

Name InstructionsReset Block Inputs

Slowest_sync_clk Slowest Synchronous Clock - Typically AXI clock

Ext_Reset_In External Reset Input - Active high or low based uponthe generic C_EXT_RESET_HIGH

Aux_Reset_In Auxiliary Reset Input - Active high or low based uponthe generic C_AUX_RESET_HIGH

MB_Debug_Sys_Rst Reset input generated by the MicroBlaze processor

Debug Module (MDM)

Dcm_locked DCM locked will cause all outputs to remain activeuntil cm_locked goes high which will cause the resetsto sequence to their inactive state.

Reset Block Output

MB_Reset Resets the MicroBlaze Processor



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Clock Generator Component - clock generator


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Clock Generator Component clock_generator

The Clock Generator helps you configure DCM andPLL components for your embedded system

One input reference clock

One feedback clock for clock deskew

Up to 16 output clocks, whose frequencyrange refer to DCM and PLL primitives

Fixed phase shift (0 to 359 degrees) foroutput clocks, Variable phase shift on

rtex- ev ces

Grouping output clocks for reducing skewamong these clocks. The grouped clockswill be the output of the same DCM, PLL,or PLL with deskew adjust

Input and output clock frequency range checkaccording to device family

Supports both active high and active low external reset

Clock Wizard


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Clock Wizard

Use Clock Wizard toconfigure Clock Generator

System Tab

Use this tab to enter values for clockconfiguration

Processors, buses, and peripheralsneedin clocks are automaticall added

Individual clock signals areautomatically identified on a percomponent basis

Selectable output frequencies

Selectable buffer insertion

Automatic DRC via Validate Clocksbutton and when OK is selected verifiesthat selections can be legally generated

Using the Clocking Wizard


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g g

Ports Overview Tab Use this tab to view a table of

the current clock configuration

Informational only, no editing

Generated clocking componentschematic view available

Using the Clock Generator - Configure IP


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g g

Accessed viaConfigure IP tomodify the initialClock Generator

settings Input clock frequency

Clock feedback in

oc ee ac ou

Output frequency,phase, and bufferingof up to 16 clocks

Reset polarity

Variable phase shift



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JTAG TAP Options


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p

At design time, you have control over whether the JTAG TAP ofeach processor (in the case of multiple processors) isincorporated into the FPGA JTAG TAP chain after FPGAconfiguration or whether it remains a separate chain

This is accomplished by instantiating or not instantiating thededicated JTAGPPC block

For the MicroBlaze processor, the MDM (MicroBlaze Debug

BSCAN component to gain accessibility to the FPGA JTAG pins When both a MicroBlaze and PowerPC processor are

incorporated in the same design, an internal JTAG daisy chaincan be automatically created by using and sharing the BSCANcomponent

JTAG Configuration/WakeupWith Combined JTAG Chains


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With Combined JTAG Chains

Combined JTAG chain designs allow configurationof FPGA, CPU, and external memory all at once

Via JTAG, system configuration can occur as follows

Configure the FPGA Identify processors present via their debug module

Configure the CPU, CPU caches, and any externalmemory a s access e y e

Download code into memory, BRAM or external

Execute the code

JTAG commands can exist as Serial Vector Format

(SVF) in configuration memory to facilitate use withthird-party software and download cables

Checkpoint!


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What is the purpose of Proc_sys_reset?

Coordinates reset behavior between the system reset inputs,processor, bus, and peripheral resets.

How does the Clock Generator module work?Determines DCM/PLL configuration, examines the systemprocessors, buses, and peripherals and then builds an

clock outputs. The clock outputs can be configured by theuser for frequency, phase, and clock buffer insertion.

Name an example of a peripheral whoseinstantiation is benefited by the presence of the

Clock Generator moduleMemory Controllers as they require multiple phase lockedclocks.

Summary


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The Processor System Reset component providescontrol over the reset of the entire embedded system

The Clock Generator component automaticallyinserts configurable clocks for processors, memorycontrollers, and peripherals.

A combined JTAG chain enables the linking of theFPGA and MDM JTAG chains

This allows the use of the ChipScope Pro logic analyzer

and the GDB software debugger

Embedded Development Design Flow


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1. Create a new EDK project as a new source in Project Navigator

2. Use the Base System Builder (BSB) to construct your basicembedded design

3. Run PlatGen (Hardware > Generate Netlist) to make your HDLinstantiation files and netlist for each component in your

embedded design. Alternatively, Export Design to SDK.4. Close XPS and return to Project Navigator

5. Export processor hardware launch SDK and create a new

6. Create a new software application project in the SDKworkspace

7. Compile your software with the GNU cross-compiler usingSDK

8. In Project Navigator, add an SDK-created ELF object to theproject and generate the programming file

9. Implement the embedded design with the ISE software

10. Download your FPGAs completed bitstream using iMPACT

Launching a New XPS Project from the ISESoftware Project Navigator


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Software Project Navigator

It is recommended that XPSprocessor projects belaunched from ProjectNavigator in the ISE software

suite

Easy to integrate a processorsub-system with other FPGAlogic

Access to more Xilinx pointtools

Easy software integration

The processor sub-system can

be place anywhere in thedesign hierarchy

New Project Creation Using the Base SystemBuilder (BSB) Option


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Builder (BSB) Option

Select a target board or customdesign

Select a processor

Configure the processor

Select and configure boardspecific interfaces

Add internal peripherals

Generate example software

applications Peripheral and memory tests

Generate design files

Generated files include the following

system.mhs

system.xmp

data/system.ucf

pcore directory (empty)

BSB A simple wizard for creating embedded systems


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Every processor system requires certain modulesthat are highly configurable and can be complex tointegrate

Processor system module design overhead

Processor

Processor bus (AXI4, LMB, AXI4 Streaming)

Clocking Module Debug Module

Base System Builder is an ideal tool to accomplish

this design integration Copying and pasting from an existing and working

design MHS file is another alternative

Choose an Interconnect System


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Traditional PLB v46 or AXI Will determine the remaining BSB wizard selections

,X+ only supported for t$e

Micro!la%e: processor

P-! v9; is traditional support

for bot$ t$e Micro!la%e andPowerP#< processors

Welcome


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Note the progress thermometer across the top You can load an existing settings file (.bsb

extension)

=seful if you $ave alreadycustomi%ed t$e !! file for

a custom demo board

#$ec& t$e More +nfo buttonfor $elp information about

XP

Selecting a Board


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Xilinx and itsdistribution partnerssell demo boards with awide range of added

components This dialog box allows

you to quickly learnmore about all availabledemo boards

If you want to target ademo from anothervendor, their XBD filesmust first be installed

Note that you can alsocreate your own BSB filefor a custom board

BSB-Supported Platforms


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AXI-supported Xilinx hardware boards Spartan-6 FPGA SP601/605 boards

Virtex-6 FPGA ML605 boards

All Avnet Spartan-6 and Virtex-6 Evaluation Boards Custom board

Board definition files are supported in the IPXACTformat

New industry standard

Board definition files (XBD, XBD2(IPXACT)) for third-party boards can be downloaded from the website of

the board vendor Links from the BSB wizard and Xilinx embedded Web

page

Selecting Single or Dual Processors


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BSB AXI-basedsystems presentlysupport only asingle processor-

based system More processors

can be added

System AssemblyView

Configuring the Processor Reference Clock


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Reference clock is boardoscillator frequency

Processor clockfrequency is the clockrate connected directly

to the processor

Bus clock frequency isthe clock rate of all busper p era s n e

system These selections will

automatically customizethe clock generatormodule

The appropriate debuginterface is addedautomatically

Configuring the I/O Interfaces


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Choose the peripherals you need from those available foryour demo board

Peripherals canbe added orremoved

Most peripheralsare customizablevia drop-down

lists whenselected

Many peripheralssupport the use ofinterrupts

Internal peripherals exist for all board hardware configurations

Cache Configuration


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Cache is automatically enabled for off FPGA memory Cache size is selectable

Creating the System


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BSB creates a MHS Filefor your system

The MHS references everyprocessor, bus, peripheral, andmemory in your embeddedsystem It contains connection information

and parameter settings for everyperipheral

Each peripheral has a defaultparameter setting stored in anMPD file MHS settings override MPD

default settings

Memory mapping informationfollows the nature of the

chosen processor for yoursystem

MHS File

MicroBlaze Hardware Specification


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MicroBlaze Hardware Specification

Hardware netlist of the processor sub-system Main source file of the processor sub-system

Component instances are from IP Catalog

Shows component instances and their connectivity

Stored as a text file

Named after the project, .mhs

Full defines the embedded s stem hardware

Does not include tool setting options (these are part of the ISEProject file, assuming ISE is top level project.)

The System Assembly View is the IDE that builds the MHS file

Hand editing is also allowed

XPS will not open a project whose XPS file has an error Usually happens when hand editing mistakes are made

May require fixing in Notepad, because XPS will not re-open

Leveraging BSB for the MicroBlaze Processor


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MHS File

MHS File Quiz B6I# ai;+artlitePA%AMT% I#STA#1 < %S929;=art;>PA%AMT% ,-;7% < >4?>4a

PA%AMT% 1 BA=&%AT < @??


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To the right is a snippet of the MHS filethat was generated by BSB

What do the MHS snippets instantiate?

Can you identify the addresses of thecomponents?

What is the difference between

;

PA%AMT% 1;&ATA;BITS < PA%AMT% 1;=S;PA%IT" < ?

PA%AMT% 1;O&&;PA%IT" < >

PA%AMT% 1;BASA&&% < ?C??????

PA%AMT% 1;,I6,A&&% < ?C??ffff

B=S;I#T%3A1 S;AXI < aiClite;?

PO%T TX < %S929;=art;>;so+t

PO%T %X < %S929;=art;>;sin

PO%T S;AXI;A1LK < clk;22;2222M,PLL?

#&

parameters and ports?

Be careful when editing the MHS

Any mistakes will be reflected in

the GUI

Some mistakes will not allow you to re-open the System Assembly View

Must use text editor to fix

;

PA%AMT% I#STA#1 < L&s;CBits

PA%AMT% ,-;7% < >4?>4aPA%AMT% 1;6PIO;-I&T, < C

PA%AMT% 1;ALL;I#P=TS < ?

PA%AMT% 1;I#T%%=PT;P%S#T < ?

PA%AMT% 1;IS;&=AL < ?

PA%AMT% 1;BASA&&% < ?C???????

PA%AMT% 1;,I6,A&&% < ?C???ffff

B=S;I#T%3A1 S;AXI < aiClite;?

PO%T 6PIO;IO;O < L&s;CBits;T%I;O

PO%T S;AXI;A1LK < clk;22;2222M,PLL?

#&

Continuing with XPS

The BSB creates a completed design of your system as specified


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The BSB creates a completed design of your system as specified

A User Constraint File (UCF) is created that contains

Pin assignments

For any MicroBlaze peripherals that require external FPGA I/O

Timing constraints

Based on the hardware board selected

Based on the clock frequency specifications

After com letin BSB start usin XPS to add more com onents ormodify the design and build the hardware netlist

UCF File

>> ystem level constraints


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A UCF file has been generatedby BSB, based on your

peripheral selections

The UCF mainly consists of

location, timing, and areaconstraints

It will not be modified when

>> ystem level constraints

?et fpga545cl&515sys5cl&5pin .?M5?8. @ sys5cl&5pinA

.+M8P8# .5sys5cl&5pin @ P87+BD sys5cl&5pin 144444 &H%A

?et sys5cl&5pin .?M5?8. @ sys5cl&5pinA

.+M8P8# .5sys5cl&5pin @ P87+BD sys5cl&5pin 14444 psA

?et sys5rst5pin .+CA

>>>> Module -8Ds56!it constraints

deleting or adding components to

the design

Changes must be done by

hand

Why has the TIG been placed?

What pin assignments or

attributes do you see here?

e pga5 5 s5 5 5 5p n E @ A

?et fpga545-8Ds56!it5CP+B5+B5pin4E +B.,?D,7D@-0#MB16A

?et fpga545-8Ds56!it5CP+B5+B5pin4E P=--DB?A

?et fpga545-8Ds56!it5CP+B5+B5pin4E -8@-BA

?et fpga545-8Ds56!it5CP+B5+B5pin4E D7+08@2A

?et fpga545-8Ds56!it5CP+B5+B5pin1E -B# @ ,D29A

?et fpga545-8Ds56!it5CP+B5+B5pin1E +B.,?D,7D@-0#MB16A

?et fpga545-8Ds56!it5CP+B5+B5pin1E P=--DB?A

?et fpga545-8Ds56!it5CP+B5+B5pin1E -8@-BA?et fpga545-8Ds56!it5CP+B5+B5pin1E D7+08@2A

Checkpoint!


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Name some of the components that are common to everydesign.

Processor, Reset block, Clocking module, Debug module, AXI (orPLB) bus

What is an MHS File?Microprocessor Hardware Specification file

Hardware netlist of the embedded processor systemText format and is typically edited graphically in XPS

When does a BSB UCF file need to be updated?UCF file is generated once when BSB finishes a design for a specifiedhardware development boardIf peripherals with external FPGA pins are added or deleted to or fromthe design, the UCF file must be updated manually.Also, if any of the clock module timing is changed, this may require amodification to related timing constraints in the UCF.

Summary


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Creating processor designs is easy with Base System Builder

Modifying a BSB-created hardware design is easily done withXPS

MHS File defines hardware platform of processing system

The System Assembly view is a graphical editor of the MHS file


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Kit

Software Flow - Exporting Hardware Platform to SDK


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Software development isperformed with the XilinxSoftware Development Kit(SDK)

A hardware image XML file,generated by XPS, defines thehardware platform for which

XPS

developed

XML exported from XPSor Project Navigator

The SDK software tools willthen associate the software

project to the hardwarePro8ect

#a0i'ator

Software Development Kit (SDK)


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Full-featured software design environment Separate tool from Project

Navigator and XPS

Base on popular Eclipse

open-source IDE Used for software applications only;

hardware design and modifications are done in XPS

e - n egra e env ronmen or seam ess e ugg ng o

embedded targets Sophisticated software design environment with many options

and features with support for

Multiple processor platforms

Multiple software Board Support Packages Multiple software applications

Superior C/C++ code editor and error navigator

SDK Application Development Flow

Platform Studio SDK


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Create SoftwareApplication Project

Add Sources

Generate HardwarePlatform (XML)

Libraries andDrivers

XPS via BSBGenerate SoftwareBoard Support Package

and Edit

Compile and Link

Done?Import ELF file anddownload to board

Debug and Profile

Yes No

iMPACTIDE in Project Navigator,batch mode operation inSDK and XPS

Board Support Package


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Primary BusPrimary Bus BridgeBridge Secondary BusSecondary Bus

SPIEEPROMSPIEEPROM

DDRSDRAMDDRSDRAM

UARTUART TimerTimer IntcIntc10/100Ethernet10/100Ethernet

XEmac_mWriteReg ( );

xemac.hXTmrCtr_mWriteReg ( );

XTmrCtr_IsExpired ( );

xtmrctr.h

libxil.aXEmac_mWriteReg ( );

XEmac_SendFrame ( );

...

XSpi_mSendByte ( );

XSpi_GetStatusReg ( );

...

XUartLite_SendByte ( );

XUartLite_GetStats ( );

...

XTmrCtr_mWriteReg ( );

XIntc_mEnableIntr ( );

...

_

...

XUartLite_SendByte ( );

XUartLite_GetStats ( );

...

...

XSpi_mSendByte ( );

XSpi_GetStatusReg ( );

...

xspi.h

uartlite.h

_

XIntc_mEnableIntr ( );

...

Board Support Packages (BSPs) arecollections of parameterized drivers for

a specific processor system

SDK Workbench ViewsC/C++ Perspective

Active Perspectiveindicated here


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C/C++ project outlinedisplays the elements of aproject with file decorators(icons) for easyidentification

C/C++ editor for integratedsoftware creation

elements of the software

file under developmentwith file decorators (icons)for easy identification

Problems, Console,

Properties views list outputinformation associated withthe software developmentflow

Building the Software Application


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The software toolchain consists of the followingGNU tools

Pre-processor (optional)

Compiler

Assembler

Linker

A software build executes all of the tools in

sequence and produces an ELF file A software build happens when

Saving a resource file

Selecting Project > Build All

Directory Structure

SDK projects are place in the application

di t th t ifi d h SDK


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directory that was specified when SDK waslaunched WorkSpace is commonly used.

Each project will have multiple directoriesfor system files and configurations

Configurations are property tool optionpermutations of the software application.

Each configuration has project properties set.

for each.

Release configuration

Debug configuration

Profile configuration

A Debug configuration is created by default

Board Support Packages associated witheach software application

Software Application Linker Script


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A linker script isnecessary for everysoftware application

Dictates wheresoftware is to beplaced in memory

Generate linker script

Use default location forlinker script file forautomatic insertion aslinker option

Merging Hardware and Software Flows

Software Application needs to be

merged with Hardware so


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merged with Hardware soMicroBlaze has code to executeupon bootup.

Only for application software that

resides in block RAM Can be done in SDK or ISE

In ISE, add the software ELF

SDK

object file as a project source

Create a bitstream file Generate bitstream

Data2MEM is automaticallyexecuted as part of the Generate

Bitstream command Software application is now pre-

loaded into the block RAM

ISETool

Data2Mem - Memory Initialization

Block RAM memory must be initialized with program code soth t th h thi t t ft FPGA


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that the processor has something to execute after FPGAconfiguration

Each bit of FPGA block RAM isrepresented as a bit in the bit file,you need

The compiled executable

executable.elf

_bd.bmm .elf

Hardware design implemented

.bit

The BMM file generated by PlatGen

/implementation directory

Data2MEM can be launched from

Project Navigator SDK

XPS

&ata9MM

.bit

_ .

Checkpoint!

What file is required from XPS to load project intoS ? ?


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What file is required from XPS to load project intoSDK? How is it created?

XML FileMust be exported from XPS tool

What does the Linker Script do?

What tool merges software application withhardware bitstream? How is it invoked?

DATA2MEM

ISE Add ELF file to Project, Generate BitstreamSDK Program FPGA, select ELF File to initialize BRAM

Summary

SDK is a comprehensive software development environmentfor simple software and firmware and for complex applications


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for simple software and firmware and for complex applications

Based on the Eclipse open-source IDE

WorkSpace

Projects Perspectives

Views

Full tool and environment option control

Multiple project and processor support Easy access to BSP and linker script generation tools

Agenda


Xili Mi Bl A hit t O i


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Exploring EDK IP Catalog Lab 2 - Adding EDK IP



Embedded Simulation





Lab Instructions

Labs are self guided you will find accompanyingt b t di ti d ill t t d fi th t


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Labs are self guided, you will find accompanyingstep-by-step directions and illustrated figures thatprovide detail for performing the lab.

Labs build on one-another. So labs must be

completed before starting next lab.

Directory structure is under

C:\SpeedWay\Spring_11\EDK\ EDK_Tutorial your work space

Solutions files containing the completed lab

Lab 1: Hardware Construction with the BSB

Introduction

This lab guides you through the process of using the Xilinx


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This lab guides you through the process of using the XilinxProject Navigator (the ISE tool) and Platform Studio (XPS) tocreate a simple processor system. In the process, you will useBSB to create an MHS file, import design to ISE, and generate a

bitstream

Objectives

Build an embedded processor system using Base System Builder

Generate a top-level wrapper for the embedded processorcomponent in ISE Project Navigator

Implement the project in the ISE tool

Create a sample C application and download it with SDK

Lab #1 - MicroBlaze Platform

DEBUGJ AXII t t

AXI-4

AXI &&%2 Memory1ontroller 32M x 16AXI-4I-Cache


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MicroBlaze

MDM

DEBUG

D-LMB

TAG

Interconnect

Block

1ontroller 32M x 16LPDDR

axi_uartlite

axi_gpio LEDs

USB-

UART

AXI-4-Lite

AXI-4-Lite

Spartan-6MCB

AXI-4D-CacheAXI-4-Lite

BRAMI-LMB

AXI

Interconnect

Block

AXI-4

AXI relationshipMaster Slave

axi_timerAXI-4-Lite

Clock_generator

Proc_sys_reset

ResetSwitch

OSC @

66MHz

External Connection

axi_intcAXI-4-Lite

ExternalPort

axi_spi128MbFlash

AXI-4-Lite

Agenda




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Embedded Simulation





EDK IP Catalog


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IP Peripherals

Most IP cores arefree to use


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free to use

The more exotic IPcores are licensed

$$ Xilinx developed,

delivered, andsupported

Evaluation IP installs witha 90-day evaluation

license You can also add

your own IP coresto the catalog

Core Sizes

The size of each core is available in the data sheetFor example the XPS LL TEMAC soft Ethernet core


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e s e o eac co e s a a ab e t e data s eet For example, the XPS LL TEMAC soft Ethernet core

data sheet contains the following table

Adding IP to the Design

To add hardware in a

1


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new, empty project, or toan existing project, selectthe IP Catalog tab in

XPS

Expand the group(s) of

1

2

23

IP in the left window

Select an IP and drag itto the System AssemblyView window

Will automatically be

added to the systemMHS file

3

1

Assigning Addresses

Select theAddresses tab

1

1 3


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Expand (+) to seeaddresses

Click in the Sizecolumn and selectthe desired size or

2

3

Addresses

Optionally, Enter thebase address Default address will

automatically begenerated

XPS calculates thehigh address fromthe base addressand size entries

4Mapped New Components

4

Connecting Ports

1 Select the Ports tab 1 F


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2

3

Expand ports listing

Click under the Net

column and select theappropriate signal

If the ort is external in the

9

F

design, make it external. A

default name will becreated

For global ports, click Add

External Port and assign

a name

3

All External Ports willbe displayed in theExternal Ports List

Port Filters

Port filters remove

undesired congestion in


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g

the net column by sorting

on ports of interest

Parameterize IP Instances

Double-click or right1


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g

click the instance and

select Configure IP to

open the configurableparameters dialog box

(refer to the datasheetDefault 0alues

1

nee e

Default values are

shown. Customize the

parameters that you

want

22

MHS File will be Updated

XPS Platform Generator (PlatGen)

After defining the system,

hardware and connectivity,th t t i t t


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the next step is to createhardware netlists with thePlatform Generator (PlatGen)

Alternatively, run Synthesisin ISE Project Navigator (Lab)

-ibrariessystemGucf

systemGbit

+8*Xflow

Hardware

Data2M8M

downloadGbit

#ompile

-in&

Bbject "iles

8xecutable

ource #ode (#)

-ibCen

M "ilesystemGmss

8D+"

+P ?etlists

H ource #ode (HD-)

ynt$esisProcessor +P

MP& "iles

MH "ile

system4m5s

Plat6en

"ocus

Here

Hardware Design Generate Netlist (PlatGen)

PlatGen inputs the following files

Microprocessor Hardware Specification (MHS) file


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Microprocessor Peripheral Definitions (MPD) file

PlatGen constructs the embedded processor system in the

form of hardware netlists for each component (HDL wrappersand implementation netlist files)

MHS file parameters override MPD parameters

Micro*rocessor Peri*5eral &efinitions (MP&) 3ileM,S 3ile

MPD contains all of t$e defaults

PlatGen

hdldirectory

system [vhd|v] file (if top level)PlatCen'Cenerated Directories

Use these ifimporting toPlanAhead


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system.[vhd|v] file (if top level)

system_stub.[vhd|v]file (if

submodule)

peripheral_wrapper.[vhd|v]files

implementationdirectory

project5directory

$dl directory

implementation directory

synt$esis directory

peripheral_wrapper.ngcfiles

system.ngcfile

system.bmmfile

synthesisdirectory

peripheral_wrapper.[prj|scr] filessystem.[prj|scr]files

PlatGen Memory Generation

Memory generation

Platform Generator generates memory using block RAMs


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g y gbased on the memory sized allocated to the memorycontroller

A BMM file is also generated. Defines the architecture of the memory built

Placement information is later added to the BMM file b PAR

Used by Data2MEM, to load ELF software object into block RAMs,

by indicating the appropriate BRAM bits in the BIT file to populate Current block RAM controllers include the following

XPS block RAM controller (xps_bram_if_cntlr)

AXI block RAM controller (axi_bram_cntlr)

LMB block RAM Controller (lmb_bram_if_cntlr)

System.bmm File

Generated by PlatGen when it instantiates BRAM

Netlist indicating the number of block RAMs used and their


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,DD785P,#8 plb5bram5if5cntlr525bram5combined #BM!+?8D 4xfffe4444/4xfffe3fffI

,DD7857,?C8 7,M!32

!=5!-B# plb5bram5if5cntlr525bram*plb5bram5if5cntlr525bram*ramb3;54 31/29I A

plb5bram5if5cntlr525bram*plb5bram5if5cntlr525bram*ramb3;51 23/1;I A

plb5bram5if5cntlr525bram*plb5bram5if5cntlr525bram*ramb3;52 1F/6I A

connection topology.

p 5 ram5 5cn r5 5 ram p 5 ram5 5cn r5 5 ram ram 5 / A

8?D5!=5!-B#A

8?D5,DD7857,?C8A

8?D5,DD785P,#8A

,DD785P,#8 xps5bram5if5cntlr515bram5combined #BM!+?8D 4xffffc444/4xffffffffI

,DD7857,?C8 7,M!32

!=5!-B#

xps5bram5if5cntlr515bram*xps5bram5if5cntlr515bram*ramb3;54 ;3/96I A

xps5bram5if5cntlr515bram*xps5bram5if5cntlr515bram*ramb3;51 9J/32I A

xps5bram5if5cntlr515bram*xps5bram5if5cntlr515bram*ramb3;52 31/1;I Axps5bram5if5cntlr515bram*xps5bram5if5cntlr515bram*ramb3;53 1F/4I A

8?D5!=5!-B#A

8?D5,DD7857,?C8A

8?D5,DD785P,#8A

PlatGen BMM Memory Sizes

Memory size mustbe aligned on a 2n


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3P6A Arc5itect+reMemory Sie (kB)

29:bit LMB or PLB0C B+s

Memory Sie (kB)

C:bit PLB0C B+s

partan


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What will the BAUDRATE for this peripheral be?

If the MPD file has the following parameter: C_BAUDRATE = 9600

If the MHS file has the following parameter: C_BAUDRATE = 115200

The MHS file overrides MPD, thus 115200.

PlatGen

What are PlatGens inputs?

MHS and all MPD files

What are PlatGens outputs?

NGC Netlist, HDL wrapper files for all cores, and BMM files

Summary

Adding EDK IP is easy

The primary output of PlatGen is a netlist for each componentof your embedded hardware platform


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of your embedded hardware platform

Each bus, peripheral, and processor in your hardware system will haveits own NGC netlist (stored in the implementation directory)

PlatGen also makes a synthesis and an HDL directory that contains allthe necessary scripts and wrappers to synthesize your design

PlatGen automatically generates a memory array structure

Only for block RAM controllers: axi_bram_cntlr, xps_bram_if_cntlr, and

lmb_bram_if_cntlr Size is determined by the address space allocated to the memory

controller component

BMM file defines the memory subsystem structure

Generated memory size is always on 2n boundaries

Agenda





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Embedded Simulation Lab 4 Simulating a MicroBlaze Design



Using SPI Flash


Lab 2: Adding EDK IP

Introduction

This tutorial demonstrates how to add and modify peripheralsto an existing MicroBlaze system using Xilinx Platform Studio


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to an existing MicroBlaze system using Xilinx Platform Studio(XPS). The system from the previous tutorial will be used as thestarting point

Objectives

ow o a an per p era

How to connect the new peripheral to the existing system

How to modify the peripheral options

How to add constraints for the new peripheral

How to add a software application to support the new peripheral

Lab #2 - MicroBlaze Platform

MDM

DEBUGJTA

AXIInterconnect

Block

AXI-4AXI &&%2 Memory

1ontroller 32M x 16LPDDRSpartan-6

MCB

AXI-4

AXI-4

I-Cache

D-CacheAXI 4 Lit


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MicroBlazeD-LMB

AG

axi_uartlite

axi_gpio LEDs

USB-

UART

AXI-4-Lite

AXI-4-Lite

MCBD CacheAXI-4-Lite

BRAMI-LMB

AXI

InterconnectBlock

AXI-4


axi_timerAXI-4-Lite

Clock_generator

Proc_sys_reset

ResetSwitch

OSC @

66MHz

External Connectionaxi_intc

AXI-4-Lite

axi_gpio DIPSwitches

AXI-4-Lite

ExternalPort

axi_spi128MbFlash

AXI-4-Lite

Agenda





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Using SPI Flash


AXI is Part of AMBA:Advanced Microcontroller Bus Architecture

AXI Is. . . An interface and


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An interface andprotocol definition

Widely used industrystandard

AMBA

APB AHB . . .

A bus

The AXI specification describes an interface on a piece of IP.

It does not specify how systems of IP will be connected.

Performance

PLB is a Bus Spec / AXI is an Interface Spec

Processor

PLBC

AXI Sla0es

Interconnect

L$ared ,ccess !us

P-!AXI Masters


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Peri*5erals

,X+ ,X+

,X+

,X+

,X+ +nterconnect +P +mplementation is not

described in t$e spec

,X+

,X+

P-!

,X+ ,X+

Arbiter

,X+

everal companies build and

sell L,X+ interconnect +P Xilinx is building its own

,rrows indicate master*slave relations$ipK

not direction of dataflow

Master Slave

,X+

P-!

P-!

AXI is an interfacespecification, not abus specification

Goals of Transition to AXI

Higher performance

AXI allows systems to be optimized for highest Fmax, maximumthroughput, lower latency or some combination of those attributes. Thisfl ibilit bl t b ild th t ti i d d t f


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flexibility enables you to build the most optimized products for yourmarkets

Easier to use By consolidating a broad array of interfaces into AXI, you only need to

know one family of interfaces, regardless of whether they are, .

different domains, as well as developing your own IP

Enable ecosystem Partners are embracing the move to AXI: an open, widely adopted

interface standard. Many of them are already creating IP targeting AXIand other AMBA interfaces. This gives you a greater catalog of IP,ultimately leading to faster time to market

Previous MicroBlaze Design - Many interfaces

8xternal

Memory

8xternal

Memory

BRAMLMB

Xilinx Cache Link


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MicroBlaze

MPMC

Video

TEMAC

VFBC

Local Link

.imer.imer 7,M7,M =,7.=,7.

P-!'

P#+e!ridge

P-!'

P#+e!ridge

PLBv46

Custom IPNPI

P-! to +P+"

!ridge

P-! to +P+"

!ridge #ustom +P#ustom +P

IPIF

P#+eP#+eTRN

ar wareAccelerator

FSL

PLBv46 Single

Now -Standardize on AXI4

BRAMLMB

AXI4 8xternal

Memory

8xternal

Memory

AXI4 AXI MemoryController


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MicroBlaze

AXIInterconnect

AXI Video DMA

TEMAC

AXI4

AXI4

.imer.imer 7,M7,M =,7.=,7.

Custom IPAXI4

,X+ to +P+"

!ridge

,X+ to +P+"

!ridge #ustom +P#ustom +P

IPIF

HardwareAccelerator

AXI4-Stream

AXI Interconnect

AXI4-Lite AXI4-Lite AXI4-Lite AXI4-Lite

MicroBlaze Cache to External Memory DatapathDefault ,Configuration, same as pre-AXI

C_ICACHE_DATA_WIDTH = 0


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AXI

Instruction Cache

AXI432-bits

v8

Interconnect External

Memory

External Memory

64-bits

Data CacheAXI4

32-bits

C_DCACHE_DATA_WIDTH = 0

MicroBlaze Cache to External Memory DatapathHighest Performance, MicroBlaze port widths match AXI cache line width

C_ICACHE_DATA_WIDTH = 1


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MicroBlazeAXI AXI4 to

Instruction CacheAXI4

128 / 256 bits

v8n erconnec x erna

Memory

External Memory

64-bits

Data CacheAXI4

128 / 256 bits

C_DCACHE_DATA_WIDTH = 1

AXI Interconnect BlockConnects Multiple Master / Slave Pairs

AXI defines a point to point,master/slave interface

Up to 16 masters and 16 slavesper interconnect


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AXIPeri*5erals

,X+ ,X+

AXI Masters(MicroBlae)

master/slave interface

32 to 256 bit data widths perendpoint

AXIInterconnect

,X+ ,X+

,X+

,X+

,X+

,X+

,X+ ,X+

To use AXI Interconnect (and other embedded AXI IP) outside of XilinxPlatform Studio, consult Answer Record 37856

- , -protocol conversion

Each master / slave pair has ownclock domain

Pipeline registers per channel toboost timing

Plug and Play IP

AXI4

Achieved via adoption of industry standards


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IP Repository withcommon look & feel for

Support for AXI BFM forsimulation

AXI4

Standard Interconnect

IP Verification with AXI4 BFMwithin Xilinx Platform Studio

Standard Packaging Standard Security

Now Easier to Access, Integrate and Protect IP

Xilinx and partner IP (50 IP-XACT cores)

IP Packager available toAlliance Program Members

Fully functional

encryption flow forpartners (13.3)

Up to 20% higher system

bandwidth and up to 50%better area for the interconnectblock

AXI4 IP for 6 and 7 Series FPGAs

AXI4 - Advanced Extensible InterfaceStandard Overview

AXI4 Three flavors: AXI4, AXI4-Lite, AXI4-Stream


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All three share same terminology, signal naming,

AXI4 AXI4-Lite AXI4-Stream

high-performance register-style interfaces

**Burst based - only a start address required to initiate a transaction

Dedicated for

and memorymapped systems

(area efficientimplementation)

-based IP

Burst**(data beat)

up to 256 1 unlimited

Data Width 32 to 1024 bits 32 or 64 bits any number of bytes

Applications

(examples)Embedded, memory

Small footprint

control logic

DSP, video,

communication

Basic AXI Signaling - AXI-4

1. Read Address Channel

2. Read Data Channel

Five Channels


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2. Read Data Channel

3. Write Address Channel

4. Write Data Channel

5. Write Response Channel

Posted write model: there willalways be a Write

Response

The AXI Interface - AXI4

Also called: Full AXI

AXI Memory MappedAXI4 Read


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AXI Memory Mapped

Single address

Burst up to 256 data

beats

Data widths 32-1024bits wide

AXI4 Write

AXI Interface: Lite

No burst Data width 32 or AXI4-Lite Read


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64 only

Xilinx IP will onlysupport 32 bits

shim to connect

AXI4 master toAXI4-Lite slave

Reflect masters

transaction ID

AXI4-Lite Write

The AXI Interface - Streaming

No address channelAXI4-Streaming Transfer


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Not read and write,

always just masterto slave

Unlimited burstlength

AXI vs. PLB v46 Comparison: Three Back-to-BackPLB Transactions

Address 0 2


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Address

RDATA

0

0.1 0.2 0.3 0.4

2

2.0 2.1 2.2 2.3

1

PLBv46 has single address, separate data channels

WDATA 1.0 1.1 1.2 1.3

AXI Has Separate Read and Write AddressChannels

RADDR 0 1 2


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RDATA 0.1 0.2 0.3 0.4 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3

Read and write transactions can be initiated simultaneously

WADDR

WDATA

0

0.1 0.2 0.3 0.4

1

1.0 1.1 1.2 1.3

2

2.0 2.1 2.2 2.3

WRESP 0R 1R 2R


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Address Pipelining Helps AXI as Well

RADDR 0 1 2

Read and Write addresses can bewritten independently


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RDATA 0.1 0.2 0.3 0.4 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3

Separate address buses helps pipelining further

WDATA 0.1 0.2 0.3 0.4 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3

WRESP 0R 1R 2R

Add Overlapping Transactions for More Efficiencies

RADDR 0 1 2


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RDATA 0.1 0.2 0.3 0.4 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3

Write responses have own channel, thus

Masters, slaves, and interconnect keep track oftransactions using ID bits

WADDR

WDATA

0

0.1 0.2 0.3 0.4

1

1.0 1.1 1.2 1.3

2

2.0 2.1 2.2 2.3

WRESP 0R 1R 2R

can be completed independently

Other AXI Tricks for Even More Bandwidth

RADDR

0 1 2Read DataInterleaving


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RDATA 0.1 0.2 0.3 0.41.0 1.1 1.21.3 2.0 2.1 2.2 2.3

Interleaving

Interleaving and re-ordering minimizethe effects of slow slaves

RADDR

RDATA

0

0.1 0.2 0.3 0.4

1

1.0 1.1 1.2 1.3

2

2.22.0 2.1 2.3

Read Data

Reordering

MicroBlaze is Both EndianAXI:Little Endian, PLBv46 Big Endian

Little Endian means the little end (the least significant byte) of themultibyte word goes into memory first. First here means the lower

memory address. Big Endian is just the opposite.

Little Endian means the little end (the least significant byte) of themultibyte word goes into memory first. First here means the lower

memory address. Big Endian is just the opposite.


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MicroBlazewith

MicroBlaze

PLBv46

Endian Byte Ordering Example

Address 3 2 1 0

Low AddressHigh Address


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3 0

Little-endian (AXI) Byte 3 Byte 2 Byte 1 Byte 0

Big-endian (PLB) Byte 0 Byte 1 Byte 2 Byte 3

32-bit value in little-endian 32-bit value in big-endian

0x44332211 0x11223344

AXI PLB

Checkpoint!

List the various AXI-based system architectural models?

AXI4, AXI Lite, AXI Streaming

What are the five AXI channels?


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What are the five AXI channels?

Read address channel, Read data channel, Write address channel,Write data channel, Write response channel

What are the advantages of the AXI protocol over a shared bus

model??Flexibility Selectable interface type (Full, Lite, Streaming)

Performance No Arbitration, AXI peripherals do not share a bus

Performance AXI has separate Read and Write Channels

Performance AXI has configurable Interface widths up to 1024 bits wide

Summary

AXI is a signal interface protocol, not a bus

AXI has separate, independent read and write interfacesimplemented with channels

Each AXI channel supports a valid/ready acknowledgement


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handshake

AXI supports bursts and overlapped transactions The AXI4 interface offers improvements over AXI3 and defines

Full AXI memory mapped

AXI Lite

AXI Streaming

The definition of the AXI interconnect is independent of the AXIinterface protocol and determined by the system architecturedesign

Adding Custom IP via IPIC

IPIC IP Interface Controller

The IPIC is generated from a set of VHDL sources Master and slave attachments that have already been described

Read FIFO, write FIFO, and interrupt logic that provide additional


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p g pfunctions

The VHDL is parameterized via generics for conditional codegeneration and various bus widths and features

Numerous parameters

Complex VHDL environment; source code is supplied

More signals defined than you may need for your design

All of the above is abstracted away by the Create or

Import Wizard Reduces the time to configure the IPIC to minutes

Create or Import Wizard

The wizard helps you create your own peripheral and

then import it into your design

The wizard generates the necessary core descriptionfiles into the user-selected directory


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files into the user selected directory

You can start the wizard after creating a new projector opening an existing project in XPS

An existing peripheral can be imported directlythrough the wizard by skipping the creation option

Ensure that the peripheral complies with the Xilinximplementation of the IBM CoreConnect bus architecturestandard

Used when updating peripherals from earlier tool versions



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Two wizards in one, lets look at the Create IPICTemplate Wizard



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Select to add to existingproject or centralized

repository

Enter peripheral name,version information, and

brief description to beused by XPS tools


Select betweenAXI , PLB v46,or Fast SimplexLink (FSL)


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Link (FSL)

related

attachmentspecifications


Select whichoptional servicesto include intoperipheral


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peripheral


This choice is notseen for the AXI Litesingle data phaseIPIC


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IPIC

Enable FIFO services


Select numberof registerenables toprovide


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provide


Select numberof addressranges toprovide


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provide



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Displays which IPICsignals will be providedto the backend user logic

Option to auto-generate aBFM simulation environment

Requires a separate tool

license



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All done!Additional options for developmentenvironment, driver template

generation, and language options Select here forVerilogHDL Templatefor User_logic

IPIC Connections

HDL files created by Wizard

.vhd is wrapper file containing IPIC and User Logic IPIC abstracts AXI to Bus2IP protocol

Requires editing when exporting external ports

User_logic.vhd is where custom HDL code goes


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_ g g

MicroBlazeCore

AXI-4Lite AXI LITE

IPIC(IP Interface)

User LogicBus2IP

ConnectionsBus2IP

Outputs

AXI

InterconnectBlock

AXI-4

Inside user_logic.vhd

Entity statement

Add custom port signals Add custom generics and parameters

Instantiate the rest of the design as a component


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Review the sample code provided for each option Registers implemented for Bus2IP_WrCE and

us _ se ec s

Block RAM memory implemented for Bus2IP_CS

Example code to generate interrupts

Example code to transfer data between read/write FIFO

Modify/delete code to accommodate your application

Only the needed IPIC signals will appear inuser_logic.v

Summary

The IPIC attachments make it a simple task to interface to the

AXI interconnect Complex IPIC services are configurable via parameters and

VHDL generics

The Create or Import Wizard makes it a simple task to configure


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p p g

and create a specific instance of an IPIF attachment IPIC attachments are supplied as separate master and slave

IPIC slave services

Single and burst data phase Address range (CS) and single address (CE) decodes

Burst read FIFO

Reset and MIR register

Data phase timeout timer

Agenda


Xilinx MicroBlaze Architecture Overview Creating an Embedded Design




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Using SPI Flash Lab 6 SPI Programming

Lab 3: Adding Custom IP

Introduction

This tutorial demonstrates how to create and add custom IP toan existing MicroBlaze system using the Xilinx Platform Studio(XPS) Create/Import Peripheral Wizard. The system from theprevious tutorial will be used as the starting point


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Objectives

ow o crea e a cus om us ng e w zar

How to customize the peripheral

How to add the IP core to the project

How to write code for the new IP

Lab #3 - MicroBlaze Platform Adding Custom IP

MDMDEBUG

JTAG

AXI

InterconnectBlock



axi_uartliteUSB-UART

AXI-4-Lite

Spartan-6MCB

AXI-4

AXI-4

I-Cache

D-CacheAXI-4-Lite


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MicroBlazeD-LMB

_

LEDs

UART

AXI-4-Lite axi_gpioaxi_pwm

BRAMI-LMB

AXI

Interconnect

Block

AXI-4


axi_timerAXI-4-Lite

Clock_generator

Proc_sys_reset

ResetSwitch

OSC @66MHz


AXI-4-Lite


AXI-4-Lite

ExternalPort

axi_spi128MbFlash

AXI-4-Lite

IPIC Connections

HDL files created by IPIF

MicroBlazePWM_Out

Add this port


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Core

AXI-4L

ite AXI Lite

Connections AXI LITE

IPIC(IP Interface) User Logic

axi_pwm.vhd

user_logic.vhd

Bus2IPConnections

Bus2IP

PWM_Out

Agenda






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p g g








Simulating an Embedded System

Your FAEs favorite question???

Did you simulate your design first?


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Simulation can be usedto validate:

IP connectivity

IP functionality AXI Bus transactions

Software execution

ISim Powerful Mixed-Language HDL Simulator

Strong compliance to standards

VHDL (IEEE 1076-1993) Verilog (IEEE 1364-2001) Mixed VHDL/Verilog simulation

SDF, Tcl, VCD, SAIF

Tight integration


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Supports all Xilinx devices inluding allHard IP blocks

, , ys en

High productivity

HDL source code debugging

Multiple waveform windows

Searching, filtering, cross-probing

Automatic memory elements detection for editing Recompile and re-launch simulation

Accessing ISim

EDKEmbeddedEdition

DSPEdition

SystemEdition


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EDK

SystemGeneratorISE

WebPack

LogicEdition SystemGenerator

LogicEdition

ISE FoundationISim Lite

PlanAhead

Limited Devices

LogicEdition

LogicEdition

ChipScopePROSerial I/O Toolkit

PlanAhead

ISE FoundationISim Full

Setting up Simulation Environment

All simulation preferences

set in ISE Project Navigator

Select Preferred


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Simulator, available: ISIM

Modelsim

Questa

For Aldec, see:http://support.aldec.com/SupportArchive/

PDFs/000820_SimulatingXilinxEDK

MicroBlazedesigninActive-HDL.pdf

Creating a Stimulus File

First step is to create a

stimulus file Text Fixture (Verilog)

Test Bench (VHDL)


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Project Navigator willautomatically create atemplate

Modifying the Stimulus File

MicroBlaze designs only require

two inputs Do you rememberwhat they are?

Reset

Clock

In ProjNav, switchView to Simulation


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Other stimulusnc u es a sys eminputs

Templates available forcreating stimulus

Adding Software Application for Simulation

ELF files provide

embedded code forsimulation

ELF file must be built inSDK and mapped to


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BRAMs

WorkSpace directory

Add ELF File to project

Setting ELF File Associations

Associations must be

set for simulation Can be associated with

simulation and implementation

Simulation uses ELF to


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execute code in MicroBlaze

Im lementation embedsELF file into Bitstream

Must checkUse With box

Simgen Simulation Model Generator

Creates structural simulation

models used to simulateembedded systems


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Inputs MHS and ELF filesto create model ofem e e sys em

Invoking SimGen Launching ISim

Select Testbench

Run SimulateBehavioral Model


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Simgen is called

Agenda





L b 2 Addi EDK IP


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Embedded Simulation





Lab 4: Embedded System Simulation

Introduction

This tutorial demonstrates how to simulate the embeddedsystem using ISim

Objectives

H t t th i l ti ti


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How to setup the simulation properties How to add a VHDL testbench

How to simulate a cycle accurate MicroBlaze design

How to view MicroBlaze specific signals and AXI bus transactions

Lab #4 - MicroBlaze Platform - Simulation

MDM

DEBUGJ

TAG

AXI

InterconnectBlock



axi_uartliteUSB-UART

AXI-4-Lite

Spartan-6MCB

AXI-4

AXI-4

I-Cache

D-CacheAXI-4-Lite


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MicroBlazeD-LMB

axi_pwm LEDsAXI-4-Lite

BRAMI-LMB

AXI

Interconnect

Block

AXI-4


axi_timerAXI-4-Lite

Clock_generator

Proc_sys_reset

ResetSwitch

OSC @66MHz


AXI-4-Lite


AXI

Documents

3 Edk Intro Mb Speedway 131