3K4Micro Spec

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Hard disk drive specifications

Hitachi Microdrivewith CF+ Type II interface

Models4GB 3K4-4 HMS360404D5CF002GB 3K4-2 HMS360402D5CF00

Revision 0.4 17 Oct. 2003

Hitachi Global Storage Technologies storage products


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S14R-8897-04 Publication #E001



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Hard disk drive specifications

Hitachi Microdrivewith CF+ Type II interface

Models4GB 3K4-4 HMS360404D5CF002GB 3K4-2 HMS360402D5CF00

Revision 0.4 17 Oct, 2003

S14R-8897-04 Publication #E001



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1st Revision (Rev 0.1) Sxxx-xxxx-xx (Jul. 14, 2003) Preliminary2nd Revision (Rev 0.2) Sxxx-xxxx-xx (Aug. 20, 2003) Preliminary

- Power / zone format3rd Revision (Rev 0.3) Sxxx-xxxx-xx (Oct. 10, 2003) Preliminary

- Peak power / power rising time4th Revision (Rev 0.4) S14R-8897-04 (Oct. 17, 2003)

The following paragraph does not apply to the United Kingdom or any country where such provisions

are inconsistent with local law: HITACHI GLOBAL STORAGE TECHINOLOGIES PROVIDES THISPUBLICATION "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, IN-CLUDING,BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FIT-

NESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer or express or implied warrantiesin certain transactions, therefore, this statement may not apply to you.

This publication could include technical inaccuracies or typographical errors. Changes are periodically made totheinformation herein; these changes will be incorporated in new editions of the publication. HGST may makeimprovements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

It is possible that this publication may contain reference to, or information about, HGST products (machinesand programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that HGST intends to announce such HGST products, programming,or services in your country.

Technical information about this product is available by contacting a local HGST representative or

http://www.hgst.com

HGST may have patents or pending patent applications covering subject matter in this document. Thefurnishing of this document does not give you any license to these patents.

(C) Copyright Hitachi Global Storage Technologies

Note to U.S. Government Users Documentation related to restricted rights Use, duplication or disclosureis subject to restrictions set forth in GSA ADP Schedule Contract with HGST.



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Table of contents

327.5 Mechanical specifications ................................... .......317.4.2 Nonrecoverable errors ................................ .......317.4.1 Recoverable errors ................................... .......317.4 Error rates .............................................. .......307.3.4 Preventive maintenance ............................... .......307.3.3 Life .............................................. .......307.3.2 Warranty .......................................... .......307.3.1 Load/unload cycles ................................... .......307.3 Reliability ............................................... .......307.2 DC power requirements .................................... .......297.1.3 Magnetic fields ...................................... .......297.1.2 Conductive noise .................................... ....... 29

7.1.1 Radiation noise ..................................... .......

287.1.1 Temperature and humidity ............................. .......287.1 Environment ............................................ .......287.0 Specification ........................................... .......266.0 File organization ........................................ .......255.7.3 Recovered read errors ................................ .......255.7.2 Nonrecovered read errors ............................. .......255.7.1 Nonrecovered write errors .............................. .......255.7 Automatic reallocation ..................................... .......255.6 Error recovery ........................................... .......245.5 Data buffer test .......................................... .......245.4 WRITE safety ........................................... .......245.3 Equipment status ......................................... .......245.2 Write cache ............................................. .......245.1 Data loss at power off ...................................... .......245.0 Data integrity ........................................... .......234.3.3 Operating modes .................................... .......214.3.2 Mechanical positioning ................................ .......214.3.1 Command overhead .................................. .......214.3 Performance characteristics ................................. .......204.2 Data sheet ............................................. .......204.1 Formatted capacity ....................................... .......204.0 Fixed disk characteristics ................................. .......183.2 Head disk assembly ....................................... .......183.1 Control electronics ........................................ .......183.0 Fixed disk subsystem description .......................... .......16Part 1. Functional specification ................................ .......142.0 General features ........................................ .......131.3 Drive handling precautions .................................. .......121.2 Abbreviations ........................................... .......121.1 References ............................................. .......121.0 General ............................................... ....... 10List of figures ............................................. .......



7/1575711.2 Card configuration registers ................................ ....... 5511.1 PCMCIA memory spaces and configuration registers ............. .......

5511 System interface ......................................... .......5410 Deviations from Standard ................................. .......539.1 Introduction ............................................. .......539 General ................................................. .......52Part 2. Interface specification ................................. .......508.14 Power on/off timing ...................................... .......498.13 True IDE Mode Ultra DMA Data Transfer Timing ................. .......488.12 True IDE Mode Multiword DMA Data Transfer Timing ............. .......478.11 True IDE Mode I/O Input (Read) Timing ....................... .......468.10 I/O Input (Write) timing .................................... .......458.9 I/O Input (Read) timing .................................... .......448.8 Attribute and Common Memory Read timing ..................... .......438.7 Common Memory Read timing ............................... .......428.6 Attribute Memory Read timing ............................... .......418.5 Interface logic signal levels ................................. .......408.4 Signal description ........................................ .......408.3 Signal definition ......................................... .......408.2 Interface connector ....................................... .......408.1 Cabling ................................................ .......408.0 Electrical interface specifications ........................... ....... 37

7.11 Packaging ............................................. .......

377.10.8 Secondary circuit protection ........................... .......377.10.7 Environment ....................................... .......377.10.6 Safe handling ...................................... .......377.10.5 Flammability ....................................... .......377.10.4 German Safety Mark ................................. .......377.10.3 IEC compliance .................................... .......367.10.2 Canadian Standards Authority (CSA) approval .............. .......367.10.1 Underwriters Lab (UL) approval ......................... .......367.10 Safety ................................................ .......367.9.2 C-Tick Mark ........................................ .......367.9.1 CE Mark ........................................... .......367.9 Electromagnetic compatibility ................................ .......367.8 Identification labels ........................................ .......357.7.2 Discrete tone penalty ................................. .......347.7.1 Sound power level ................................... .......347.7 Acoustics ............................................... .......347.6.4 Nonoperating shock .................................. .......347.6.3 Operating shock ..................................... .......347.6.2 Nonoperating vibration ................................ .......337.6.1 Operating vibration ................................... .......337.6 Vibration and shock ....................................... .......

337.5.5 Load/Unload mechanism .............................. .......337.5.4 Mounting orientation .................................. .......337.5.3 Connector ......................................... .......327.5.2 Mechanical dimensions ............................... .......327.5.1 Physical dimensions and weight ......................... .......



8/1578112.9 Reassign Function ....................................... .......8012.8 Write Cache Function ..................................... .......7912.7 Seek Overlap .......................................... .......7812.6.4 Transition Time ..................................... .......7812.6.3 Low Power Idle mode ................................ .......7712.6.2Active Idle mode ..................................... .......7712.6.1 Performance Idle mode ............................... .......7712.6 Advanced Power Management (Adaptive Battery Life Extender 3)Feature ................................................... .......

7612.5.7 Initial Power Mode at Power On ......................... .......7612.5.6 Interface Capability for Power Modes ..................... .......7612.5.5 Status ............................................ .......7612.5.4 Standby timer ...................................... .......7512.5.3 STANDBY command completion timing ................... .......7512.5.2 Power Management Commands ........................ .......7512.5.1 Power Mode ....................................... .......7512.5 Power Management Feature ................................ .......7412.4.2 LBA Addressing Mode ................................ .......7412.4.1 Logical CHS Addressing Mode .......................... .......7412.4 Sector Addressing Mode .................................. .......7212.3.3 Required power-off sequence .......................... .......7212.3.2 Emergency unload .................................. .......7212.3.1 Load/Unload ....................................... ....... 72

12.3 Power-off considerations .................................. .......

7112.2 Diagnostic and Reset considerations .......................... .......7012.1.1 Register Initialization ................................. .......6912.1 Reset Response ........................................ .......6811.4.13 Status Register .................................... .......6711.4.12 Sector Number Register ............................. .......6711.4.11 Sector Count Register ............................... .......6711.4.10 Feature Register ................................... .......6611.4.9 Error Register ...................................... .......6611.4.8 Device/Head Register ................................ .......6511.4.7 Drive Address Register ............................... .......6511.4.6 Device Control Register .............................. .......6411.4.5 Data Register ...................................... .......6411.4.4 Cylinder Low Register ................................ .......6411.4.3 Cylinder High Register ............................... .......6411.4.2 Command Register .................................. .......6411.4.1 Alternate Status Register .............................. .......6411.4 CF-ATA Registers ....................................... .......6311.3.4 True IDE Mode addressing ............................ .......6211.3.3 Memory mapped addressing ........................... .......6111.3.2 Contiguous I/O mapped addressing ...................... .......6011.3.1 Primary or Secondary I/O mapped addressing .............. .......

6011.3 CF-ATA Drive Register Set Definition and Protocol ............... .......5911.2.4 Socket and Copy Register (Offset 06h) .................... .......5911.2.3 Pin Replacement Register (Offset 04h) .................... .......5811.2.2 Card Configuration Status Register (Offset 02h) ............. .......5711.2.1 Configuration Option Register (Offset 00h) ................. .......



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14613.6 Card information structure ................................. ......14513.5 Error Posting ........................................... ......14413.4.37 Write Verify (3Ch: Vendor Specific) ..................... ......14313.4.36 Write Sector(s) without Erase (38h) ..................... ......14113.4.35 Write Sector(s) (30h/31h) ............................. ......14013.4.34 Write Multiple without Erase (CDh) ...................... ......13813.4.33 Write Multiple (C5h) ................................. ......13613.4.32 Write Long (32h/33h) ................................ ......13413.4.31 Write DMA (CAh/CBh) ............................... ......13313.4.30 Write Buffer (E8h) .................................. ......13213.4.29 Wear Level (F5h) .................................. ......13113.4.28 Translate Sector (87h) .............................. ......13013.4.27 Standby Immediate (E0h/94h) ......................... ......12913.4.26Standby (E2h/96h) .................................. ......12813.4.25 Sleep (E6h/99h) ................................... ......12713.4.24 Set Multiple (C6h) .................................. ......12513.4.23 Set Features (EFh) ................................. ......12413.4.22 Sense Condition (F0h : vendor specific) .................. ......12313.4.21 Seek (7Xh) ....................................... ...... 122

13.4.20 Security Erase Prepare (F3h) .......................... ......

12013.4.19 Request Sense (03h) ............................... ......11913.4.18 Recalibrate (1Xh) .................................. ......11713.4.17 Read Verify (40h/41h) ............................... ......11513.4.16 Read Sector(s) (20h/21h) ............................. ......11313.4.15 Read Multiple (C4h) ................................. ......11113.4.14 Read Long (22h/23h) ................................ ......10913.4.13 Read DMA(C8h/C9h) ................................ ......10813.4.12 Read Buffer (E4h) .................................. ......10713.4.11 Initialize Device Parameters (91h) ...................... ......10613.4.10 Idle Immediate (E1h/95h) ............................. ......10513.4.9 Idle (E3h/97h) ...................................... ......9913.4.8Identify Device (ECh) ................................. .......9813.4.7Format Unit (F7h: Vendor Specific) ....................... .......9513.4.6 Format Track (50h: Vendor Specific) ..................... .......9413.4.5 Flush Cache (E7h) .................................. .......9313.4.4 Erase Sectors (C0h) ................................. .......9213.4.3 Execute Device Diagnostics (90h) ....................... .......9113.4.2 Check Power Mode (E5h/98h) .......................... .......8813.4.1 Access Metadata Storage - B8h ......................... .......8713.4 DMA Data Transfer Commands ............................. .......8613.3 Non-Data Commands ..................................... .......

8513.2 Data Out Commands ..................................... .......8313.1 Data In Commands ...................................... .......8212.10.1 Meatadata Storage Command Set ...................... .......8212.10 Metadata Storage Function ................................ .......8112.9.1 Auto Reassign Function ............................... .......



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List of figures

51Figure 35. Power On/Off timing diagram ........................... .......50Figure 34. Power On/Off timing data .............................. .......49Figure 33. Ultra DMA data transfer timing data ...................... .......48Figure 32. Multiword DMA data transfer timing data ................... .......47Figure 31. True IDE Mode IO Input (Read) timing diagram .............. .......47Figure 30. True IDE Mode IO Input (Read) timing data ................. .......46Figure 29. I/O Write timing diagram ............................... .......46Figure 28. I/O Write timing data ................................. .......45Figure 27. Common Memory Read Timing diagram ................... .......45Figure 26. Common Memory Read Timing data ...................... .......44Figure 25. Attribute and Common Memory Read timing ................ .......44Figure 24. Attribute and Common Memory Read timing data ............ .......43Figure 23. Common Memory Read timing .......................... .......

42Figure 22. Attribute Memory Read timing diagram .................... .......42Figure 21. Attribute Memory Read timing data ....................... .......41Figure 20. Interface logic signal levels. ............................ .......40Figure 19. DC characteristics ................................... .......35Figure 18. Sound power levels .................................. .......34Figure 17. Random vibration PSD profile breakpoints (nonoperating) ...... .......33Figure 16. Random vibration ................................... .......32Figure 15. Mechanical outline of the drive .......................... .......32Figure 14. Physical dimensions and weight ......................... .......30Figure 13. DC power requirements. .............................. ....... 29

Figure 12. Radiation noise ..................................... .......28Figure 11. Temperature and humidity specifications ................... .......26Figure 10. Cylinder allocation ................................... .......23Figure 9. Operating modes .................................... .......23Figure 8. Drive Ready Time ................................... .......22Figure 7. Latency Time ....................................... .......22Figure 6. Single track seek time ................................ .......22Figure 5. Full stroke seek time ................................. .......21Figure 4. Mechanical positioning performance ...................... .......21Figure 3. Performance parameters .............................. .......20Figure 2. Data sheet ........................................ .......20Figure 1. Formatted capacity .................................. .......



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1.0 GeneralThis document describes the characteristics of 1.0-type 3600-RPM hard disk drive with a CF+ Type IIinterface and with capacities of 4 GB and 2 GB. This drive is the HGST Microdrive and is hereafter referred to as "the drive". This document defines the hardware functional and interface specifications.The drive is available in the following models:

4GB 3K4-4 HMS360404D5CF00 2GB 3K4-2 HMS360402D5CF00

The major difference among 3K4-4 and 3K4-2 is the number of heads.

The specifications are subject to change without notice.

1.1 ReferencesCompact Flash Specification Version 1.4

1.2 Abbreviations

to be definedTBD

Machine Level ControlMLC

3K4-4/3K4-2Hitachi Microdrive

3K4-4/3K4-2drive

1,000,000 bits per square millimeter Mb/sq-mm

128 x 1 024 bytes128 KB

1,000,000,000 bytesGB

1,000,000 bytesMB

1,024 bytesKB

1,000,000 bits per secondMbps

1,000 bits per millimeter Kbit/mm



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1.3 Drive handling precautionsThe drive can be easily damaged by shocks or Electric Static Discharge (ESD). Any damageincurred by the drive after removal of it from the shipping package and opening of the ESDprotective bag is the users responsibility.

Do not apply pressing force onto the top or bottom surface of the drive.

DO NOT PRESS!

DO NOT PRESS WHEN REMOVING THEDRIVEDO NOT PRESS WHEN CARRYING THEDRIVEDO NOT APPLY PRESSURE WHENATTACHING THE DRIVE

Do not seal the breather hole on the top cover.

DO NOT SEAL THIS HOLE!

SEALING THIS HOLE WILL RESULT IN LOSS OF DATA



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2.0 General featuresw Compact Flash Type-2 Card Compliance.

w 4.0GB and 2.0GB formatted capacity

w 512 bytes/sector

w CF + Interface

w Integrated controller

w No-ID recording format

w ME2PR 120/126 coding

w Multi zone recording

w Enhanced ECC On-The-Fly

42.5 bytes Reed Solomon Code

20 byte On-The-Fly correctionw 128kB cache (total buffer 320kB , upper 192KB is used for firmware )

w Fast data transfer rate

- Up to 16.7MB/sec at PIO mode 4

- Up to 16.7MB/sec at Multiword DMA mode 2 (True IDE Mode only)

- Up to 33 MB/sec at Ultra DMA mode 2 (True IDE Mode only)w Media data transfer rate 98 (outer zone / typical) - 57 (inner zone) Mbits/sec

w Average seek time 12 msec for readw Closed -loop actuator servo (Embedded Sector Servo)

w True Track servo

w Rotary voice coil motor actuator

w Load/Unload mechanism

w Mechanical latch

w Adaptive power save control

w

1.0 sec Power on to readyw Shock

Non-operation : 19600 m/s2 / 1 ms (2000 G/1 ms)

Operation : 1960 m/s2 / 2 ms (200 G/2 ms)



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Part 1. Functional specification



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3.0 Fixed disk subsystem description

3.1 Control electronicsThe control electronics works with the following function:

Compact Flash Card Interface Protocol

Embedded Sector Servo

No-ID(TM) format

Multi zone recording

ME2PR 120/126 Code

ECC On-The-Fly

Enhanced Adaptive Battery Life Extender

3.2 Head disk assemblyThe following technologies are used in the drive:

Femto slider

Smooth glass disk

GMR head

Integrated Lead Suspension (ILS)

Load/Unload mechanism

Mechanical latchFrame bumper



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4.0 Fixed disk characteristics

4.1 Formatted capacityThe defaults of the logical drive parameters in Identify Device Data are as follows:

2,047,868,9284,095,737,856Total Logical Data Bytes3,999,7447,999,488Number of Sectors

39687936Number of Cylinders6363Number of Sectors/Track1616Number of Heads

Logical Layout

36003600RPM11Number of Disks12Number of Heads

160266160266Sectors per Track512512Bytes per Sector

Physical Layout3K4-23K4-4Description

Figure 1. Formatted capacity

4.2 Data sheet

16Data Bands87.6 (Max)Areal Density (Mbit/sq-mm)

3.54Track Density (ktrack/mm)

24.7 (Max)Recording Density (kbit/mm)

16.7 MB/sec (PIO mode4)16.7 MB/sec

(Multiword DMA mode2 at TRUE IDE)33MB/sec

(Ultra DMA at TRUE IDE )

Data transfer rates (host to/from buffer)

57.197.9 Mb/sData transfer rates (buffer to/from media)3600Rotational Speed (RPM)

Figure 2. Data sheet



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4.3 Performance characteristicsDrive performance is determined by the following parameters:

Command overheadMechanical positioning- Seek time- LatencyData transfer speedBuffering operation (Look ahead/Write cache)

Note: All the above parameters contribute to drive performance. Other parameters also contribute tothe performance of the actual system. This specification describes only the characteristics of thedrive, not the system throughput which depends on the system and the application.

The following table gives a typical value of each parameter. Detailed descriptions follow in the nextsections.

Refer to CFA Spec.Disk-host data transfer 57.197.9 Mbit/sDisk-buffer data transfer

1 msCommand Overhead1.0 secPower On To Ready

3600 RPMRotational speed13 msAverage Random Seek Time for Write12 msAverage Random Seek Time for Read

TypicalFunction

Figure 3. Performance parameters

4.3.1 Command overheadCommand overhead time is defined as the total time from the receipt of the command by the drive tothe start of motion of the actuator.

4.3.2 Mechanical positioning

4.3.2.1 Average Seek Time (Including Settling)

1513Write1412Read

Max (ms)Typical (ms)Command Type

Figure 4. Mechanical positioning performance

Headings " Typical " and " Max " are given throughout the performance specification. Typical meansthe average of the drive population tested at nominal environmental and voltage conditions. Maxmeans the maximum value measured on any one drive over the full range of the environmental andvoltage conditions. (See section Environment Also see Section, DC Power Requirements .)

The seek time is period of time from the start of the motion of the actuator to the start of a reliableread or write operation. A reliable read or write implies that error correction/recovery is not employedto correct arrival problems. The Average Seek Time is a measure of the weighted average of allpossible seek combinations.

maxSUM (max + 1 n) (Tn in + Tn out )



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n=1Weighted Average = --------------------------------------------------

(max + 1) (max)

Where: max = Maximum Seek Length

n = Seek Length ( 1 to max )Tn in = Inward measured seek time for an n track seekTn out = Outward measured seek time for an n track seek

4.3.2.2 Full Stroke Seek Time

25.021.0Write24.020.0Read

Maximum (ms)Typical (ms)Function

Figure 5. Full stroke seek time

Full stroke seek is measured as the average of 1000 full stroke seeks.

4.3.2.3 Single Track Seek Time (without Command Overhead, includingsettling)

3.01.0Write2.01.0Read

Maximum (ms)Typical (ms)Function

Figure 6. Single track seek time

Single track seek time is an average. The single track seek time is calculated by adding the time of inward and outward seek time of each single track and dividing that sum by the total number of tracks.

4.3.2.4 Average latency

8.316.73600

Average latency(ms)

Time for a revolution(ms)

Rotation speed(RPM)

Figure 7. Latency Time



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4.3.2.5 Drive Ready Time/Mode Transition Time

0.70.5Stand by to Idle0.70.5Power on to Stand by

Maximum (sec)Typical (sec)Condition

Figure 8 . Drive Ready Time

4.3.3 Operating modes

Same as StandbySleep

The drive interface is capable of accepting commands. Spindle motor isstopped. All circuitry except the host interface is in power saving mode.The execution of commands is delayed until spindle becomes ready.

Standby

Spindle motor is rotating normally with actuator unloaded to theparking positions.Low power idle

The device is capable of responding immediately to media accessrequests.Some circuitry including servo system and R/W electronicsis in power saving mode. The head is parked near the mid-diameter

the disk without servoing.

Active idle

The drive is capable of responding immediately to media accessrequests. All electronic components remain powered and full frequencyservo remains operational.

Performance Idle

Read operation modeRead

Write operation modeWrite

Seek operation modeSeek

Start up time period from spindle stop or power downSpin-up

DescriptionOperating mode

Figure 9. Operating modes

4.3.3.1 Operating mode at power onThe drive powers up in Standby mode.

4.3.3.2 Adaptive Power Save Control

The transition timing from Performance Idle to Standby depends on both the access pattern of thehost system and the setting of the advanced power management level. With the power-on default,the transition timing for each power mode is under control of Adaptive Battery Life Extender algorithm.



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5.0 Data integrity

5.1 Data loss at power off Power off during any operations except for write operation will not cause any data loss.

Power off during a write operation causes the loss of data received by the drive but not yet writtenonto the disk media.

There is a possibility that power off during a write operation might make a maximum of 1 sector of data unreadable. This state can be recovered by a rewrite operation.

5.2 Write cacheWhen write cache is enabled, there is a possibility that the write command completes before theactual disk write operation finishes. This means that there is a possibility that a power off eventmay occur even after a full write command finishes. This means that it is possible that even after a write command completion a power off might cause the loss of the data which the drive hasreceived but not yet written onto the disk.

In order to prevent data loss, confirm the completion of the actual write operation prior to thepower off by issuing the Standby Immediate or Sleep command and confirming its completion.

The default state of the write cache at power-on is "OFF."

5.3 Equipment statusEquipment status is available to the host system any time the drive is not ready to read, write, or seek. This status normally exists at power-on time and will be maintained until the following conditions

are satisfied:Access recalibration/tuning is complete.Spindle speed meets requirements for reliable operation.Self-check of drive is complete.

Appropriate error status is made available to the host system if either of the following conditions occur after the drive has once become ready:

Spindle speed outside requirements for reliable operation.Occurrence of a Write Fault condition.

5.4 WRITE safety

The drive ensures that the data is written onto the disk media properly. The following conditions aremonitored during a write operation. When one of those conditions exceeds the criteria, the writeoperation is terminated and automatic retry sequence will be invoked.

Head off trackExternal shockLow supply voltageSpindle speed toleranceHead open/short

5.5 Data buffer testThe data buffer is tested at Power-on-reset. The test consists of a write/read "00"x and "ff"x pattern oneach buffer position.



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5.6 Error recoveryErrors occurring on the drive are handled by the error recovery procedure.

Errors that are uncorrectable after application of the error recovery procedures are reported to thehost system as nonrecoverable errors.

5.7 Automatic reallocationThe sectors those show some errors may be reallocated automatically when specific conditions aremet. The drive does not report automatic reallocation to the host system. The conditions for automaticreallocation are described below.

5.7.1 Nonrecovered write errorsWhen a write operation cannot be completed after the Error Recovery Procedure (ERP) is fullycarried out, the sector(s) are reallocated to the spare location. An error is reported to the host systemonly when the write cache is disabled and the auto reallocation has failed.

5.7.2 Nonrecovered read errors When a read operation has failed after defined ERP is fully carried out, a hard error is reported to thehost system. This location is registered internally as a candidate for the reallocation. When aregistered location is specified as a target of a write operation, a sequence of media verification isperformed automatically. When the result of this verification meets the criteria, this sector isreallocated.

5.7.3 Recovered read errors When a read operation for a sector fails once and is then recovered at the specific ERP step, thissector is reallocated automatically. A media verification sequence may be run prior to the reallocationaccording to the predefined conditions.



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6.0 File organizationThe following figure shows the cylinder allocation for the drive.

16017920 -1516016384 - 179191416014848 - 163831316013696 - 14847121801280013695111921139212799102009728113919213844897278224755284477224652875516240550465275240448055034240332844793256192033272266102419191266010230 Sectors per TrackCylinder Zone

Figure 10 . Cylinder allocation



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7.0 Specification

7.1 Environment

7.1.1 Temperature and humidity

300 to 12,192 mAltitude

5C/MinutesMaximum temperature gradient

40C, non condensingMaximum wet bulb temperature

595%, non condensingRelative humidity

40 to 70C (See note)Temperature

Nonoperating conditions

300 to 3048 mAltitude

5C/MinutesMaximum temperature gradient

29.4C non condensingMaximum wet bulb temperature

890%, non condensingRelative humidity

070C (See Note)Temperature

Operating conditions

Note: Regardless of the ambient temperature, the drive can be operated at a maximum temperatureof 70C at the center of the base spindle of the drive.

Figure 11. Temperature and humidity specifications

Maximum storage period with shipping package is one year.

7.1.1.1 Corrosion test

The hard disk drive must be functional and show no signs of corrosion after being subjected totemperatures of 50C with 90% relative humidity for one week of storage followed by a return to 25Cwith 40% relative humidity in two hours.



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7.1.1 Radiation noiseThe disk drive must work without degradation of the soft error rate under the following magnetic fluxdensity limit at the enclosure surface.

5020140010010120025061100500060 Limits ( T RMS)Frequency

Figure 12. Radiation noise

7.1.2 Conductive noiseThe disk drive shall work without degradation of the soft error rate with an AC current of up to 45mA(p-p) in the frequency range from DC to 20 MHz, injected through any two of the mounting screw

holes of the drive via a 50-Ohm resistor.

7.1.3 Magnetic fieldsThe disk drive must withstand the radiation and conductive noise limits shown above. The testmethod is devined in the document "Noise Susceptibility Method" specification (P/N 95F3944).



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7.2 DC power requirementsConnection to the drive should be made in a safety extra low voltage (SELV) circuit.

6385 mA363 mAPeak (maximum RMS in0.5 ms windows)

18 mA16 mAStandby5230 mA265 mASeek average4314 mA305 mAWrite4315 mA303 mARead

72 mA67 mALow power idle average375 mA70 mAActive idle average

3230 mA225 mAPerformance idleaverage

Population meanPopulation meanSupply current (nominalcondition)

25%5%Tolerance

1100 mV p-p max.70 mV p-p max.Power supply ripple(0-20Mhz)

+5 Volt+3.3 VoltsNominal supply

Notes+5V power supply case+3.3V power supply casePower supply

Notes1. The maximum fixed disk ripple is measured at 3.3 / 5 V input of the drive.2. The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of

20 ms) on the 3.3 / 5 Volt nominal supply.3. The idle current is specified at an inner track.4. The read/write current is specified at 100%duty.5. The seek average current is specified based on three operations per 100 ms.6. The worst case operating current at unloading.

Figure 13. DC power requirements.

7.3 Reliability

7.3.1 Load/unload cyclesThe drive will meet the specified error rates after the following Load/Unload cycles:

300,000 cycles (Load/Unload to be controlled by the drive microcode)20,000 cycles (Emergency unloads)

7.3.2 WarrantyThe warranty will be covered by contracts.

7.3.3 LifeTo be discussed separately.

7.3.4 Preventive maintenanceNone required.



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7.4 Error ratesError rates fall into two categories:

Recoverable errorsNonrecoverable errors

The following error rates assume that no attempts are made to read or write in areas alreadyidentified as being defective. The error rates are defined for the drive operating at the full range of environmental conditions and are shown in section Environment. The voltage limits are shown insection DC Power Requirements.

7.4.1 Recoverable errorsA recoverable error is defined as an operation that failed the first time but succeeded in recoveringthe error when the drive error recovery procedure was invoked. ECC On-The-Fly, which is alwaysactive, is transparent to the system and is not counted as a recoverable error.

A typical drive shall have no more than one recoverable error per 100 million bits transferred (1 in 10 8)when operated at nominal voltage and environmental condition. The typical disk drive error raterepresents the geometric mean of the error rates of the total disk drive population. The size of thedrive population is 50 drives or more.

Each drive in the population shall have no more than one recoverable error per 10 million bitstransferred (1 in 10 7) when operated at full range of voltage and environmental conditions and theoperating vibration levels stated in, Vibration and Shock on page 0.

7.4.2 Nonrecoverable errorsA nonrecoverable error is defined as an operation that failed and was not recovered by the fixed diskerror recovery procedure. No drive has more than one nonrecoverable error per 10 trillion bits

transferred (1 in 1013

) when operated at the full range of voltage and environmental conditions.



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7.5 Mechanical specifications

7.5.1 Physical dimensions and weightThe following table lists the dimensions and weight of the HGST Microdrive.

16 (typical)Weight (grams)

36.400.15Length (mm)42.800.101Width (mm)

5.0 + 0.0/0.1Height (mm)

Figure 14. Physical dimensions and weight

7.5.2 Mechanical dimensions

Figure 15. Mechanical outline of the drive



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7.5.3 Connector See Section, Interface Connector.

7.5.4 Mounting orientationThe drive will operate in all axes (360).

Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientationis able to run vertically and vice versa.

Vibration test and shock test are to be conducted by mounting the drive to the test table using aspecial fixture.

7.5.5 Load/Unload mechanismThe head load/unload mechanism is provided to protect the disk during shipping, movement, or storage.Upon power down, a head unload mechanism secures the heads at the unload position. See Section,Nonoperating shock for additional details.

7.6 Vibration and shockAll vibration and shock measurements in this section are for the drive without the mountingattachments for the systems. The input level is applied to the normal drive mounting points.

7.6.1 Operating vibrationThe drive will operate without a hard error while being subjected to the following vibration levels.

7.6.1.1 Operating random vibrationThe test consits of 30 minutes of random vibration using the power spectral density (PSD) levelsspecified in C-S 1-9711-002 (1990-03) as V5L. The vibration test level for V5L is 6.57 m/sec 2 RMS.

4.80 x E-25004.80 x E-22000.96 x E-11500.96 x E-1657.68 x E-1627.68 x E-1481.05 x E-1451.05 x E-1171.92 x E-35(m/sec 2)2Frequency (Hz)

Note: Random vibration PSD profile breakpoints (Operating).

Figure 16. Random vibration

7.6.1.2 Operating swept sine vibration

9.8 m/sec 2 (Zero-to-peak), 5 to 500 to 5 Hz sine wave2.0 oct/min sweep rate



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7.6.2 Nonoperating vibration

7.6.2.1 Nonoperating random vibration

The test consists of a random vibration applied in each of three mutually perpendicular axes with a15-minute duration per axis. The Power Spectral Density (PSD) levels for the test simulates the

shipping and relocation environment which is shown below.

1.7285001.728402.885

0.0962.5

Power Spectral Density(m/sec 2)2 /Hz)

Frequency (Hz)

Note: Overall RMS level of vibration is 29.49 m/sec 2 RMS.Figure 17. Random vibration PSD profile breakpoints (nonoperating)

7.6.2.2 Nonoperating swept sine vibration49 m/sec 2 (zero-to-peak), 10 to 500 to 10 Hz sine wave0.5 oct/min sweep rate

7.6.3 Operating shockThe drive meets the following criteria while operating under the conditions described as follows:

The shock test consists of ten shock inputs in each axis and direction for a total of 60 shocks.

There must be a minimum delay of 3 seconds between shock pulses. Soft errors and automaticretries are allowed during the test.

No data loss or permanent damage occurs during a half-sine shock pulse of 1960 m/sec2

of 2-ms duration and a half-sine shock pulse of 98 m/sec 2 of 11-ms duration.

The input level shall be applied to the normal disk drive subsystem mounting points of the deviceinto which it is installed, as mounted in normal system use.

7.6.4 Nonoperating shockThe disk drive must withstand with no damage a half-sine wave shock pulse of 1176 m/sec 2 of 11-msduration and a half-sine wave shock pulse of 19600 m/sec 2 of 1-ms duration on six sides when headsare unloaded. (When the power is not applied to the unit, the heads are automatically located on theunloaded position.)

All shocks shall be applied in each direction of the drives three mutually perpendicular axes, one axis

at a time. Input levels shall be measured at the frame of the disk drive. The input level shall beapplied to the device into which the HGS T Microdrive is mounted. Through this device the operatingshock is imparted to the HGS T Microdrive through the normal disk drive guide rails and connector retention mountings of the device under test.

7.7 Acoustics

7.7.1 Sound power levelThe criteria of A-weighted sound power level is described as follows.

Measurements are to be taken in accordance with ISO 7779. The mean of 40 drives is to be less than

the typical value. Each drive is to be less than the maximum value. Drives are to meet thisrequirement in both board down orientations.



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2.42.1Operating2.01.8Idle

MaximumTypicalA-weighted sound power (Bels)

Figure 18 . Sound power levels

Background power levels of the acoustic test chamber for each octave band are to be recorded.

Sound power tests are to be conducted with the drive supported by spacers so that the lower surfaceof the drive is located at 253 mm height from the chamber floor. No sound absorbing material is used.

The acoustical characteristics of the disk drive are measured under the following conditions:

Mode definition

Idle modePower on, disks spinning, track following, unit ready to receive and respond to control linecommand

Operating modeContinuous random cylinder selection and seek operation of actuator with a dwell time at eachcylinder. Seek rate for the drive can be calculated as follows:

Ns = 0.4 / (Tt + T1)

where

Ns = average seek rate in seeks/secondTt = published seek time from one random track to another without including rotational latencyT1 = equivalent time, in seconds, for the drive to rotate by half a revolution

7.7.2 Discrete tone penalty

Discrete tone penalties are added to the A-weighted sound power (LW) with the following formulaonly when determining compliance:

LWt(spec) = LW + 0.1Pt + 0.3 < 4.0 (Bels)

where

LW = A-weighted sound power levelPt = Value of discrete tone penalty [= dLt6.0 (dBA)]dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band



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7.8 Identification labelsThe labels are affixed to every drive.

The top side of the label contains

Model namePart number The statement "Made by HGS T"Country of originNotifications to the customer The marks of agencies approvalBar code of the serial numbers

The bottom side of the label contains

The HGS T logoThe capacityThe product name (Microdrive)

Due to space limitations, no additional requirements by customer are allowed.

7.9 Electromagnetic compatibilityThe drivewhen installed in a suitable enclosure and exercised with a random accessing routine atmaximum data ratemeets the following worldwide EMC requirements.

United States Federal Communications Commission (FCC) Rules and Regulations (Class B),Part 15

UE EMC Directive Technical Requirements and Conformity Assessment Procedures:NB 20-0001-038

HGS T small LES development will provide technical support to assist users in complying with theEMC requirements.

7.9.1 CE MarkThe product is certified for compliance with EC directive 89/336/EEC. The EC marking for thecertification appears on the drive.

7.9.2 C-Tick MarkThe product complies with the following Australian EMC standardlimits and methods of measurement of radio disturbance characteristics of information technology equipment per documentAS/NZS 3548:1995 Class B,

7.10 Safety

7.10.1 Underwriters Lab (UL) approvalAll models of the drive comply with UL 1950.

7.10.2 Canadian Standards Authority (CSA) approvalAll models of the drive comply with CSA C22.2 950-M1995.



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7.10.3 IEC complianceAll models of the drive comply with IEC 950.

7.10.4 German Safety Mark

All models of the drive are approved by TUV on Test Requirement EN 60 950:1988/A1:1990, but theGS mark has not been obtained.

7.10.5 FlammabilityPrinted circuit boards used in this product are made of material with a UL recognized flammabilityrating of V-1 or better. The flammability rating is marked or etched on the board. All other parts notconsidered electrical components except for minor mechanical parts are made of material with a ULrecognized flammability rating of V-1 or better.

7.10.6 Safe handling

The products are designed for safe handling with regards to sharp edges and corners.

7.10.7 EnvironmentThe product does not contain any known or suspected carcinogens.

Environmental controls meet or exceed all applicable government regulations in the country of origin.Safe chemical usage and manufacturing control are used to protect the environment. Anenvironmental impact assessment has been done on the manufacturing process used to build thedrive, the drive itself, and the disposal of the drive at the end of its life.

Production also meets the requirements of the international treaty on chloroflurocarbon (CFC) controlknown as the United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon

1211, Halon 1301, and Halon 2402. Although not specified by the Protocol, CFC-112 is alsocontrolled. In addition to the Protocol HGST requires the following:

No packaging used for the shipment of the product uses controlled CFCs in the manufacturingprocess.

No manufacturing processes for parts or assembliesincluding printed circuit boardsusecontrolled CFC materials.

7.10.8 Secondary circuit protectionThis product utilizes printed circuit wiring that must be protected against the possibility of sustainedcombustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against

Combustion). Adequate secondary over-current protection is the responsibility of the using system.The user protects the HDD from its electrical short circuit problem. A 0.5-Amp limit is required for safety purposes.

7.11 PackagingDrives are shipped in appropriate containers and placed on pallets in accordance with HGST Supplier Packaging Instruction (HGST specification GA-21-9261-8).

Drives procured under this specification are assembled and tested using "Electrostatic DischargeProtection" process and precedureHGST document number EN/14/0116. A protection systemsuitable for the fixed disk drive must be installed and monitored by the appropriate ME/QA function.The goal is to prevent electrostatic potential from accumulating on any object which may deliberatelyor inadvertently be brought into contact with the drive.



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Drives are shipped in ESD protective bags as defined in the HGS T specification control drawing(P/N 6937283).



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8.0 Electrical interface specificationsThe following figure defines all the DC characteristics of the drive. Unless otherwise stated, thefollowing are the electrical interface requirements:

Vcc = 5 5% VVcc = 3.3 5% V

Ta = 070C (70CMax at Top cover of the drive)

(See Section,Environment)

C 40 to 70Storage temperatureTstgC070Operating TemperatureTopr

Watt1.2Ta = 25CPower consumptionPd

Volts 0.3 to V CC + 0.3Output VoltageVo

Volts 0.3 to V CC + 0.3Input VoltageVi

Volts 0.3 to 7.0

with respect to ground

Input power Vcc

UnitsConditionsMeasurement methodItemSymbol

Figure 19 . DC characteristics

8.1 CablingRefer to CompactFlash specification.

8.2 Interface connector The CompactFlash (CF) interface connector is designed to meet the connector interface specificationspecified in CF specification revision 1.4.

8.3 Signal definitionFor the pin assignments of the interface signals, refer to the CompactFlash specification revision 1.4.

8.4 Signal descriptionRefer to Table 4-2 of CompactFlash specification revision 1.4 with the following exceptions:

In True IDE Mode -INPACK (pin 43) is used as DMARQ (DMA request) for DMA data transfers.This signal is asserted by the device when it is ready to transfer data to or from the host.

In True IDE Mode -REG (pin 44) is used as -DMACK (DMA acknowledge) for DMA datatransfers. This signal is used by the host in response to DMARQ to initiate DMA transfers.



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8.5 Interface logic signal levelsThe interface logic signal has the following electrical specifications:

140 90 20 14

OE#, WE#,REG#,BVD1, BVD2,CSEL

5 5D15D0

1 1

CE1#, CE2#,IORD#,IOWR#,A10A0,RESETVIN = GND

IDE Mode

5 5D15D01 1A10A0

70 45 10 7RESET

mA

140 90 20 14

CE1#, CE2#,OE#, WE#,REG#,IORD#,IOWR#,CSEL

VIN = GNDPC Card Mode

"L"InputCurrent

IIL

5 5BVD1,BVD2,D15D0

110709063RESET

mA

1 1

CE1#, CE2#,OE#, WE#,IORD#,IOWR#,REG#,CSEL,A10A0

VIN=VCC"H"InputCurrent

IIH

the other outputs

IOH = 4.0 mA (3.465V)

7.0 mA (5.25 V)

Volts0.4

READY,INPACK#,BVDI,BVD2

IOH =2.5 mA

(3.465V)4.0 mA (5.25 V)"L"

OutputVoltage

VOL

the other computer IOH =3.5 mA (3.135 V)7.0 mA (4.75 V)

Volts3.453.00

READY,INPACK#,BVDI,BVD2

IOH =2.0 mA (3.135V)4.0mA (4.75V)

"H"OutputVoltage

VOH

5.25 V3.465V4.75 V3.135

V

UnitMaximumTypica

l Minimum

ConditionParameter Symbol

Figure 20. Interface logic signal levels.



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8.6 Attribute Memory Read timingThe Attribute Memory access time is defined as 300 ns. Detailed timing specifications are shown inthe following two figures.

0Data Valid from Address ChangetvA5Output Enable Time from OEtenOE5Output Enable Time from CEtenCE

100Output Disable time from OEtdisOE100Output Disable Time from CEtdisCE150Output Enable Access TimetaOE300Card Enable Access TimetaCE300Address Access TimetaA

300Read Cycle TimetcR

Maximum(ns)

Typical(ns)

Minimum(ns)ItemSymbol

Figure 21. Attribute Memory Read timing data

Data invalid

Memory Timing ChartRead Cycle

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

CE#

OE#

Dm(Dout)

WE#= ?

?c(?)

??(A)??(CE)

tv(A)

tdis(CE)ten(CE)ta(OE)

tdis(CE)

ten(OE)

Hi-Z

Note?

An-REG

VIH

VILWAIT#

ta(OE)

tdis(OE)

Figure 22. Attribute Memory Read timing diagram



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8.7 Common Memory Read timingDetailed timing specifications are shown in the following figure.

0Data Valid from Address ChangetvA5Output Enable Time from OEtenOE5Output Enable Time from CEtenCE

100Output Disable time from OEtdisOE100Output Disable Time from CEtdisCE125Output Enable Access TimetaOE250Card Enable Access TimetaCE250Address Access TimetaA

250Read Cycle TimetcR

Maximum(ns)Typical(ns)Minimum(ns)ItemSymbol

Figure 23. Common Memory Read timing



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8.9 I/O Input (Read) timingDetailed timing specifications are shown in the following two figures.

350Wait Width Timetw (WT)0Data Delay from Wait Risingtdr (WT)

35Wait Deay Falling from IORDtdf WT (IIORD)35IOIS16 Delay Rising from Addresstdr iois16 (ADR)35IOIS16 Delay Falling from Addresstdf IOIS16 (ADR)45INPACK Delay Rising from IORDtdr INPACK (IORD)45INPACK Delay Falling from IORDtdf INPACK (IORD)

0REG Hold following IORDth REG (IORD)5REG Setup before IORDtsu REG (IORD)

20CE Hold following IORDth CE (IORD)5CE Setup before IORDtsu CE (IORD)

20Address Hold following IORDth A (IORD)70Address Setup before IORDtsu A (IORD)

165IORD width Timetw (IORD)0Data Hold following IORDth (IORD)

twData Delay after IORDtd (IORD)

Maximum(ns)Minimum(ns)ItemSymbol

Figure 26. Common Memory Read Timing data

A[10::0]

REG#

CE#

IORD#

INPACK#

IOIS16#

WAIT#

D[15::0]

tsuREG(IORD)

tsuCE(IORD)

tsuCE(IORD)

tdfIOIS16(ADR)

tdfINPACK(IORD)

td(IORD)tdr(WT)

tw(WT)

tdfWT(IORD)

th(IORD)

tdrIOIS16(ADR)

tdrINPACK(ADR)

tw(IORD)

thCE(IORD)

thA(IORD)th

REG(IORD)

Figure 27. Common Memory Read Timing diagram



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8.10 I/O Input (Write) timingDetailed timing specifications are shown in the following two figures.

350Wait Width Timetw(WT)0IOWR high from Wait hightdr IOWR(WT)

35Wait Deay Falling from IOWRtdfWT(IOWR)35IOIS16 Delay rising from Addresstdr IOIS16 (ADR)35IOIS16 Delay Falling from Addresstdf IOIS16 (ADR)

0REG Hold following IOWRthREG (IOWR)5REG Setup before IOWRtsuREG(IOWR)

20CE Hold following IOWRthCE(IOWR)5CE Setup before IOWRtsuCE(IOWR)

20Address Hold following IOWRthA(IOWR)70Address Setup before IOWRtsuA(IOWR)

165IOWR width Timetw(IOWR)30Data Hold following IOWRth(IOWR) 60Data Setup before IOWRtd(IOWR)

Maximum(ns)


Note: The maximum load on -WAIT, -INPACK, and -IOIS16 is 1LST TL with a 50 pF total load.

Figure 28. I/O Write timing data

A[10::0]

REG#

CE#

IORD#

INPACK#

IOIS16#

WAIT#

D[15::0]

tsuREG(IORD)

tsuCE(IORD)

tsuCE(IORD)

tdfIOIS16(ADR)

tdfINPACK(IORD)

td(IORD)tdr(WT)

tw(WT)

tdfWT(IORD)

th(IORD)

tdrIOIS16(ADR)

tdrINPACK(ADR)

tw(IORD)

thCE(IORD)

thA(IORD)th

REG(IORD)

Figure 29. I/O Write timing diagram



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8.11 True IDE Mode I/O Input (Read) TimingDetailed timing specifications are shown in the following two figures.

35IOIS16 Delay Rising fromAddresstdf IOIS16 (ADR)

35IOIS16 Delay Falling fromAddresstdf IOIS16 (ADR)

20CE Hold following IORDth CE (IORD)5CE Setup before IORDtsu CE (IORD)

20Address Hold following IORDth A (IORD)70Address Setup before IORDtsu A (IORD)

165IORD Width Timetw (IORD)0Data Hold following IORDth (IORD)

100Data Delay after IORDtd (IORD)

Maximum(ns)Minimum(ns)ItemSymbol

Figure 30. True IDE Mode IO Input (Read) timing data

An

Dout

CE#

IORD#

tsuCE(IORD)

tw(IORD)

thCE(IORD)

IOIS16#

tdfIOIS16(ADR)

tsuA(IORD)

td(IORD)

thA(IORD)

th(IORD)

Note: The maximum load on -IOIS16 is a 1 LSTTL with a 50 pF total load.

Figure 31. True IDE Mode IO Input (Read) timing diagram



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8.12 True IDE Mode Multiword DMA Data Transfer TimingThe device supports multiword DMA data transfer for Read DMA and Write DMA commands, whichare available in true IDE mode only. In multiword DMA data transfer, INPACK# is used as DMARQand REG# is used as DMACK#. Detailed timing specifications are shown in the following figure. Note

that the fastest transfer timing is equivalent to DMA Mode 2 as defined in ATA/ATAPI-4 standard.

25DMACK# to tristatetZ35IOW# to DMARQ delaytLw35IOR# to DMARQ delaytLr

25IOW# negated pulse widthtKw (*1)25IOR# negated pulse widthtKr (*1) 5IOR#/DIOW# to DMACK# holdtJ

0DMACK# to IOR#/IOW# setuptI10IOW# data holdtH20IOR#/IOW# data setuptG5IOR# data holdtF

60IOR# data accesstE70IOR#/IOW#tD (*1)

DMACK# to DMARQ delaytC120Cycle timet0 (*1)

Maximum(ns)


Notes:(*1) t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKr or tKw,as appropriate) is the minimum command recovery time or command inactive time. The actual cycletime equals the sum of the actual command active time and the actual command inactive time. Thethree timing requirements of t0, tD, tK shall be met. The minimum tootle cycle time requirement, t0, isgreater than the sum of tD and tK. This means the host can lengthen either tD or tK or both to ensure

that t0 is equal to the value reported in the devices identify drive data.

Figure 32. Multiword DMA data transfer timing data



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8.13 True IDE Mode Ultra DMA Data Transfer TimingThe device supports Ultra DMA data transfer for Read DMA and Write DMA commands, which areavailable in true IDE mode only. In Ultra DMA data transfer, INPACK# is used as DMARQ and REG#is used as DMACK#. Detailed timing specifications are shown in the following figure. Note that the

fastest transfer timing is equivalent to Ultra DMA Mode 2 as defined in ATA/ATAPI-4 standard.

50Time from STROBE edge to negation of

DMARQ or assertion of STOPtSS

20Setup and hold times for DMACK-tACK0Minimum time before driving IORDYtIORDYY

20Maximum time before releasing IORDYtIORDYZ100Ready-to-pause timetRP

600Ready-to-final-STROBE timetRFS7020Envelope timetENV

20Minimum delay time required for outputtZAH

10Maximum Time allowed for output driversto releasetAZ

0Unlimited interlock timetUI20Interlock time with minimumtMLI

1500Limited interlock timetLI170First STROBE timetFS

31.0Time from data output released-to-drivinguntil the first transition of critical timingtDZFS

0Time from STROBE outputreleased-to-driving until the first transitionof critial timing

tZFS

6.2CRC word valid hold time at sender tCVH31.0CRC word valid setup time at hosttCVS5.0CRC word hold time at devicetCH7.0CRC word setup time at devicetCS6.2Data Valid hold time at sender tDVH

31.0Data Valid setup time at sender tDVS5.0Data hold time at recipienttDH7.0Data setup time at recipienttDS

115Two cycle time allowing for clockvariationst2cyc

54Cycle Time allowing for asymmetry andclock variationstcyc

120Typical sustained average two Cycle timet2cyctyp

Maximum(ns)


Figure 33. Ultra DMA data transfer timing data



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8.14 Power on/off timingDetailed timing specifications are shown in the following two figures.

ms0ts (Hi-zRESET)

ms1th (Hi-zRESET)

us10RESET pulse widthtw (RESET)

ms300390% of V CC 10%Power falling timetpf

ms400.110% 90% of V CCPower rising timetpr

us1Card Enable Recovery timetrec (Vcc)

ms20RESET Setup timetsu (RESET)

ms20Card Enable Setup timetsu(V CC )

Volts

VCC + 0.1VIHVIH =< V CC

Volts

VCC + 0.1VCCVCC - 0.12 V =< V CC < V IH Card Enable signal levelVi(CE)

Volts

VCC00 V =< V CC < 2 V

Units

Max.Typ.MinimumConditionItemSymbol

Figure 34. Power On/Off timing data



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tpr tsu(Vcc)

Vcc

Vcc@90%

Vcc@10%

VIH

2V

tsu(RESET)

th(Hi-zRESET)

tsu(RESET)

tw(RESET)

RESET

tw(RESET)

Hi-z

Vcc

Vcc@90%trec(Vcc)

VIH

Vcc@10%2V

ts(Hi-zRESET)

Hi-z

tpf

CE1#,CE2#

CE1#,CE2#

Figure 35. Power On/Off timing diagram



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Part 2. Interface specification


Hard disk drive specfication for Hitachi Microdrive TM 3K4


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9 General

9.1 Introduction

This part of specification describes the host interface of Hitachi Microdrive 3K4.The interface conforms to the CF+ and CompactFlash Specification with certainlimitations described in " 2 Deviations from Standard " on page 0.Hitachi Microdrive 3K4 following new functions included byCompactFlash Specification 1.4 or newer standard.

Hitachi Microdrive 3K4 support following functions as Vendor Specific Function.SENSE CONDITION commandFormat Unit commandMetadata Storage Function

The following terminology is used in this part of specification.

Interrupt request (Device or Host)INTRQ

The command which is executed first right after power on reset or hard resetwhen the initial power mode at power on is Standby mode.

First Command

Host indicates the system that the device is attached to.Host

Device indicates Hitachi Microdrive 3K4Device




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10 Deviations from Standard

WRITE VERIFY command does not include read verification after writeoperation. The function is exactly same as WRITE SECTORS command.

Write Verify

If STANDBY command or IDLE command is used with the Sector CountRegister being zero, the standby timer is programmed to 109 minutes,instead of disabling automatic standby function. Note that if the advanced

power management level is less than 80h, which is power-on default, thetransition timing to enter Standby mode is determined by either thestandby timer or Adaptive Battery File Extender algorithm, whichever meets the condition first.

Standby Timer

The device supports Ultra DMA transfer mode. BBK bit in Error register is replaced by ICRCE ( Interface CRC Error ) bit.ICRCE (CRC)




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Socket and Copy Register Write

011000100100X

Socket and Copy Register Read

011000101000X

Pin Replacement Register Write

001000100100X

Pin Replacement Register Read

001000101000XCard Status Register Write010000100100XCard Status Register Read010000101000X

Configuration OptionRegister Write000000100100X

Configuration OptionRegister Read

000000101000X

Selected spaceA0A1A2A3A8-A4A9A10-WE-OE-REG-CE1-CE2

Figure 2. Configuration registers decoding




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11.2 Card configuration registers

The drive has a set of configuration registers in attribute memory space. These registersare used to control the configurable characteristics of the card. The configurablecharacteristics include the electrical interface, I/O address space, interrupt request, and

power requirements of the card. These registers also provide a method for accessingstatus information about the card. The information can be used to arbitrate betweenmultiple-interrupt sources on the same interrupt request level. Addresses of theconfiguration registers are specified by the Configuration registers Base Address in theTPCC_RADR field of the Configuration Tuple and offset relative to the base address.For example, the Configuration and Status register can be located at offset 02h from the

base address. The addresses of the card configuration registers should always be readfrom the CIS since these addresses may vary in future products.

11.2.1 Configuration Option Register (Offset 00h)

The Configuration Option Register is used to configure the cards interface, addressdecoding, and interrupt and to issue a soft reset to the drive.

Conf0Conf1Conf2Conf3Conf4Conf5LevlREQSRESETR/WD0D1D2D3D4D5D6D7Operation

Figure 3. Configuration Option Register (Offset 00h)

SRESET: Soft Reset -Setting this bit to one (1), waiting the minimum reset width time and returning tozero (0) places the card in the Reset state. Setting this bit to one (1) is equivalent to assertion of +RESETsignal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the card in the sameunconfigured, Reset state as following power-up and hardware reset. This bit is set to zero (0) by

power-up and hardware reset. Using PCMCIA Soft Reset is considered a hard reset from the ATA pointof view. An "ATA" soft reset is issued through the Device Control Register.

LevlREQ: This bit is set to (1) when level mode Interrupt is selected, and zero (0) when pulse mode isselected. This bit is set to zero (0) by power-up and hardware reset. When the card is in Level Mode, the-IREQ pin is pulled up to Vcc on the card and asserted low to signal an interrupt. The interrupt is keptasserted until the host reads the card status register, thereby resetting the interrupt indication and causing-IREQ to be deasserted. When the card is in pulse mode, the card signals an interrupt by the trailing edgeof the negative pulse which width is at least 0.5ms.

Conf5 - Conf0: Configuration Index. This is set to zero (0) by power-up and hardware reset. It is used toselect operation mode of the card as shown below. Conf5 and Conf4 are reserved and must be written aszero (0) .




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Secondary I/O mapped, 170h n 177h/376h n377h

110000

Primary I/O mapped, 1F0h n 1F7h/3F6h n3F7h

010000

I/O mapped 16 contiguous registers at any

16-byte system decoded boundary100000

Memory mapped000000

Card Configuration ModeConf0Conf1Conf2Conf3Conf4Conf5

Figure 4. Configuration Option Register (Offset 00h)

11.2.2 Card Configuration Status Register (Offset 02h)

The Card Configuration and Status Register contains information about the cardcondition.

00PwrDwn0-XEIOis8SigChg0Write0IntPwrDwn0-XEIOis8SigChgChangedRead

D0D1D2D3D4D5D6D7Operation

Figure 5. Configuration Status Register (Offset 02h)

Changed: This bit indicates that one or both of the Pin Replacement register CRdy, or CWProt bits areset to one (1). When the Changed bit is set, pin 46 (-STSCHG) is held low if the SigChg bit is a one (1)and the card is configured for the I/O interface.SigChg: This bit serves as a gate for pin 46 (-STSCHG). If the card is configured for the I/O interfaceand this bit is zero (0), pin 46 (-STSCHG) is held high. If the card is configured for the I/O interface and

both the Changed and SigChg bits are set to one (1), the card asserts pin 46 (-STSCHG) upon changes inthe Changed bit.IOis8: This bit is set to one (1) when the card is configured in 8-bit I/O mode as the host provides I/Ocycles only with an 8-bit (D7-D0) data path.-XE: Extended power enabled. When the host sets this bit to zero (0), the card enables extended power operations. When the host sets this field to one (1), the card disables extended power operations. Whenthis filed is read, the bit indicates the card's acceptance of extended power operations. If it is read as one(1), extended power operations are being disabled. If it is read as zero (0), the card can perform extended

power operations. This bit is read as zero (0) after power-up and hardware reset. Identify Deviceinformation word 170 also has -XE bit for the same purpose. These -XE bits are always consistent.Extended power operations are defined as a command that requires the hosts extended power capability.For the drive, extended power operations includes any read, write and seek commands. Identify Device,Set Features (Enable Extended Power and Disable Extended Power), Request Sense and Execute DeviceDiagnostics are not extended power operations, i.e., these commands can be performed regardless of thesetting in -XE bit.PwrDwn: The device does not change PwrDwn bit even if the power mode is changed as a result of either an internal event or command completion. Also, the state of Rdy/-Bsy signal is not changed whenthe host changes PwrDwn bit is intended for the host system to direct the device's immediate entrance of Standby mode upon command completion. If PwrDwn bit is set to one(1), the device immediately entersStandby mode after command completion, regardless of the standby timer and setting of the advanced

power management level. If PwrDwn is set to zero(0), the device entrance of Standby mode is controlled by both standby timer and Adaptive Battery Life Extender algorithmInt : This bit represents the internal state of the interrupt request. This value is available whether or noteI/O interface has been configured. This signal remains true until the condition which caused the interrupt




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11.3.2 Contiguous I/O mapped addressing

ReservedDevice AddressF11110Device ControlAlternate StatusE01110

2,3Dup. FeaturesDup. Error D101102Dup. Odd WR DataDup. Odd RD Data9100102Dup. Even WR DataDup. Even RD Data800010

CommandStatus711100Device/HeadDevice/Head601100

Cylinder HighCylinder High510100Cylinder LowCylinder Low400100

Sector Number Sector Number 311000Sector CountSector Count201000

2FeaturesError 1100001Even WR DataEven RD Data000000

Notes-IOWR=0-IORD=0OffsetA0A1A2A3-REG

Notes:1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = dont care) as a word register on the combinedOdd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to theoffset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the addressspace of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with-CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byteof the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read)or feature (write) register.2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 isequivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in theorder 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 willaccess consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will

access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However,repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from thedata buffer. Byte accesses to register 9 access only the odd byte of the data.3. The drive does not support accessing the Dup. Features and the Dup. Error as word register at offset 0Ch withCE1 low and CE2 low.4. Address lines that are not indicated are ignored by the drive for accessing all the registers in this table.




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11.3.3 Memory mapped addressing

3Odd WR DataOdd RD Data91xxxx113Even WR DataEven RD Data80xxxx11

ReservedDevice AddressF1111x01Device ControlAlternate StatusE0111x01

2,4

Dup. FeaturesDup. Error D1011x01

2Dup. Odd WR Data

Dup. Odd RDData

91001x01

2Dup. Even WR Data

Dup. Even RDData

80001x01CommandStatus71110x01

Device/HeadDevice/Head60110x01Cylinder HighCylinder High51010x01Cylinder LowCylinder Low40010x01

Sector Number Sector Number 31100x01Sector CountSector Count20100x01

1,2

FeaturesError 11000x01

1,2

Even WR DataEven RD Data00000x01

Notes

-WE=0-OE=0OffsetA0

A1

A2

A3

A9-A4A10-REG

Notes:1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus andEven Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1

low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error andFeature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byteto be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent wordaccess. A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write)register.2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 isequivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in theorder 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 willaccess consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 willaccess consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However,repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data

buffer. Byte accesses to register 9 access only the odd byte of the data.3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between

400h and 7FFh access register 9. This 1 Kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Somehosts, such as the X86 processors, must increment both the source and destination addresses when executing thememory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementingaddress logic embedded within them. This address window allows these hosts and adapters to functionefficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access tothe data buffer within the drive. A word access to address at offset 8 will provide even data on the low-order

byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus.4. The drive does not support accessing the Dup. Features and the Dup. Error as word register at offset 0Ch withCE1 low and CE2 low.




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11.3.4 True IDE Mode addressing

ReservedDevice Address11110Device ControlAlternate Status01110

CommandStatus11101Device/HeadDevice/Head01101

Cylinder HighCylinder High10101Cylinder LowCylinder Low00101

Sector Number Sector Number 11001Sector CountSector Count01001 FeaturesError 10001

WR DataRD Data00001-IOWR=0-IORD=0A0A1A2-CE1-CE2

The Command Block Registers are used for sending commands to the device or posting status from thedevice.The Control Block Registers are used for device control and to post alternate status.




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11.4.6 Device Control Register

0-IENSRST1----01234567

Device Control Register

This register is used to control thr Compact Flash Storage Card interrupt request and toissue an ATA soft reset to the card. This register can be wrriten even if the device isBUSY.

Interrupt Enable. When -IEN=0, and the device is selected, device interruptsto the host will be enabled. When -IEN=1, or the device is not selected,device interrupts to the host will be disabled.

-IEN

Software Reset. The device is held reset when RST=1. Setting RST=0reenables the device.The host must set RST=1 and wait for at least 5 microseconds before settingRST=0, to ensure that the device recognizes the reset.

SRST (RST)

Bit Definitions

11.4.7 Drive Address Register

-DS0-DS1-H0-H1-H2-H3-WTGHIZ01234567

Drive Address Register

This register contains the inverted drive select and head select addresses of the currentlyselected drive.

-Drive Select 0. Drive Select bit for device 0, active low. DS0=0 when device0 (master) is selected and active.

-DS0

-Drive Select 1. Drive select bit for device 1, active low. DS1=0 whendevice 1 (slave) is selected and active.

-DS1

-Head Select. These four bits are the one's complement of the binary codedaddress of the currently selected head. -H0 is the least significant.

-H3,-H2,-H1,-H0

-Write Gate. This bit is 0 when writing to the disk device is in progress.-WTG

High Impedance. This bit is not device and will always be in a highimpedance state.HIZ

Bit Definitions




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11.4.8 Device/Head Register

HS0HS1HS2HS3DRV1L1 01234567

Device/Head Register

This register contains the device and head numbers.

Head Select. These four bits indicate binary encoded address of the head.HS0 is the least significant bit. At command completion, these bits areupdated to reflect the currently selected head.The head number may be from zero to the number of heads minus one.In LBA mode, HS3 through HS0 contain bits 24-27 of the LBA. Atcommand completion, these bits are updated to reflect the current LBA bits24-27.

HS3,HS2,HS1,HS0

Device. When DRV=0, device 0 (master) is selected. When DRV=1, device1 (slave) is selected.

DRV

Binary encoded address mode select. When L=0, addressing is by CHSmode. When L=1, addressing is by LBA mode.

L

Bit Definitions

11.4.9 Error Register

AMNFTK0NABRT0IDNF0UNCCRC01234567

Error Register

This register contains status from the last command executed by the device, or adiagnostic code.

At the completion of any command except Execute Device Diagnostic, the contents of this register are valid always even if ERR=0 in the Status Register.Following a power on, a reset, or completion of an EEXECUTE DEVICE DIAGNOSTICS command, this register contains a diagnosticcode. See "Diagnostic Codes" on page 29 for the definition.




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11.4.13 Status Register

ERR IDXCORR DRQDSCDFDRDYBSY 01234567

Status Register

This register contains the device status. The contents of this register are updatedwhenever an error occurs and at the completion of each command.If the host reads this register when an interrupt is pending, it is considered to be theinterrupt acknowledge. Any pending interrupt is cleared whenever this register is read.If BSY=1, no other bits in the register are valid.

ERR=1 indicates that an error occurred during execution of the previouscommand. The Error Register should be read to determine the error type.The device sets ERR=0 when the next command is received from the host.

ERR Index. Always 0.IDX

Corrected Data. Always 0.CORR (COR)

Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write theCommand register when DRQ=1.

DRQ

Device Seek Complete. DSC=1 indicates that a seek has completed and thedevice head is settled over a track. DSC is set to 0 by the device just before aseek begins. When an error occurs, this bit is not changed until the StatusRegister is read by the host, at which time the bit again indicates the currentseek complete status.When the device enters into or is in Standby mode, this bit is set by device inspite of not spinning up.

DSC

Device Fault. DF=1 indicates that the device has detected a write faultcondition. DF is set to 0 after the Status Register is read by the host.

DF

Device Ready. RDY=1 indicates that the device is capable of responding toa command. RDY will be set to 0 during power on until the device is readyto accept a command.

DRDY (RDY)

Busy. BSY=1 whenever the device is accessing the registers. The hostshould not read or write any registers when BSY=1. If the host reads anyregister when BSY=1, the contents of the Status Register will be returned.

BSY

Bit Definitions




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12 General Operation Descriptions

12.1 Reset ResponseThere are three types of resets in a CompactFlash device: a power-on reset, a hardware reset, and asoftware reset. There is also a reset called PCMCIA soft reset, which uses bit 7 of Configuration OptionRegister. It is treated as a hard reset.

A reset initiated by changing bit 7 (SRESET) of ConfigurationOption Register as 0, 1 then 0. It is equivalent to a hardware reset

PCMCIA soft reset

A reset initiated by changing bit 2 (SRST) of Device ControlRegister as 0, 1 then 0

Soft Reset (Software Reset)

A reset initiated by a raising edge of RESET signal (in True IDEmode)A reset initiated by a falling edge of RESET signal (In PC Cardmode)

Hard Reset (Hardware Reset)A reset carried out upon device's every power up sequencePower On Reset (POR)

DescriptionType

Figure 8. 36Reset type

X00Reset Standby timer ABLE modeDMA transfer mode (3)PIO transfer modeByte transfer mode (3)On-demand prefetchDelayed WriteECC bytes for Read Long and Write LongRead look-aheadWrite cacheMultiple mode

Logical geometry (number of cylinders/heads/sectors)

'(4)OOReverting programmed parameters to power-on defaultOOOPDIAG handshake (3)OOODASP handshake (3)XOOInitialization of registers at attribute memoryOOOInitialization of task file registers (2)XOOInternal diagnosticsXOOInitialization of hardware

'(1)'(1) Aborting Device operationOO Aborting Host interface

Soft ResetHard ResetPOR Description

Figure 9. 37Reset Response

Notes: - not applicableO - executedX - not executed

(1) If the device receives a reset during cached writing, the reset completes after cached writing completes.

(2) Initialized value of task file registers are shown in figure 58 below.(3) True IDE mode only.




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(4) If the device has received Set Features with feature code CCh prior to a reset, setting is reverted tothe power-on default.

12.1.1 Register Initialization

After power on, hard reset, or software reset, the register values are initialized as shownin

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