All Digital CMOS Self-sample Vernier Delay Line

Circuit for Clock Jitter Measurement

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1. 15 3 http://thesis.lib.ncu.edu.tw/paper.htm

2.

3.

4.

i

(PLL)(jitter)

one-period-delay

circuit jitter-measurement circuit

One-period-delay circuit Jitter

Measurement circuit

TSMC 0.35um 2P4Mone-period-delay circuit

300ps jitter-measurement circuit 15ps

100MHz~400MHz

ii

Abstract As the improvement of semiconductor technology, VLSI circuits has developed

into System-On-a-ChipSoC. When many systems integrated into a chip, the

sequence of clock of every circuit must be accurate. In the system, clock skew

will affect the performance of the system. The Phase-Locked Loop (PLL) is

recognized as one of the important components for clock recovery.

In PLL circuits, the value of output clock jitter effect the performance of PLL. In

the past, the jitter is measured by the external equipment. But, with the

increased operating frequency, it will have a high cost on jitter measuring by

external equipments. Sometimes probes of external equipments will be

induced noise. The measurement result will be different. Because this reason,

the built-in clock jitter measurement circuits are proposed. Using built-in clock

jitter measurement circuits to measure the clock jitter that can reduce testing

cost, decrease the effect of noise, and speeding up the jitter measurement.

In the past, the vernier delay line circuit has high circuit resolution but high chip

area. In this all digital CMOS self-sample vernier delay line circuit has two

stages. One is one-period-delay circuit, the other is jitter measurement circuit.

In this circuit, the one-period-delay circuit is used to delay the clock to

measurement point quickly and the jitter measurement circuit created high

circuit resolution to measure the jitter. In this way, the circuit can measure the

clock jitter quickly and accurately and reduce the chip area.

The proposed circuit is designed in TSMC 0.35um 2P4M CMOS process. The

resolution of one-period-delay circuit is 300ps and that of jitter measurement

circuit is 15ps. The measured frequency of the proposed circuit is 100MHz to

400MHz.

iii

Contents Abstract.................................................................. ii List of Table ............................................................. v List of Figure........................................................... vi Chapter 1 Introduction.............................................1

1.1 Motivation.....................................................................................................1 1.2 Organization of Thesis ..................................................................................2

Chapter 2 Preview Work .........................................4 2.1 Jitter Definition ...........................................................................................4

2.1.1 Cycle-to-Cycle jitter...........................................................................4 2.1.2 Period Jitter ........................................................................................6 2.1.3 Long-Term Jitter I ..............................................................................7 2.1.4 Long-Term Jitter II.............................................................................8

2.2 Jitter Histogram...........................................................................................8 Chapter 3 Jitter Measurement Technology ........... 11

3.1 Off-chip Jitter Measurement ..................................................................... 11 3.2 On Chip Jitter Measurement .....................................................................12 3.3 Operation of BIJM Circuits ......................................................................14 3.4 Traditional Methodology ..........................................................................15 3.5 Delay Chain Circuit ..................................................................................16

3.5.1 Operation of Delay Chain Circuit ..................................................16 3.5.2 Jitter Measurement of Delay Chain Circuit ...................................17 3.5.3 Characteristic of Delay Chain Circuit............................................18

3.6 Delay Loop Circuit ...................................................................................18 3.6.1 Operation of Delay Loop Circuit .....................................................18 3.6.2 Jitter Measurement of Delay Chain Circuit ...................................19 3.6.3 Characteristic of Delay Chain Circuit............................................19

3.7 Vernier Delay Line Circuit........................................................................203.7.1 Operation of Vernier Delay Line Circuit..........................................20 3.7.2 Jitter Measurement of Vernier Delay Line Circuit...........................21 3.7.3 Characteristic of Vernier Delay Line Circuit ...................................22

Chapter 4 Proposed BIJM Circuit..........................23 4.1 Structure of the Proposed BIJM Circuit....................................................23 4.2 Proposed Methodology .............................................................................24 4.3 One-period-delay Circuit ..........................................................................25

4.3.1 Structure of One-period-delay Circuit .............................................25 4.3.2 Operation of One-period-delay Circuit ............................................26 4.3.3 Design of One-period-delay Circuit.................................................27

4.4 Jitter-measurement Circuit..........................................................................28 4.4.1 Structure of Jitter-measurement Circuit ...........................................28 4.4.2 Operation of Jitter-measurement Circuit..........................................29 4.4.3 Design of Jitter-measurement Circuit ..............................................29 4.4.4 Control Logic Circuit .......................................................................30

4.5 Operating Principle ...................................................................................31 Chapter 5 Chip implementation.............................33

iv

5.1 Simulation of the proposed circuit ............................................................34 5.1.1 Consideration of Simulation ............................................................35 5.1.2 Simulation of One-period-delay Circuit ..........................................35 5.1.3 Simulation of Jitter-measurement Circuit ........................................36 5.1.4 Simulation of Control Logic Circuit ................................................37

5.2 Layout of the Proposed Circuit .................................................................38 5.3 Measurement Result..................................................................................39

5.3.1 Concept of Measurement .................................................................39 5.3.2 Chip Measurement ...........................................................................40 5.3.3 Measurement Result.........................................................................41 5.3.4 Specification of Circuit ....................................................................44

Chapter 6 Conclusion and Future Work................45 6.1 Conclusion ................................................................................................45 6.2 Future Work ..............................................................................................45

Reference material ................................................46

v

List of Table Table 5.1 Specification of BIJM circuit44

Table 5.2 Comparison of BIJM circuit.44

vi

List of Figure

Figure 2.1 Cycle-to-cycle jitter..........................................................................5 Figure 2.2 Application of cycle-to-cycle jitter ....................................................5 Figure 2.3 Period jitter......................................................................................6 Figure 2.4 Application of period jitter measurement .........................................6 Figure 2.5 Long-term jitter I..............................................................................7 Figure 2.6 Long-term (tracking) jitter II.............................................................8 Figure 2.7 Jitter histogram ...............................................................................9 Figure 2.8 Jitter histogram II ............................................................................9 Figure 2.9 Jitter histogram III ...........................................................................9 Figure 2.9 Jitter histogram IV.........................................................................10 Figure 3.1 Operation of BIJM circuits.............................................................14 Figure 3.2 Traditional methodology................................................................15 Figure 3.3 Delay chain circuit.........................................................................16 Figure 3.5 Jitter measurement of delay chain circuit......................................17 Figure 3.6 Operation of delay chain circuit.....................................................19 Figure 3.7 Operation of vernier delay line circuit............................................20 Figure 3.8 Jitter measurement of vernier delay line circuit .............................21 Figure 4.2 Propose methodology ...................................................................24 Figure 4.3 Structure of one-period-delay circuit .............................................25 Figure 4.4 Operation of one-period-delay circuit ............................................26 Figure 4.6 Structure of jitter-measurement circuit ..........................................28 Figure 4.7 Operation of jitter-measurement circuit .........................................29 Figure 4.8 MOS capacitance..........................................................................30 Figure 4.9 Control logic circuit........................................................................30 Figure 4.10 Operating principle......................................................................32 Figure 5.1 Design procedure..........................................................................34 Figure 5.2 Simulation consideration...............................................................35 Figure 5.3 Simulation of circuit resolution in one-period-circuit ......................36 Figure 5.4 Simulation of circuit resolution in jitter-measurement circuit .........37Figure 5.5 Simulation of control logic circuit...................................................38 Figure 5.6 Photograph of whole chip .............................................................39 Figure 5.7 Layout block of whole chip............................................................39 Figure 5.8 concept of measurement ..............................................................40 Figure 5.9 Measurement setup of the chip.....................................................41 Figure 5.10 100MHz signal mixed with random signal...................................42 Figure 5.11 Measurement result of proposed circuit I ....................................42 Figure 5.10 100MHz signal mixed with square noise.....................................43 Figure 5.11 Measurement result of proposed circuit II ...................................43

1

Chapter 1 Introduction

1.1 Motivation

As the improvement of semiconductor technology, VLSI circuits has developed

into System-On-a-ChipSoC. When many systems integrated into a chip, the

sequence of clock of every circuit must be accurate. In the system, clock skew

will affect the performance of the system. In many practical applications, such

as, wireless phone, optical fiber links or macro-computers. The Phase-Locked

Loop (PLL) is recognized as one of the important components for clock

recovery.

In high-speed system, the PLL circuit is an important component for the clock

recovery. In theory, the PLL circuit is a good clock recovery circuit [1], however,

in the circuit implementation; there is non-ideal effect, clock jitter, in the PLL

circuit. This effect affects the timing accuracy and the signal to noise ratio in

circuits base on a PLL. Sometimes, the clock jitter may cause unacceptable

errors in high-speed systems.

In PLL circuits, the jitter affects the performance of PLL. So, the clock

measurement and testing is the most effective method to estimate the PLL

performance. With increasing frequency resulting from new submicron

technologies, the impact of clock jitter on all function has become more and

more critical. The clock measurement has become a very important job for the

design PLLs [2]. There is a strong pressure to find a low-cost test solution for

PLLs[3].Although measuring timing margins and synchronization requirements

push the limits of traditional test equipment [3], the urgent need for high-speed

clock jitter testing is still not satisfied. It makes designers find a new technology

2

that can substitute for the traditional equipments. However, traditional ways are

still not enough in measuring the clock jitter.

In traditional way, the external equipment would distort the tested clock signal

and change the clock measurement result. In order to achieve a more

convenient clock jitter measurement a Time to Digital ConverterTDC

technology is used to output an all-digital data in the propose method. A built-in

jitter test method is used to realize to the propose method. However, even if

some usable built-in clock jitter measurement BIJMmethods also have been

proposed, the requirements of the test time and circuit area still limited the

circuit application. In order to release these requirements, a new built-in clock

jitter measurement method is proposed. A continuous clock jitter measurement

method is adopted to make a real-time measurement. The proposed circuit

area and test time cab be reduce. And, with the improve circuit structure; no

more external jitter-free clock is needed to sample the clock jitter.

1.2 Organization of Thesis

In PLL circuit design, the half-digital PLL is the most popular used circuit. It has

advantages of less area requirement, simple circuit structure. However, unlike

all-digital PLL, clock jitter of the half-digital PLL circuit cannot be extracted

directly by the circuit internal signal. It needs a specific jitter test circuit to

measure the clock jitter of the half-digital PLL circuit.

In the chapter 2, the different clock jitter is defined. Normally, the common

tested clock jitter can be divided into four parts, period jitter, cycle-to-cycle jitter,

and two different long term jitter. Different jitter definitions play different in the

circuit.

In the chapter 3, the on-chip and off-chip jitter measurement techniques will be

3

introduced. All techniques have their-self benefits. Off-chip jitter measurement

techniques base on external equipments. On-chip jitter measurement

techniques will introduce delay chain circuit, delay loop circuit, vernier delay

line circuit. With these existed techniques, readers would have a brief concept

in clock jitter measurement techniques.

In the chapter 4, the proposed circuit is introduced. The propose circuit used

new technique to measure the clock jitter. This new technique can reduce

chip area. In the proposed circuit, it only needs only one input, without extra

jitter-free clock.

In the chapter 5, the simulation and layout of chip will be introduced. The

approach of measuring chip and the result of the chip measurement will be

shown.

In the final chapter, some general conclusions from this work are presented.

4

Chapter 2 Preview Work

PLLs can be used in timing applications such as clock synthesis, clock

recovery, and clock skew compensation. In these applications, the most

important set of specifications for a PLL is its jitter characteristic [4]. In fact,

jitter specifications are critical in high speed interfaces because of a limit

available timing budget. Although jitter testing is expensive test because it

requires costly equipment and long test time [5]. Jitter testing is still a very

important in analyzing the circuit performance of PLL.

2.1 Jitter Definition

Jitter can be defined as the deviations in an output transition of clock from their

ideal positions. The deviations can be leading or lagging the ideal position.

Jitter is usually specified in positive or negative pico-seconds. Jitter

measurement can be classified into three categories: cycle-to-cycle jitter,

period jitter, and long-term jitter. All jitter measurements are at a specified

voltage, usually Vcc/2 [6].

2.1.1 Cycle-to-Cycle jitter

Cycle-to-cycle jitter is the change in a clocks output transition from its

corresponding position in the previous cycle. This form of jitter is the most

difficult to measure and require a Timing Interval Analyzer (TIA). Figure 2.1

depicts the graphical representation of cycle-to-cycle jitter. J1 and J2 are the

jitter values measured for single ends signals [6].

Figure 2.1 Cycle-to-cycle jitter

The maximum of such values measured over multiple cycles in the maximum

cycle-to-cycle jitter. Large cycle-to-cycle jitter can cause system to fail.

Consider the example shown in Figure2.2 where the output of PLL1 is the

reference of PLL2. If PLL2 cannot lock to the reference frequency, the

cycle-to-cycle jitter of the output of PLL1 may have exceeded the maximum

jitter allowable for PLL2 to lock. The cycle-to-cycle jitter of PLL1 must be low

enough for PLL2 to lock [6].

Figure 2.2 Application of cycle-to-cycle jitter

5

2.1.2 Period Jitter

Period jitter is the maximum change in a clocks output transition from its ideal

position. Figure 2.3 is a graphical representation of period jitter [7]. Period jitter

measurements are used to calculate timing margins in systems.

Figure 2.3 Period jitter

For example, a macro-processor-based system in which the processor

requires 2ns of a data set-up time [6]. Assume that the clock driving the

macro-processor-based system has a maximum of 2.5ns period jitter. In this

example, the rising edge of the clock can occur before the data is valid on the

data bus. The processor will be given incorrect data and the system will not

operate correctly. The example is shown in Figure 2.4. The system designer

must consider period jitter when calculating the timing margin of the system [6].

Figure 2.4 Application of period jitter measurement

6

2.1.3 Long-Term Jitter I

Long-term jitter measures the maximum change in a clocks output transition

from its ideal over a large number of cycles. Figure 2.5 is a graphical

representation of long-term jitter. The actual number of cycles depends on the

application and the clock frequency. For PC motherboards and graphics

applications, this is usually 10~20 microseconds. For other application, this

number will be different [6].

One example of a system affect by long-term jitter is a graphics card driving a

CRT. Assume that a pixel of data is specified for the pixel at coordinates (10,

24) on the CRT. Because of long-term jitter, this data may drive at the wrong

location (11, 28). Since the effect of a jittery clock is consistent over all pixels,

the overall effect of a jittery clock is to cause an image to shift from its ideal

display position on the screen. This effect is also known as running of the

screen. The long-term jitter is the time difference of the first rising edge and the

time delayed edge [6].

Figure 2.5 Long-term jitter I

7

2.1.4 Long-Term Jitter II

Long term, or tracking, jitter, which is measure of the phase variation between

PLLs input and output clocks, as shown in Figure 2.6. Tracking jitter

represents how closely the PLL output tracks the reference clock. This jitter is

important only in inter-chip communication, where synchronization must be

maintained [7].

Output clock of PLL

Lag

Ideal

Lead

Reference Clock

Jitter

Figure 2.6 Long-term (tracking) jitter II

2.2 Jitter Histogram

The variation of the clock jitter can be census to jitter histogram. The jitter is

random in the clock. The jitter histogram can shown the distribution of jitter. In

general, the jitter histogram will be shown in the Gaussian histogram without

other noise. See the Figure 2.7 [8].

When some noise brings to the clock jitter, the jitter histogram will be change. It

will be no longer in the Gaussian histogram. The noise may be the square,

triangle, and sinusoid waves. The different jitter histogram will be shown in

Figure 2.8, Figure 2.9, and Figure 2.10.

8

Figure 2.7 Jitter histogram

Figure 2.8 Jitter histogram II

Figure 2.9 Jitter histogram III

9

Figure 2.9 Jitter histogram IV

10

11

Chapter 3 Jitter Measurement Technology

Jitter measurement technology divided into two parts. One is off-chip jitter

measurement technology; it is depended on the test equipment, it is also called

equipment based techniques [9]. The other is on-chip jitter measurement, it

included delay chain techniques, delay loop techniques and vernier delay line

techniques. All these techniques have their-self benefits.

3.1 Off-chip Jitter Measurement

In high-speed circuit design, clock jitter measurements have become a very

important job in analyzing the circuit performance. From a users perspective,

there are four traditional ways of making jitter measurements.

Spectrum analyzer: From this measurement, the jitter is modeled as phase

noise of the signal. The power of the phase noise can be measured with high

frequency range

ATE: The signal is repeatedly acquired at slightly different time settings for the

capture strobe. With the distribution of signal timing, jitter can be easily

measured.

Real time sampling oscilloscope: The clock signal is over-sample at a fixed

voltage threshold. Special software can extract the jitter from the sample data.

12

Dedicated jitter instrumentation: The signal jitter is directly measured from

the dedicated jitter instrumentation. The measurement result is report as a

digital number. There are two main approaches in this way: one is based on

Time-Interval-analyzer (TIA) ; the other is based on counter-timer.

In these traditional ways, all jitter measurements rely on the external

equipment. This will cause some serious problem. The most obvious problem

is the loading problem. In making jitter measurements, the output signals of the

circuits have to connect many probes. These probes loading makes the

measured signal decrease or distort seriously. Therefore, the reported result

will be not the original data, but the fake data. Moreover, these traditional ways

also have some other problem, resolution, accuracy, test time, testable clock

speed, and so on. In order to reduce these problems effect, the built-in clock

jitter measurement method has been report [10]-[14]. In the clock jitter

measurement, the built-in clock jitter measurement method uses the Time to

Digital Converter (TDC) technique to deal with the analog clock signal. The

TDC technique is like the ADC technique. It can translate the analog signal into

all-digital clock signal. The translated digital signal makes the clock jitter

measurement become easier. Users can use general equipment, logic

analyzer, to measure the clock jitter directly. In the built-in clock jitter

measurement method, there are fewer measurement limitations than the

traditional ways.

3.2 On-chip Jitter Measurement

On chip jitter measurement can also called built-in clock jitter measurement

(BIJM). Using BIJM method, it can avoid many problems from outside testing

equipment. The BIJM method also has many properties as following.

13

1. Low cost on testing equipment: In recent year, the output frequency of

PLL is increasing, because of the improvement of semiconductor

technology. Therefore, it is difficult to measure the clock jitter of PLL by the

traditional testing equipment. Users must buy more high level testing

equipment and software that support testing equipment to measure jitter.

When using BIJM methods, users can measure clock jitter by general

testing equipment.

2. Low noise independent of test equipment: When the output frequency

of PLL is increasing, if the clock jitter measurement is still relying on the

external equipment, it will cause many problems. The most important

problem is loading problem, the output signal of circuit will connect many

probes. This probes may induce noise to signal, these may cause output

signal distort. The measurement result of output signal will be not correct.

Using BIJM circuits, the jitter measurement is measured in chip, the output

signal will not be effect by the external equipment. The BIJM circuits can

reduce the effect of noise to minimum, so the measurement result will be

more accuracy.

3. Full speed measurement: The measurement accuracy is according to the

sampling frequency of the testing equipment. When sampling frequency is

high, the measurement result is more accuracy. But the sapling frequency

has limitation. When measuring the clock jitter in the chip, users can

measure the jitter at full speed.

4. Suitable for SoC system: In high speed communication system, the

system will compose of many circuits, such as transceiver, receiver, and

PLL. When users only want to measure the clock jitter of PLL, it is difficult

to measure. Using BIJM circuits can solve this problem.

3.3 Operation of BIJM Circuits

BIJ

M

Ou t

p ut

Figure 3.1 Operation of BIJM circuits

Seeing Figure 3.1 that shown the operation of BIJM circuits.

First step: The output signal of PLL or DLL or VCO, which has jitter, feed into

the BIJM circuit. The BIJM circuit will produce a serious digital data.

Second step: The serious digital data feed into the logic analyzer, then the

logic analyzer will measure this digital data and transfer this data to computer

format file.

Third step: Using computer to deal with the digital data that is computer

format file. The digital data can be translated into jitter histogram by mathlab.

14

3.4 Traditional Methodology

In BIJM method, Time to Digital Converter (TDC) technique used to deal with

the clock signal. Figure 3.2 will introduce the traditional TDC methodology.

Figure 3.2 Traditional methodology

Seeing Figure 3.2, input clock pass through delay cell, then input clock

become delayed clock. When passing more and more delay cells, the first

rising edge of delayed clock can sample the second rising edge of input clock.

In this way, the delay time of delay cells had been known, the numbers of delay

cells that input clock passed had also been known, the period of clock can be

quantify as P=Td*N. Td is delay time of delay cells, N is the numbers of delay

cells that input clock pass through. In this example, the input clock passed

through six delay cells, then, the first rising edge of delayed clock can sample

the second rising edge of input clock. Therefore, P= Td*6. In TDC circuits, the

circuit resolution is the delay time of delay cells. In order to quantify the period

of clock more accuracy, the circuit resolution of TDC circuits must be improve.

15

In following sections, some of BIJM circuits will be introduce.

3.5 Delay Chain Circuit

In delay chain circuit, the main components are constant delay chain,

adjustable delay chain, D-type flip/flop, and error counter. See the Figure 3.3

Figure 3.3 Delay chain circuit

3.5.1 Operation of Delay Chain Circuit

At first, the output of PLL passed through the constant delay, the input of PLL

passed through adjustable delay chain. So the jittery clock will have a constant

delay time, them the delay time of input clock can control by the adjustable

delay chain. Figure 3.4 is shown the adjustable delay chain. In the adjustable

delay chain, the digital buffers are the delay cells, it can control the delay time.

When the binary counter is increasing is increasing, the delay time will also

increase. When the delay time of adjustable time delay is increasing, the input

clock of PLL can sample the output clock of PLL. As the rising edge of input

clock sample the rising edge of output clock, the numbers of delay cells of

delay chain will be known [10]. According to the number of delay cells, the

16

clock can be quantified.

Figure 3.4 Adjustable delay chain

3.5.2 Jitter Measurement of Delay Chain Circuit

In this circuit, if the output clock of PLL is no jitter, when the input clock pass

through the adjustable to sample the output clock, the counter signal will rise

up in the same delay cell stage. If the output clock of PLL has jitter, the counter

signal will rise up in different delay cells, because that the rising edge of output

will shift left or right.

Figure 3.5 Jitter measurement of delay chain circuit

17

18

3.5.3 Characteristic of Delay Chain Circuit

Low circuit resolution: Because that the circuit resolution is delay cells of

adjustable delay chain. The delay cells are digital buffers.

Measurement error: Because that the input clock may be have jitter, when

input clock used to sample output clock, the measurement result may be have

error.

Limitation of measurement: In this circuit, it only can measure the internal

and external input of PLL.

Real time testing: This circuit can process the clock continuously. The clock

can be measured one by one.

3.6 Delay Loop Circuit

The delay loop circuit composed of NOR gate , latches, counters, encoder, and

D-type flip/flops [14].

3.6.1 Operation of Delay Loop Circuit

See the Figure 3.6. In this circuit, the clock that wants to measure will treat as

the enable signal. The enable signal can trigger the latches. In the beginning,

all outputs of latches set on 0, the rst signal sets on 1, so that output of NOR

gate sets on 0. When the clock that wants to measure feed into the circuit, the

rst signal sets on 0, then output of NOR gate will change to 1, the 1 signal will

pass through all latches, when the last stage signal 1 return to the NOR gate,

the rst signal is still on 0, so the output change to 0, then the 0 signal will also

pass through all latches, then the 0 signal will return to the NOR gate, the

output signal of NOR gates will change to 1. In the way, the signal will loop in

this circuit until the enable signal disabled. The counter will count the numbers

of 1 and 0. The enable signal can be quantified by the signal that combine

counter signal and encoder signal.

Enable 11111100000011111100000011111100000

Counter

D Q

Latch

D Q

Latch

D Q

Latch

D Q

Latch

Encoder

Counter

DFFs

RST

Enable

Output

1

0

0 0 0 00

1

1 1 1 1 1

0

Figure 3.6 Operation of delay chain circuit

3.6.2 Jitter Measurement of Delay Chain Circuit

In this circuit, if the clock has no jitter, the output of the circuit will be the same.

If the clock has jitter, the output of the circuit will be different. Comparing the

different signal, the difference between the clock will be known. In this way, the

clock jitter can be measured.

3.6.3 Characteristic of Delay Chain Circuit

Low circuit resolution: In this circuit, the circuit resolution is determined by

the latches. The delay time of latches is long.

Low chip area: Because the circuit is used in the loop type, so that the

numbers of latches can be reduced, and the chip area alas can be reduced.

19

Limitation of measurement: Before measuring the jittery clock, the clock

must divide by 2. That, the clock signal can start the circuit.

Discrete time testing: Because that the circuit is loop circuit, so that the

circuit can only process one data once time. When the process of one data is

finished, then the next data will be process.

3.7 Vernier Delay Line Circuit

Vernier delay line circuit is composed of two different time of delay cells, D type

flip/flop, and counters. The basis concept of vernier delay line is to produce

high circuit resolution [13].

3.7.1 Operation of Vernier Delay Line Circuit

Figure 3.7 Operation of vernier delay line circuit

Seeing figure 3.7, it is shown that operation of vernier delay line circuit.

Previously, the circuit resolution of the BIJM circuit is only decided by one type

delay cells. Sometimes, inverter may be used to be a delay cell, although the

20

propagate delay of inverter is very small. If users want to quantify the period of

clock more accuracy, the delay time of inverter is still too big. In order to

achieve high circuit resolution, vernier delay line circuit was proposed. In

instead of one type delay cell, vernier delay circuit used two types of delay

cells that had different delay time. The high circuit resolution was produce by

the difference of two types of delay cells that have different time. Using high

circuit resolution, the period of clock can be quantified more accuracy. In this

circuit, the rising edge of signal B is used to sample the rising edge of signal A.

When the rising edge of signal B can sample the rising edge of signal A, signal

C and D will be rise up.

3.7.2 Jitter Measurement of Vernier Delay Line Circuit

In this circuit, when measuring the clock jitter, an extra jitter free clock is need;

it is feed into the clock side, the clock that users want to measure is feed into

the data side. See the Figure 3.8.

Jitter-less Data

Ideal Clock

N-1 Counter

N Counter

N+1 Counter

Jitter Data

Jitter

N-1 Counter

N Counter

N+1 Counter

1 2 3 1

2

3

Jitter are detected on Signal 2 and Signal 3

1 2 3

2

1 2

D QData

Clock

Counter

1 N M

1

Stage 1 Stage 2 Stage N Stage M

D1

C1

A1

B1

TA

TB

D Q

Counter

TA

TB

2

D Q

Counter

TA

TB

N

2

D Q

Counter

TA

TB

M

N M

Figure 3.8 Jitter measurement of vernier delay line circuit

21

22

If the data that users want to measure is jitter-less, when it feed into to the

circuit, the signal of counter will rise up in the same position. Because that the

second rising edge of data that users want to measure is always in the same

position. If the data that has jitter feed into the circuit. Because that the second

rising edge of the jittery data will shift right of left, when the extra no jitter clock

sample the jittery data, the counter signal will rise up in different positions.

Jitter is detected on signal 2 and signal 3.

3.7.3 Characteristic of Vernier Delay Line Circuit

High circuit resolution: The circuit resolution is created by the difference of

two different delay cells. The difference can be very small, so that the period of

clock can be quantify more accuracy.

Large chip area: In order to create high circuit resolution, the circuit needs

double delay cells. Therefore, the chip area is also increase. More higher

circuit resolution, more layout area is need.

Jitter-free clock is need: When measuring clock jitter, the jitter-free clock is

feed into the clock side.

Real time testing: This circuit can process the data continuously. The data

can be measured one by one.

Chapter 4 Proposed BIJM Circuit

In proposed BIJM circuit, the circuit is improving on vernier delay line circuit.

The characteristic of vernier delay line circuit is high circuit resolution but large

chip layout area, it also need a jitter free clock. So that in the proposed circuit,

it should be have high circuit resolution, low chip layout area, and the jitter free

clock is not need. The structure and operation of the circuit will be introduce in

this chapter.

4.1 Structure of the Proposed BIJM Circuit

One Period Delay

Jitter Measurement

Figure 4.1 Structure of the proposed BIJM circuit

The structure of the proposed BIJM circuit is shown in Figure 4.1. The

proposed circuit has three components. There are one-period-delay circuit,

jitter-measurement circuit, and control logic circuit. When the circuit measured

the clock jitter, first, the circuit needs only one input, the output signal of PLL or

DLL or other circuits feed in the BIJM circuit, then the one-period-delay circuit

will produce two outputs. This two outputs will feed in the jitter-measurement

23

circuit, the control logic circuit will control the jitter-measurement circuit to

measure clock jitter. The measurement result will be show in the BIJMoutput. In

the propose BIJM circuit, the one-period-delay circuit is used to reduce the

whole chip area , the jitter-measurement circuit has high circuit resolution, so

that the jitter-measurement circuit can measure the clock jitter more accuracy.

4.2 Proposed Methodology

The proposed methodology can achieve reduce chip layout area. Proposed

methodology use a new way to quantify the period of clock.

TOTOTO TP TPScale TP

CLKin

TP = TN - TNP

Ti

0 1 2 3 Q

M0 5 10

One Period Delay Jitter Measurement

CLKin TNP TNPTN TN

1th 2th

TNPTN

Qth

MthTOTOTO

1st 2nd Nth

TO TO TO TP...

Figure 4.2 Propose methodology

The new methodology is that using two circuit resolutions to quantify the

period of the clock. Before the second edge of clock, low circuit resolution to

quantify the clock. When closing to the second rising edge, high circuit

resolution to quantify the clock. In this way, users can quantify the clock more

quickly and accurately. Because that traditional way always using the same

circuit resolution, when using low circuit resolution, clock can be quantify

24

quickly but not accuracy, when using high circuit resolution, clock can be

quantify accuracy but slowly. The new methodology used two circuit

resolutions that can achieve accuracy and quick. In one-period-delay circuit,

the circuit resolution is low and the circuit can delay the clock almost one

clock. In jitter-measurement circuit, the circuit resolution is high and the clock

can measure the clock jitter. In following sections, these two circuits will be

introduced.

4.3 One-period-delay Circuit

In this section, the structure, detail components, and operation of the circuit will

be introduced.

4.3.1 Structure of One-period-delay Circuit

Figure 4.3 Structure of One-period-delay circuit

This circuit composed of adjustable delay cells, AND gates, OR gates and

D- type flip/flops. The adjustable delay cells can control by the Ctrl signal, so

that the delay cells have two mode delay time. When Ctrl=0, delay time of

25

delay cells is TON+TO. When Ctrl=1, delay time of cells is TON. In the circuit,

Ctrl signals of the upward delay cells are always set on 1, so that the delay

time of the delay cells is TON. The Ctrl signals of the downward delay cells

are changeable. The D-type flip/flops are used to determine that whether the

CLKD+OPD outstrip one period than CLKD+IN. If the CLKD+OPD outstrip one

period than CLKD+IN, the Ctrl signals of the delay cells will be set on 1.

4.3.2 Operation of One-period-delay Circuit

In the circuit, at beginning, all Ctrl signals of downward of delay cells are set

on 0 and all Ctrl signals of upward of delay cells are set on 1. So that the

stage dealt time is TON+TO-TON=TO. In this way, the CLKD+OPD can delay TO

more than CLKD+IN in every stage. When CLKD+OPD delay almost one period

of the clock than CLKD+IN, the d-type flip/flop will detect, then, the Ctrl signals

of downward delay cells will be change on 1. In this way, the stage delay

Figure 4.4 Operation of One-period-delay circuit

time will be change to TO-TO=0. Therefore the difference of delay time

26

between the CLKD+OPD and CLKD+IN is the same until the signal pass through

all delay cells. Seeing Figure 4.4, it is shown the whole process.

4.3.3 Design of One-period-delay Circuit

In one-period-delay circuit, the circuit compose of D-type flip/flop, AND

gates, OR gates and adjustable delay cells. The D-type flip/flop was design

in TSPC circuit. The OR and AND gates was design in static circuit. Seeing

Figure 4.5, it was shown the design of adjustable delay cells.

Figure 4.5 Design of adjustable delay cell

In this circuit, M1, M2, M3, M4 can be treated as current source. M1 and M2

are always turning on, M3 and M4 is control by the Ctrl signal. The size of

M3 and M4 is bigger than that of M1 and M2. When Ctrl signal is set on 1,

M3 and M4 are turn on, the current of M3 and M4 is bigger than that of M1

and M2, therefore, the delay time of the delay cell will be decrease. When

there are only M1 and M2 turn on, the delay time of delay cell will longer

than that M3 and M4 turn on.

27

4.4 Jitter-measurement Circuit

In this section, the structure, detail components, and operation of the circuit will

be introduced.

4.4.1 Structure of Jitter-measurement Circuit

CLKD+OPD

CLKD+INVSS

buffer

buffer

D Q

BISToutputCLKtest

Control Logic

10

0

MOS1

MOS1

10

0

MOS2

MOS2

10

0

MOSN

MOSN

buffer

buffer

10

0

MOSM

MOSM

1 2 N M

Figure 4.6 Structure of jitter-measurement circuit

Seeing Figure 4.6, it is shown that the structure of jitter-measurement circuit.

This circuit composed of MOS capacitances and D-type flip/flop. The output

signal s of one-period-delay circuit will feed into the jitter-measurement circuit.

In the circuit, MOS capacitances are used to be the delay cells. Using MOS

capacitances can create high circuit resolution than using logic gates. In this

way, the circuit can quantify the clock more accuracy. The high circuit

resolution is produced by the difference of MOS capacitances turn on and off.

In the circuit, the upward MOS capacitances are always turning off; the

downward capacitances are controlled by the control logic circuit. The CLKtest

can control the control logic circuit that the signals of control logic rise up one

by one.

28

4.4.2 Operation of Jitter-measurement Circuit

In this circuit, the way of jitter-measurement works as the vernier delay line

circuit. See the Figure 4.7. At the beginning, the rising edge of CLKD+IN and the

rising of CLKD+OPD is very closing. With increasing the control signal, the

difference between the rising edge of CLKD+IN and CLKD+OPD will decrease.

When the rising edge of CLKD+OPD had sampled the rising edge of CLKD+IN, the

output signal of D-type flip/flop will rise up. According to the numbers of control

signals, the clock can be quantified. When measuring the jittery clock, because

that the rising edge of jittery clock will shift right or left, so that, the numbers of

control signal will be different.

Ti Ti-TF

1st Control signal ON

Ti-2*TF

1st 2nd Control signal ON

Ti-N*TF

1st 2nd Nth Control signal

ON

CLKD+IN

CLKD+OPD

Control Signal

BISTOutput

Figure 4.7 Operation of jitter-measurement circuit

4.4.3 Design of Jitter-measurement Circuit

The circuit is composed of MOS capacitances, control login circuit, D-type

flip/flop. The control logic circuit will be introduced in next section. The D-type

flip/flop is design in TSPC circuit. The MOS capacitances are the most

important design in the circuit. According to the property of MOS capacitances,

the very small delay time is created. See the Figure 4.8. When control the

voltage of the gate side of the MOS capacitance, the control voltage is high,

the MOS capacitance is lager, the control voltage is low, and MOS capacitance

is small. The MOS capacitance is very stable. When the MOS capacitance is

29

large, it will take long time to charge. So that, the delay time will increase. In

this way, the difference of the MOS capacitances turn on and off will be created

easily.

Figure 4.8 MOS capacitance

4.4.4 Control Logic Circuit

The control logic circuit is composed of D-type flip/flops, seeing the Figure 4.9.

Figure 4.9 Control logic circuit

Before the last D-type flip/flop, the output Q of D-type flip/flop is always

connect to the next input D of the next D-type flip/flop. In the last D-type

30

31

flip/flop, the output of the Qbar will connect to the input D of the first D-type

flip/flop. In the beginning, all the D-type flip/flops should be reset. Then the

output Qbar of the last D-type will be set to high. When control clock start the

circuit, the control signals will rise up one by one. So that, the control logic

circuit can control the jitter-measurement circuit.

4.5 Operating Principle

Data flow of self-sampled vernier delay line (VDL) structure is divided into

two steps. First step is one-period-delay and second step is jitter-measurement.

TOPD is the timing difference between CLKD+IN and CLKD+OPD of

one-period-delay (OPD) block. TJ is the timing delay used to control the sample

window of jitter-measurement (JM) block. M is the number of processed input

clock period, and X is the upper limit number for M. N is the controlled delay

stage number for TJ, and C is counted number for the sample window of TJ.

Furthermore, TO and TF are timing units in OPD block and JM block. And, TP is

the period of each clock cycle.

When input clock is fed into the self-sampled VDL structure in first step, TOPD

is set to zero initially. Then, TOPD starts to increase with the fixed timing delay

TO continuously to produce internal signals, CLKD+IN and CLKD+OPD. When TOPD

is larger than TP, TOPD is forced to decrease with one fixed timing delay

conversely. At this time, TOPD is smaller than TP again, but TOPD has

approached to TP. Therefore, the first rising edge of CLKD+OPD signal will leads

before the second rising edge of the CLKD+IN signal. And, the timing difference,

TOPD, between CLKD+IN and CLKD+OPD is approached to one-period-delay time

in first step.

In second step, sample window, TJ, is defined by delay stage number, N, in

the beginning. And, the timing difference between CLKD+IN and CLKD+OPD is

extended to TOPD plus TJ. Then, the jittery clock period TP is compared with the

system defined timing difference TOPD plus TJ .And the comparison result is

stored in the counter value, C, in JM block. At this moment, the number of

processed input clock period, M, is increased. And, its compared with the

system defined upper limit number of processed input clock period, X

continuously until M is larger than X. In the end, the measurement result is

translated into the hit number, C divided by X, in JM block to generate the

cumulative distribution function (CDF) of input clock jitter.

Figure 4.10 Operating principle

32

33

Chapter 5 Chip implementation

The simulation result, layout of the chip, chip measurement is shown in this

section. Figure 5.1 is the design procedure.

Reference Material

Circuit Structure Specification

Draw Schematic Decide Size of MOS

Netlist CDL out

Pre-Simulation

Timing & Cost fit specification

Layout

DRCDesign Rules

Checking

LVSLayout versus

Schematic

Post Simulation

Timing, Cost, Area fit specification

Put PAD in Layout

DRC & LVS

Output GDS File IC fabricate

IC Measurement

Figure 5.1 Design procedure

5.1 Simulation of the proposed circuit

The circuit is design for measuring clock frequency from 100MHz to 400MHz.

The circuit resolution of jitter-measurement circuit is 15ps. The circuit is design

in TSMC 0.35um 2P4M CMOS process.

34

5.1.1 Consideration of Simulation

When the chip was fabricated, it has inductances on its bounding pads. When

chip working, the inductances will cause the ground bounce effect. The ground

bounce effect can induce noise into the power line and ground line, so that the

chip function may fail or the performance will decrease. Therefore, in the

simulation, the ground bounce is also simulated. See Figure 5.2. In the power

land ground line, there are 3nH inductances.

Figure 5.2 Simulation consideration

5.1.2 Simulation of One-period-delay Circuit

In this circuit, the circuit resolution is design in 320ps. In other words, TO is

320ps in a stage. Because that the input frequency is 100MHz from 400MHz,

in order to measure 100 MHz frequency, the circuit must almost delay 10000ns.

35

In this way, the circuit needs 10000/32031 stages at least. Considering of

process variation, see Figure 5.3. When delay cells work on FF mode, the

circuit resolution TO is 250ps, so that the circuit designed in 40 stages.

Figure 5.3 Simulation of circuit resolution in one period circuit

5.1.3 Simulation of Jitter-measurement Circuit

In this circuit, the circuit resolution designed in 15ps in a stage. The total delay

time of all stages is double of the circuit resolution of one-period-delay circuit.

So, the circuit resolution of one-period-delay circuit is 300ps, and the numbers

36

of stage in jitter-measurement circuit is 40(300*2/15=40). Figure 5.4 is shown

the process variation of circuit resolution in jitter-measurement.

Figure 5.4 Simulation of circuit resolution in jitter-measurement circuit

5.1.4 Simulation of Control Logic Circuit

The control clock can control the control signals rise up. It can control how long

the control signals rise up. In this design, the clock pass through 16 times clock,

then the next control signal will rise up. See Figure 5.5

37

Figure 5.5 Simulation of control logic circuit

5.2 Layout of the Proposed Circuit

In the Figure 5.6, it is the photograph of whole chip layout. The layout block of

whole chip is shown in Figure 5.7. In this chip, it included the proposed BIJM

circuit and the PLL circuit. The chip area of the proposed BIJM circuit is

38

500um*750um.

Figure 5.6 Photograph of whole chip

Figure 5.7 Layout block of whole chip

5.3 Measurement Result

5.3.1 Concept of Measurement

In order to measure the chip, the measure signal is created from the pulse

generator, because that the signal is not really ideal, so it will have jitter. So

39

that the signal feed into the BIJM circuit, the circuit can measure the signal.

Then the output of BIJM will be measured by the logic analyze. The output

signal of BIJM circuit will be process by computer, then, the jitter histogram will

be created by computer.

Figure 5.8 concept of measurement

5.3.2 Chip Measurement

The setup of measurement in the chip is shown in Figure 5.9. The power is

provided by the Agilent E3646A. The input signal is created from Agilent

81334A, and HP 33120A pulse generator provided different noise into Agilent

81334A, so that the signal will have different jitter histogram. In this way, the

chip can measure differ histogram.

40

Agilent E3646APower Supply

Agilent 81134APulse Generator

HP 33120APulse Generator

Hp 16702ALogic Analysis system

Figure 5.9 Measurement setup of the chip

5.3.3 Measurement Result

In order to measure the chip, the input signal is induced noise. In this way,

the chip can measure the signal. In Figure 5.10, the input signal is 100MHz

that mixed with the random noise, so that the signal has jitter that is 214ps

(peak to peak). In the Figure 5.11, it is the result that measured from the BIJM

circuit. In the measurement result, the jitter (peak to peak) is 17*15ps=255ps.

In Figure 5.12, the input signal is 100MHz that is mixed with the square signal

that is 100KHz , 300mVolt. In the Figure 5.13, it is the result that measured

from the BIJM circuit. In the measurement result, the jitter (peak to peak) is

18*15ps=270ps.

41

Figure 5.10 100MHz signal mixed with random signal

150

350

550

750

950

1150

1350

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28Stage number

Hit number

Figure 5.11 Measurement result of proposed circuit I

42

Figure 5.10 100MHz signal mixed with square noise

0

200

400

600

800

1000

1200

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32Stage number

Hit number

Figure 5.11 Measurement result of proposed circuit II

43

44

5.3.4 Specification of Circuit

Technology TSMC352P4M

Power Supply 3.3V

Input Frequency 100MHz~400MHz

Jitter Resolution 15ps

Jitter Range 15ps~330ps

Power Dissipation 29mw(at 100MHz)

Measurement VS. BIJM 210ps(peak-peak) VS.

255ps(peak-peak)

Table 5.1 Specification of BIJM circuit

Reference Logic Vision [12] G. W.

Robers[13] G. W. Robers[15]

Propose Cirucit

Technology 0.6um 0.35um 0.18um 0.35um Resolution(ps) 40ps 118ps 18,9ps 15ps Area (gate) 3000~6000(gates) 5.5mm2 0.12mm2 0.375mm2

Technique Delay Chain Vernier Delay

Vernier Delay

Vernier Delay

Table 5.2 Comparison of BIJM circuit

45

Chapter 6 Conclusion and Future Work

6.1 Conclusion

In this work the circuit for clock jitter-measurement is proposed. The proposed

circuit is divided into two structures. One is one-period-delay circuit; the other

is jitter-measurement circuit. In one-period-delay circuit, the circuit can reduce

the chip area. In jitter-measurement circuit, the circuit has high circuit

resolution, in order to measure the clock jitter accurately. The testing frequency

of the proposed circuit is 100HMz to 400MHz. The circuit resolution is 15ps.

The circuit is fabricated in TSMC 0.35um 1P4M CMOS process. The chip area

of the proposed circuit is 500umx750um. The power consumption is 29mw.

6.2 Future Work

The circuit resolution must be improve, because the frequency of PLL will

increase. The most important factor of circuit resolution is the noise. Because

that the circuit resolution will smaller than 10ps, so that, when there is noise in

the circuit, the circuit resolution will be interfere with the noise. The circuit must

resist the noise. The D-type flip/flop is the circuit is used to determine the jitter.

But the D-type flip/flop has setup time and hold time, those factors will affect

that determine the jitter. So the design of D-type flip/flops can be improve.

46

Reference material

[1] C.C. Tsai, On-Chip jitter measurement for phase-locked loop. MSc. Thesis,

National Chiao Tung University, Taiwan, 2002.

[2] M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, K. K. Gullapalli,

and B. J.Mulvaney, A new approach for computation of timing jitter in phase locked

loop, Proc.of Design, Automation and Test in Europe and Exhibition 2000, pp.

345-349, 2000.

[3] F. Azais, M. Renovell, Y. Bertrand, A. Ivanova, and S. Tabatabaei, A unified

digital test technique for PLLs: catastrophic faults covered, Proc. of Int. Mixed

Signal Testing Workshop, pp. 269-292, June 1999.

[4] Bell Research Laboratories, SONET transport systems: Common criteria network

element architecture features, GR-253-core, Issue 1, pp. 5-81, Dec. 1994.

[5] W. Dalal and D. Rosenthal, Measuring jitter of high speed data channels using

under-sampling technique, Proc. of Int. Test Conf., pp. 814-818, 1998.

[6] Nelson Soo, Jitter measurement techniques, Pericom Application Brief AB36,

Nov.2000.

[7] K. A. Jenkins and J. P. Eckhardt, Measuring jitter phase error in microprocessor

phase-locked loop, IEEE Design & Test of computers, vol.17, pp. 86-93, Apr-Jun

2000.

[9] Bozena Kaminska, BIST means more measurement options for designers, EDN

Magazine, Dec. 2000.

[10] M. Frisch Arnold and H. Thomas Rinderknecht, Jitter Measurement System and

Method. US Patent # 6,295,315 assigned to Frisch, et al. Sep. 2001.

47

[11] S. Tabatabaei and A. Ivanov, Embedded timing analysis: A SoC infrastructure

IEEEDesign & Test of Computers, vol. 19, pp. 22-34, May-June 2002.

[12] S. Stephen and R. Audin, BIST for Phase-Locked Loops in Digital

Applications Proc.

of Int. Test Conf., pp. 532-540, Sep 1999.

[13] A. H. Chan and G.W. Roberts, A synthesizable, fast and high-resolution timing

measurement device using a component-invariant vernier delay line Proc. of Int. Test

Conf., pp. 858-867, Nov 2001.

[14] T. Lin, K. L. Luo, Y. J. Chang and W.C. Wu, A testable design of on-chip jitter

measurement, VLSI Design/CAD Symposium, Taidong, Taiwan, Aug 2002, pages

182-185

[15] Antonio H. Chan and Gordon W. Roberts, A Jitter Characterization System Using a

Component-Invariant Vernier Delay Line Very Large Scale Integration (VLSI)

Systems, IEEE Transactions on Volume 12, Issue 1, Jan. 2004 Page(s):79 - 95

.pdf93ncu_au(digital).pdf.pdfTable 5.2 Comparison of BIJM circuit.44List of FigureChapter 1 Introduction1.1 Motivation1.2 Organization of Thesis

Chapter 2 Preview Work2.1 Jitter Definition2.1.1 Cycle-to-Cycle jitter2.1.2 Period Jitter2.1.3 Long-Term Jitter I2.1.4 Long-Term Jitter II

2.2 Jitter Histogram

Chapter 3 Jitter Measurement Technology3.1 Off-chip Jitter Measurement3.2 On-chip Jitter Measurement3.3 Operation of BIJM Circuits3.4 Traditional Methodology3.5 Delay Chain Circuit3.5.1 Operation of Delay Chain Circuit3.5.2 Jitter Measurement of Delay Chain Circuit3.5.3 Characteristic of Delay Chain Circuit

3.6 Delay Loop Circuit3.6.1 Operation of Delay Loop Circuit3.6.2 Jitter Measurement of Delay Chain Circuit3.6.3 Characteristic of Delay Chain Circuit3.7 Vernier Delay Line Circuit3.7.1 Operation of Vernier Delay Line Circuit3.7.2 Jitter Measurement of Vernier Delay Line Circuit3.7.3 Characteristic of Vernier Delay Line Circuit

Chapter 4 Proposed BIJM Circuit4.1 Structure of the Proposed BIJM Circuit4.2 Proposed Methodology4.3 One-period-delay Circuit4.3.1 Structure of One-period-delay Circuit4.3.2 Operation of One-period-delay Circuit4.3.3 Design of One-period-delay Circuit

4.4 Jitter-measurement Circuit4.4.1 Structure of Jitter-measurement Circuit4.4.2 Operation of Jitter-measurement Circuit4.4.3 Design of Jitter-measurement Circuit4.4.4 Control Logic Circuit

4.5 Operating Principle

Chapter 5 Chip implementation5.1 Simulation of the proposed circuit5.1.1 Consideration of Simulation5.1.2 Simulation of One-period-delay Circuit5.1.3 Simulation of Jitter-measurement Circuit5.1.4 Simulation of Control Logic Circuit

5.2 Layout of the Proposed Circuit5.3 Measurement Result5.3.1 Concept of Measurement5.3.2 Chip Measurement5.3.3 Measurement Result5.3.4 Specification of Circuit

Chapter 6 Conclusion and Future Work6.1 Conclusion6.2 Future Work

Reference material