Embed Size (px)
Citation preview
Department of Science and Technology Institutionen för teknik och naturvetenskap Linköpings Universitet Linköpings Universitet SE-601 74 Norrköping, Sweden 601 74 Norrköping
ExamensarbeteLITH-ITN-ED-EX--06/019--SE
A MMIC GaAs up-converter from350 MHz to 1835 MHz realized both
in a HBT diode-mixer topologyand pHEMT resistive FET-mixer
topologyAnders Andersson
Joakim Östh
2006-05-24
LITH-ITN-ED-EX--06/019--SE
A MMIC GaAs up-converter from350 MHz to 1835 MHz realized both
in a HBT diode-mixer topologyand pHEMT resistive FET-mixer
topologyExamensarbete utfört i Elektronikdesign
vid Linköpings Tekniska Högskola, CampusNorrköping
Anders AnderssonJoakim Östh
Handledare Per GustafsonHandledare Martin Johansson
Examinator Adriana Serban Craciunescu
Norrköping 2006-05-24
RapporttypReport category
Examensarbete B-uppsats C-uppsats D-uppsats
_ ________________
SpråkLanguage
Svenska/Swedish Engelska/English
_ ________________
TitelTitle
FörfattareAuthor
SammanfattningAbstract
ISBN_____________________________________________________ISRN_________________________________________________________________Serietitel och serienummer ISSNTitle of series, numbering ___________________________________
NyckelordKeyword
DatumDate
URL för elektronisk version
Avdelning, InstitutionDivision, Department
Institutionen för teknik och naturvetenskap
Department of Science and Technology
2006-05-24
x
x
LITH-ITN-ED-EX--06/019--SE
A MMIC GaAs up-converter from 350 MHz to 1835 MHz realized both in a HBT diode-mixer topologyand pHEMT resistive FET-mixer topology
Anders Andersson, Joakim Östh
Two mixers for up-conversion from an IF frequency of 350 MHz to a RF frequency of 1835 MHz havebeen designed and simulated to be used in Ericsson�s radio link system MINI-LINK. One mixer usesdiodes in a balanced structure, and the other one use resistive FET-mixers, also in a balanced structure.Both implemented in a GaAs MMIC process; for the diode mixer TriQuint HBT2 and for the resistiveFET-mixer TriQuint 0.25 um pHEMT. The mixers were designed to work with input LO-power of 0dBm and an IF-power of -20 dBm. For the diode based mixer with an active LO balun the conversiongain is 5.7 dB, P-1dB 15 dBm and the LO-suppression -22 dB. For the resistive FET-mixer theconversion gain is 11 dB, IIP3 26 dBm, P-1dB 15 dBm and the LO-suppression -49 dB. The data givenis based on simulations; no wafers have been processed at this time. The chip-area the final design willoccupy is approximated to 1.8 mm^2 for the diode mixer and approximately 1.9 mm^2 for the resistiveFET-mixer. For both of the mixer types an off-chip balun for the IF-frequency is the only externalcomponent needed.
MMIC, up-converter, GaAs, mixer, linearity, HBT, HEMT, LO-suppression
Upphovsrätt
Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare –under en längre tid från publiceringsdatum under förutsättning att inga extra-ordinära omständigheter uppstår.
Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner,skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat förickekommersiell forskning och för undervisning. Överföring av upphovsrättenvid en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning avdokumentet kräver upphovsmannens medgivande. För att garantera äktheten,säkerheten och tillgängligheten finns det lösningar av teknisk och administrativart.
Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman iden omfattning som god sed kräver vid användning av dokumentet på ovanbeskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådanform eller i sådant sammanhang som är kränkande för upphovsmannens litteräraeller konstnärliga anseende eller egenart.
För ytterligare information om Linköping University Electronic Press seförlagets hemsida http://www.ep.liu.se/
Copyright
The publishers will keep this document online on the Internet - or its possiblereplacement - for a considerable time from the date of publication barringexceptional circumstances.
The online availability of the document implies a permanent permission foranyone to read, to download, to print out single copies for your own use and touse it unchanged for any non-commercial research and educational purpose.Subsequent transfers of copyright cannot revoke this permission. All other usesof the document are conditional on the consent of the copyright owner. Thepublisher has taken technical and administrative measures to assure authenticity,security and accessibility.
According to intellectual property law the author has the right to bementioned when his/her work is accessed as described above and to be protectedagainst infringement.
For additional information about the Linköping University Electronic Pressand its procedures for publication and for assurance of document integrity,please refer to its WWW home page: http://www.ep.liu.se/
© Anders Andersson, Joakim Östh
A MMIC GaAs up-converter from 350 MHz to 1835 MHz realized both in a HBT diode-mixer topology
and pHEMT resistive FET-mixer topology
Master Thesis by
Anders Andersson and Joakim Östh 2006
Department of Science and Technology Linköping Institute of Technology
Norrköping
ii
Abstract
Two mixers for up-conversion from an IF frequency of 350 MHz to a RF frequency of 1835 MHz have been designed and simulated to be used in Ericsson’s radio link system MINI-LINK. One mixer uses diodes in a balanced structure, and the other one use resistive FET-mixers, also in a balanced structure. Both implemented in a GaAs MMIC process; for the diode mixer TriQuint HBT2 and for the resistive FET-mixer TriQuint 0.25 um pHEMT. The mixers were designed to work with input LO-power of 0 dBm and an IF-power of -20 dBm. For the diode based mixer with an active LO balun the conversion gain is 5.7 dB, P-1dB 15 dBm and the LO-suppression -22 dB. For the resistive FET-mixer the conversion gain is 11 dB, IIP3 26 dBm, P-1dB 15 dBm and the LO-suppression -49 dB. The data given is based on simulations; no wafers have been processed at this time. The chip-area the final design will occupy is approximated to 1.8 2mm for the diode mixer and approximately 1.9 2mm for the resistive FET-mixer. For both of the mixer types an off-chip balun for the IF-frequency is the only external component needed.
iii
Contents 1 Introduction ............................................................................................1 2 Theory .....................................................................................................2
2.1 Semiconductor devices ..............................................................3 2.1.1 HBT ............................................................................................3 2.1.2 HEMT .........................................................................................4 2.1.3 Schottky diode............................................................................4 2.2 Mixer basics ...............................................................................5 2.2.1 General non-linear analysis .......................................................5 2.2.2 Restricted analysis: the conversion matrix method..................11 2.2.3 Mixer parameters .....................................................................12 2.3 General non-linear phenomena ...............................................14 2.3.1 Gain Compression ...................................................................15 2.3.2 Desensitization and Blocking ...................................................15 2.3.3 Cross Modulation .....................................................................16 2.3.4 Intermodulation ........................................................................16 2.4 Resistive FET-mixer.................................................................18 2.5 Balanced diode mixers.............................................................22 2.5.1 Single-balanced diode mixer....................................................22 2.5.2 Double-balanced diode mixers.................................................26
3 Requirements .......................................................................................30 4 Design ...................................................................................................31
4.1 Diode mixer ..............................................................................31 4.1.1 Mixer core ................................................................................31 4.1.2 Baluns ......................................................................................35 4.1.3 RF power amplifier ...................................................................41 4.1.4 IF-balun ....................................................................................42 4.1.5 The complete up-converter ......................................................42 4.2 FET-mixer ................................................................................44 4.2.1 FET-mixer core ........................................................................44 4.2.2 Active balun..............................................................................48 4.2.3 Passive balun...........................................................................50 4.2.4 RF power amplifier ...................................................................50 4.2.5 The complete up-converter ......................................................53
5 Results ..................................................................................................54 5.1 Diode mixer ..............................................................................54 5.1.1 Active LO-balun........................................................................54 5.1.2 Passive LO-balun.....................................................................57 5.1.3 LO amplifier..............................................................................61 5.1.4 RF power amplifier ...................................................................62 5.1.5 The complete up-converter ......................................................63 5.2 FET mixer.................................................................................68 5.2.1 LO balun...................................................................................68 5.2.2 RF amplifier..............................................................................71 5.2.3 The complete up-converter ......................................................73
6 Layout and chip area ...........................................................................76 6.1 Diode mixer ..............................................................................76 6.1.1 Active LO-balun........................................................................76 6.1.2 LO-amplifier..............................................................................77 6.1.3 Passive LO-balun.....................................................................78 6.1.4 LO-filter ....................................................................................79
iv
6.1.5 RF-amplifier..............................................................................79 6.1.6 An estimation of the complete chip-area..................................80 6.2 FET mixer.................................................................................81 6.2.1 Layout of the mixer core...........................................................81 6.2.2 Layout of the active LO balun ..................................................82 6.2.3 Layout of the output RF amplifier .............................................83 6.2.4 Layout of the whole up-converter.............................................83
7 Conclusion............................................................................................84 8 Acknowledgements .............................................................................85 9 References............................................................................................86 Appendix A ....................................................................................................90
Additional design: adaptive bias circuit ..................................................90 Layout 91
Appendix B ....................................................................................................93 Workbenches .........................................................................................93
Appendix C ....................................................................................................97 Maple calculation 1 ................................................................................97 Maple calculation 2 ................................................................................98 Maple calculation 3 ................................................................................99 Maple calculation 4 ..............................................................................101 Maple calculation 5 ..............................................................................102
1
1 Introduction
The purpose of this work is to investigate if it is possible to make an up-converter in MMIC technology that fulfills the performance requirements, and at the same time, is cheaper than the solution used by Ericsson today. All work has taken place at Ericsson AB in Mölndal using Agilent ADS for design and simulation.
In today’s solution an expensive filter is needed after the mixer to suppress the LO-signal, therefore it is highly desirable to suppress the LO-signal already in the mixer so that a cheaper filter can be used.
The most demanding requirements were
1 high linearity
2 good LO-suppression
It turned out that a resistive pHEMT FET-mixer and a HBT diode mixer are good candidates to requirement one, due to their inherent good linearity. To meet requirement two, a balanced topology is selected, that theoretical can suppress the LO to infinity.
The work was basically divided in four parts: literature study, design, simulations and tuning, and finally the layout was made to estimate the chip area needed to manufacture the mixer.
The report is divided in sections in an attempt to make it easy for the reader to find the information he or she finds interesting. The reader that is familiar with basic mixer theory can with advantage skip the section dealing with basic mixer theory. The design and result chapters are also divided in different sections, one for each mixer type to make it easy to find the relevant information.
The reader mainly interested in the performance is directed to the results section, and especially to the summaries there.
2
2 Abbreviatoins and vocabulary
Agilent ADS – The company Agilents Avanced Design System, a computer aided electronics design program.
Balun – A baluns task is to convert an balanced signal to an unbalanced signal (and also conversely). A hybrid is often used as a balun.
DB – Duble balanced.
GB (GD) – Gain balance (Gain difference)
HB – Harmonic balance.
HBT – Heterojunction bipolar transistor.
HBT2 – A TriQuint specific HBT process.
HEMT – High Electron Mobility Transistor
IF – Intermediate Frequency
IM – InterModulation
IP3 (IIP3) – Interception Point Three, i.e third order interception point. IIP3 represents Input IP3.
LO – Local Oscillator.
LSSP – Large Signal S-Parameters, this refers to the ADS simulation controller.
MINI-LINK – Ericsson’s radio link system.
P-1dB – Power of the 1-dB compression point.
PB (PD) – Phase Balance (Phase differance)
RF – Radio Frequency.
SB – Single Balanced.
SP – S-parameter (scattering parameter).
TOI – Third Order Interception.
TriQuint – An American semiconductor company.
XDB – X DeciBell i.e this refers to the X:th order compression point simulaiton controller.
3
3 Theory
3.1 Semiconductor devices
In this thesis three types of semiconductor devices have been used, namely bipolar transistors, FET transistors and diodes. Regarding the transistors it is the improved and modern Heterojunction Bipolar Transistor (HBT) and High Electron Mobility Transistor (HEMT)1 that have been used. The diodes used are Schottky diodes. Since these improved devices differ slightly from the traditional (BJT, FET and PN-diode), regarding performance and manufacturing, each of them will be described briefly in the subsections below [1] [2].
3.1.1 HBT
In order to increase the speed of a regular BJT the doping of the base could be increased. This comes, unfortunately, with the drawback of decreased current gain. There are also physical limitations; the semiconductor cannot be doped to that great extent that is sometimes wanted. Therefore, an additional material is added to the emitter and, thus, forming a heterojunction2. If the additional material added is a material that easily releases electrons (for example Al or In) the consequence will be that more electrons are injected into the base from the emitter; and this without excessive doping. As a result this will create a much faster device than the regular BJT.
Today there are mainly two versions of the HBT. They are the so called AlGaAs/GaAs HBT and InGaP/GaAs HBT. The latter, so called 2nd generation HBT, is the one used in TriQuints HBT2 process, which also is the one used in this thesis work. This is said to perform better and be more reliable than the 1st generation.
The key features of the HBT are:
• High linearity
• High power gain
• Low cost
• Relatively high operating frequency
• Low noise
1 Also known as modulation-doped FET (MODFET). 2 Hetero, from Greek, means different or dissimilar.
4
3.1.2 HEMT
The HEMT or, High Electron Mobility Transistor, is basically constructed as an ordinary FET besides that, similar to HBT, bandgap engineering technologies have been utilized to increase the performance and creating a channel with low losses. In the HEMT a 2D electron gas is responsible for the carrier transport, this electron gas have a very large electron density and a high mobility and this is the main reason for the special features of the HEMT, the interested reader is recommended to read chapter 7 in reference [4]. In this work a special version of the HEMT has been used, instead of using additional materials with matching crystal lattices (for instance GaAlAs/GaAs) non-matching materials have been used (for instance InGaAs/GaAs). These HEMTs are called pseudomorphic HEMT or pHEMT. The reason that the pHEMT is used is that there was no HEMT device available in the design library used.
The key features of HEMT are:
• High linearity
• Very high cut-off frequency (at least 500 GHz have been reported)
• Very low noise
3.1.3 Schottky diode
A commonly used diode in RF applications is the Schottky diode. Unlike the regular pn-junction diode the Schottky diode uses a metal-semiconductor junction. By using this configuration the diode becomes a majority carrier device, which means only electrons are injected and, by being a majority carrier device, there will be no time consuming electron-hole recombination. Due to this the Schottky diode is faster than a conventional pn-diode and therefore suitable for high speed switching RF-applications, such as mixers.
5
3.2 Mixer basics
A mixers' prime function [2-9] is to translate one frequency to another. Mathematically this is done by multiplication of two signals at different frequencies, for example between frequency 1f and 2f . However the angular frequency 2 fω π= is used due to the trigonometric functions. How it works mathematically is shown with the following identity
( ) ( ) ( ) ( )1 2 1 2 1 21cos cos cos cos2
t t t t t tω ω ω ω ω ω⎡ ⎤= − + +⎣ ⎦ (1.1)
Apparently, multiplication of two signals with different frequencies gives two new frequency components; one is the sum and the other the difference between the two frequencies. The wanted signal is selected in some suitable way, usually by filtering. The symbol for a mixer can be seen in Figure 1. For the case of up-conversion3, the intermediate frequency (IF) IFω signal is applied to the left. From the bottom the local oscillator (LO) LOω signal is applied, and the output, the radio frequency (RF) RFω signal, is taken from the right. The multiplication sign in the mixer symbol suggests it works by multiplication. Inside the mixer symbol some non-linear device can be found, for example diodes or transistors. Before moving on to investigating different mixer topologies, let us investigate more closely how the mixer works by analyzing it mathematically.
Down-converterUp-converter
LO LO
RFIF RF IF
Figure 1 The mixer symbol for the cases of an up-converter and a down-converter.
3.2.1 General non-linear analysis
In the following, the variable Iω is the input frequency, that is either IFω or
RFω depending if the mixer is an up-converter or a down-converter.
A mixer is a non-linear device that is capable of frequency transformation due to the non-linear relationship between the input signals and the output signal. To describe it mathematically lets assume that
2 31 2 3
1
ni
out ii
I V V V Vα α α α=
= = + + +∑ K (1.2)
3 If down-conversion is wanted, simply change the RF and IF-signals with each other.
6
where V is the total input voltage, 1 2 3, , ,α α α K are constants dependent of the non-linear device used. It is easy to see that the output signal can be written as above, because every function can be approximated by a power or Taylor series if needed.
Below follows a practical example to show how it is applicable on a simple FET device and then follows the more general case.
3.2.1.1 Practical example
Let us see how the drain current for a simplified FET model that uses the square law behavior in saturation can be written [5]. This is done to make the analysis a bit more concrete.
The LO-signal is applied to the source of the transistor and the input signal is applied to the gate4 of the transistor, that is the RF-signal if it is a down-converting mixer, and the IF-signal if it is an up-converting mixer. The circuit can be seen in Figure 2.
G
D
VtSineVLO
VtSineVI
V_DCgate_biasVdc=VGS
EE_MOS1FET
RRload
LDC_FEED3
CDC_Blck2
CDC_Blck
LDC_FEED2
LDC_FEED
V_DCdrain_biasVdc=drain_bias
Figure 2 A simple mixer circuit. The LO-signal is applied to the source and the input
signal to the gate.
From Figure 2 it is evident that the gate to source voltage is
gs I LO GSV V V V= − + (1.3)
4 Often both the LO- and RF/IF-signal is applied to the gate, however using the source for the LO-signal is also valid because the potential between gate and source is what is important when the non-linear drain current is investigated.
7
where GSV is the gate to source DC bias voltage. Under the assumption that the device is operating in the saturation region, the drain current can be expressed as
2 2
21 2gs gs gsD DSS DSS DSS DSS
P P P
V V VI I I I I
V V V⎛ ⎞
= − = − +⎜ ⎟⎝ ⎠
(1.4)
Where PV is the pinch-off voltage and DSSI is the drain current for 0=gsV
A comparison with equation (1.2) and (1.4) shows thatP
DSS
VI2
1 −=α ,
22P
DSS
VI
=α and gsVV =
in this case. If a more complicated function were used, for example the relationship for a diode or BJT transistor, then the exponential function needs to be approximated by a series expansion.
If ( )cosI I Iv V tω= (1.5)
( )cosLO LO LOv V tω= (1.6)
and equation (1.3) is inserted in equation (1.4) then the drain current DI can be found (here Iω is the input signal, that is either RFω or IFω ). The derivation was done with help of the mathematical software MAPLE5; this can be seen in appendix C, Maple calculation 1. From this calculation the up-converted as well as the down-converted frequencies can be found. The expression is
( ) ( )2
1 cos cosDSS I LO I LO I LOP
I V V t t t tV
ω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.7)
The constant before the square bracket divided by the amplitude of the input voltage Iv is defined as the conversion transconductance:
2 2DSS I LO DSS LO
CI P P
I V V I Vg
V V V= = (1.8)
From the calculation (appendix C, Maple calculation 1) the following wanted components arises
The down-converted frequency:
( )2
1 cosDSS I LO I LOP
I V V t tV
ω ω− (1.9)
The up-converted frequency:
5 http://www.maplesoft.com/
8
( )2
1 cosDSS I LO I LOP
I V V t tV
ω ω+ (1.10)
And these undesired components arises
DC component:
2 22
1 2DSS P DSS P GS DSS GSP
I V I V V I VV
⎡ ⎤− +⎣ ⎦ (1.11)
Fundamental (RF/IF) input frequency component:
( )2
2 cosDSS P I IP
I V V tV
ω− (1.12)
Fundamental LO input frequency component:
( )2
2 cosDSS P LO LOP
I V V tV
ω (1.13)
Second harmonic (RF/IF) input frequency component:
( )22
1 cos 22 DSS I I
P
I V tV
ω (1.14)
Second harmonic LO input frequency component:
( )22
1 cos 22 DSS LO LO
P
I V tV
ω (1.15)
Note that signal components that have multiples, greater than one, of either the LO-, RF- or IF-signal is called harmonics.
In order to minimize the influences of these unwanted components some actions are needed, for example by filtering the output signal. Filtering is usually needed anyway to select the desired output frequency. The above equations were derived for the specific case of a square law FET device, described by (1.4). That is every voltage component above order two in the output current is zero.
3.2.1.2 The general case
The general form of equation (1.9) to (1.15), for terms up to third-order will now be considered. It is straight forward to analyze more terms if desired6. The calculation that was made to get these results was done in MAPLE and can be seen in appendix C, Maple calculation 2.
Up-converted frequency component:
6 Simply change the value of “n” in the MAPLE calculation to desired order and re-run the calculation.
9
[ ] ( )3 23 cosI LO bias I LO I LOV V V V V t tα α ω ω+ + (1.16)
Down-converted frequency component:
[ ] ( )3 23 cosI LO bias I LO I LOV V V V V t tα α ω ω+ − (1.17)
DC term:
2 2 3 2 23 3 3 2 2 1
3 3 1 12 2 2 2LO bias I bias bias I bias biasV V V V V V V Vα α α α α α+ + + + + (1.18)
Fundamental (RF/IF) input frequency component:
( )2 3 23 3 3 2 1
3 3 3 2 cos2 4LO I I I bias I bias I IV V V V V V V V tα α α α α ω⎡ ⎤+ + + +⎢ ⎥⎣ ⎦
(1.19)
Fundamental LO input frequency component:
( )3 2 23 3 3 2 1
3 3 3 2 cos4 2LO LO I LO bias LO bias LO LOV V V V V V V V tα α α α α ω⎡ ⎤+ + + +⎢ ⎥⎣ ⎦
(1.20)
Second harmonic (RF/IF) input frequency component:
( )2 23 2
3 1 cos 22 2I bias I IV V V tα α ω⎡ ⎤+⎢ ⎥⎣ ⎦
(1.21)
Second harmonic LO input frequency component:
( )2 23 2
3 1 cos 22 2LO bias LO LOV V V tα α ω⎡ ⎤+⎢ ⎥⎣ ⎦
(1.22)
Third harmonic (RF/IF) input frequency component:
( )33
1 cos 34 I IV tα ω (1.23)
Third harmonic LO input frequency component:
( )33
1 cos 34 LO LOV tα ω (1.24)
Third-order intermodulation product:
( ) ( )23
3 cos 2 cos 24 LO I LO I LO IV V t t t tα ω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.25)
and
( ) ( )23
3 cos 2 cos 24 LO I LO I LO IV V t t t tα ω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.26)
10
It should be noted that no third-order or higher intermodulation products arose during the analysis of the simplified FET because only non-linearity up to the second-order was considered there.
The name third-order is because the sum of the multiples of the two frequency components is three, two LO and one signal component in (1.25) for example, and 2+1 = 3 hence third-order. The third-order components will be discussed more closely in chapter 3.3.
The different frequency components are often illustrated in a graph in the frequency domain where the frequency and amplitude of the different components is shown. One example can be seen in Figure 3, this is in fact for the LO frequency of 1485 MHz and the IF frequency of 350 MHz used in this work. The output is therefore the RF frequency7 of 1485+350=1835 MHz.
From Figure 3 the LO-signal at 1485 MHz is seen, as well as the harmonic 2LO at 2970 MHz. The third-order intermodulation product at 2LO-IF at 2620 MHz can be seen in this graph, as well as many other harmonics and intermodulation products. The vertical scale is in dBm.
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00.0 4.5
-150
-100
-50
-200
0
freq, GHz
IF_s
pect
rum
Output Spectrum
Figure 3 Output spectrum
7 The graph says IF spectrum, however the correct is indeed the RF spectrum.
11
3.2.2 Restricted analysis: the conversion matrix method
In the literature often the output current as a function of the RF/IF input signal is given in the following form
( ) ( ) ( )i t g t v t= (1.27)
where ( )g t is the (trans) conductance, ( ) ( )( )
di tg t
dv t= and is assumed to be a
function of the LO-signal only and ( )v t is the applied RF/IF-signal. This way
to express the current ( )i t is valid if the amplitude of the RF/IF-signal is much lower than the amplitude of the LO-signal, then the LO is assumed to be solely responsible for mixing [8][9]
( ) ( )1
cosm
n LOn
g t g n tω=
= ∑ (1.28)
( ) ( )cosI Iv t V tω= (1.29)
It is therefore possible to divide the analysis of the mixer in two steps: 1 a non-linear analysis to determine the steady state time-varying
(trans)conductance ( )g t , here only the LO and bias voltage is
considered to see how they affect ( )g t 2 a linear analysis to determine the small-signal performance.
The current ( )i t is then simply
( ) ( ) ( ) ( ) ( )1
cos cosm
n LO I In
i t g t v t g n t V tω ω=
⎛ ⎞= = ⎜ ⎟
⎝ ⎠∑ (1.30)
Separating the products that arises when the multiplication in (1.30) is made gives
( )0 cosI Ig V tω (1.31)
( ) ( )1 cos cos2 I LO I LO Ig V t t t tω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.32)
( ) ( )2 cos 2 cos 22 I LO I LO Ig V t t t tω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.33)
( ) ( )3 cos 3 cos 32 I LO I LO Ig V t t t tω ω ω ω⎡ ⎤− + +⎣ ⎦ (1.34)
and so on. The total current ( )i t is then the sum of these components.
12
From this, it is clear that the output components is of the form LO Inω ω− and
LO Inω ω+ for 1,2,3,n = L . Harmonics of the LO-signal exists but no harmonics of the input RF/IF-signal and no DC component. But from the general analysis, as well as from the example above for the simplified FET mixer, harmonics of both the LO- and RF/IF-signal as well as a DC component appeared in the output!
A question is now arising, how valid is the restricted analysis? The simple answer is that it is valid while the LO-signal is much greater than the RF/IF-signal. To see this, a somewhat cumbersome mathematical calculation was made to compare the complete non-linear analysis with this restricted analysis. In this comparison, many terms are missing in the ( ) ( ) ( )i t g t v t= approximation. This is expected because only the LO-signal is treated as a non-linear function, not the applied RF/IF-signal.
The comparison is made by comparing the result of the complete non-linear analysis in “equ2” with the restricted analysis in “equ1” shown in the MAPLE calculation in appendix C, Maple calculation 3. Clearly every term that has IV
is the same in both “equ1” and “equ2” but higher order terms as 2 3, ,I IV V K are missing, as well as the DC components. Now, if the quotient between the LO and input signal is much greater than one, these components will have a negligible effect on the output signal and the general analysis can be simplified to the restricted analysis by discarding these higher order terms of
2 3, ,I IV V L and the DC term.
The complete non-linear analysis must be performed if the LO- and RF/IF-signal is of the same magnitude or if intermodulation products are of interest, which they usually are.
3.2.3 Mixer parameters
Now when it has been seen, that mixing is due to the non-linear relationship between input and output, let us define some important parameters.
3.2.3.1 Conversion gain
The conversion gain8 is defined as the amplitude of the output RF (IF) signal divided by the input IF (RF) signal amplitude.
3 23 2
33I LO bias I LO
LO bias LOI
V V V V Vconversion gain V V V
Vα α
α α+
= = + (1.35)
The conversion gain is often expressed in dB
8 From the equations for conversion gain or conversion loss, apparently the LO-signal amplitude is an important factor. Other important parameters such as the third-order interception point, IP3 and the 1-dB compression point
1dBP− will be defined later. These parameters are also dependent of the 1 2 3, , ,α α α K in the non-linear transfer characteristics.
13
( )20logdBconversion gain conversion gain= (1.36)
For mixers with no gain, often conversion loss is used.
1conversion lossconversion gain
= (1.37)
dB dBconversion loss conversion gain= − (1.38)
3.2.3.2 Isolation
Isolation (IS) between ports is an important parameter and is defined by the ratio of power available from the source to the power dissipated in the load at the same frequency.
3.2.3.3 Suppression
The suppression is defined as the power difference between two signals at the same port. For example in this case the LO-suppression relative to the RF-signal is defined as the LO-power at the output minus the RF-power at the output.
3.2.3.4 Impedances
The input and output impedance is defined as
,IN OUTV at excitation frequencyZI at excitation frequency
= (1.39)
14
3.3 General non-linear phenomena
There are many important phenomena in a non-linear system like a mixer. This section deals with the basic theory behind it and why it is important [10].
Assume that the output ( )y t of a non-linear device is a function of the input
signal ( )x t and can be written as
( ) ( ) ( ) ( ) ( )2 31 2 3
1
nn
ny t x t x t x t x tα α α α
∞
=
= = + + +∑ K (1.40)
where 1 2 3, , ,α α α L are constants. For simplicity, only the components to order three are considered here, but it is easy to extend the order if required. From (1.40) many interesting phenomena of a non-linear system can be derived.
If
( ) ( )cosx t A tω= (1.41)
then (1.40) becomes
( ) ( ) ( ) ( )2 2 3 31 2 3cos cos cosy t A t A t A tα ω α ω α ω= + + (1.42)
Simplifying and collecting terms, ( )y t can be written as
( ) ( )
( ) ( )
232
1 3
3232
3 cos2 4
cos 2 cos 32 4
Ay t A A t
AAt t
αα α ω
ααω ω
⎛ ⎞= + + +⎜ ⎟⎝ ⎠
+
(1.43)
From this, the term with the input frequency ω , is the fundamental term:
( )31 3
3 cos4
A A tα α ω⎛ ⎞+⎜ ⎟⎝ ⎠
(1.44)
The nth harmonic term is
( )cosK n tω (1.45)
15
where K is a constant and 1,2,3,n = K In (1.43) the second-order ( 2n = )
harmonic is ( )2
2 cos 22A tα ω and the third-order( 3n = ) harmonic is
( )3
3 cos 34A tα ω .There is also a DC component in the output,
22
2Aα
, although
the input signal, ( )x t ,had no DC term.
3.3.1 Gain Compression
The small-signal gain of a circuit is usually obtained with the assumption that the harmonics are negligible. Assume that 1α is much greater than all the other factors, so the higher order terms can be neglected. The small-signal
gain is then ( )( ) 1
y tx t
α=
In reality, as the input level increase, the small-signal gain starts to decrease
if 3 0α < , since 31 3
34
A Aα α+ is a decreasing function of A . This effect is
quantified by the 1-dB compression point, 1dBP− defined as the input signal level that causes a small-signal gain drop by 1 dB.
Mathematically:
( )21 3 1
320log | | 20 log | | 14
A dBα α α⎛ ⎞+ = −⎜ ⎟⎝ ⎠
(1.46)
11
3
0.145 | |dBA αα− = (1.47)
3.3.2 Desensitization and Blocking
When a weak desired signal, ( )1 1cosA tω and a strong interferer ( )2 2cosA tω is applied to a circuit, the strong signal reduces the gain of the circuit and the weak desired signal experiences a vanishingly small gain; this is called desensitization. For a sufficient large 2A the gain becomes zero and the
weaker signal is blocked. To see this assume ( ) ( ) ( )1 1 2 2cos cosx t A t A tω ω= + , then the output is (from (1.40))
( ) ( )3 21 1 3 1 3 1 2 1
3 3 cos4 2
y t A A A A tα α α ω⎛ ⎞= + + +⎜ ⎟⎝ ⎠
K (1.48)
if 1 2A A<< then
16
( ) ( )21 3 2 1 1
3 cos2
y t A A tα α ω⎛ ⎞= + +⎜ ⎟⎝ ⎠
K (1.49)
The gain of the desired signal ( )1 1cosA tω is therefore 21 3 2
32
Aα α+ . If 3 0α <
the gain is decreasing with 2A , this is called desensitization. For some value of 2A , the gain becomes zero and the signal is blocked.
3.3.3 Cross modulation
When a variation in the amplitude of a strong interferer affect the amplitude of the weak and wanted signal, is called cross modulation. It is easy to see this if ( )y t from (1.49) is considered. Now, if the amplitude 2A is changing, the
amplitude of the wanted signal 1ω also is changing. This phenomenon is most important when many signals are processed at the same time.
3.3.4 Intermodulation
When two (or more signals) with different frequencies are applied to a non-linear system, frequencies that are not harmonics of the input frequencies arise. This is called intermodulation, IM.
This arises from the mixing of the two signals when their sum is raised to a power greater than unity. To see how, assume ( ) ( ) ( )1 1 2 2cos cosx t A t A tω ω= + , if this is inserted in (1.40) the resulting
intermodulation products are
( ) ( )1 2 2 1 2 1 2 2 1 2 1 2: cos cosA A t t A A t tω ω ω α ω ω α ω ω= ± + + − (1.50)
( ) ( )2 21 2 3 1 2 1 2 3 1 2 1 2
3 32 : cos 2 cos 24 4
A A t t A A t tω ω ω α ω ω α ω ω= ± + + − (1.51)
( ) ( )2 22 1 3 2 1 2 1 3 2 1 2 1
3 32 : cos 2 cos 24 4
A A t t A A t tω ω ω α ω ω α ω ω= ± + + − (1.52)
and these fundamental products
( )3 21 1 3 1 3 1 2 1
3 3 cos4 2
A A A A tα α α ω⎛ ⎞+ +⎜ ⎟⎝ ⎠
(1.53)
( )3 21 2 3 2 3 2 1 2
3 3 cos4 2
A A A A tα α α ω⎛ ⎞+ +⎜ ⎟⎝ ⎠
(1.54)
The third-order IM products 2 12ω ω− and 1 22ω ω− are the most interesting ones. The reason is that the difference between 2 12ω ω− and 1 22ω ω− is in the vicinity of 1ω and 2ω , if the difference between 1ω and 2ω is small. This small frequency difference makes it almost impossible to filter these unwanted frequency components.
17
To measure the IM distortion, a two-tone test can be made. In a typical two-tone test; 1 2A A A= = . The ratio of the amplitude of the third-order output product to 1Aα , defines the IM distortion. The unit used here is dBc, “c” means “with the respect to the carrier”.
The third-order IM is so important so that a performance metric has been defined for this, called the third-order interception point. This is measured with a two-tone test where 1 2A A A= = is chosen so that higher order non-linearity terms are negligible and the gain is relatively constant and equal to 1α . The fundamental product increases in proportion to A , whereas the third-order IM product, increases as 3A . The third-order interception point is defined to be the interception of these two lines as the name suggest. The horizontal coordinate of this point is called the input interception point, IIP3 and this is the voltage input amplitude. The vertical coordinate of this point is called the output interception point, OIP3 and is the corresponding voltage output amplitude. It is common to express these metrics in the unit dBm, in that case the voltage quantities is converted to power.
If 1 2A A A= = then a simple expression for IP3 can be derived under the
assumption that 21 3
94
Aα α>> , the result is
13
3
4 | |3IIPA α
α= (1.55)
In practice, the IM and fundamental is measured for small values of A then interpolation is used to obtain the IP3 points.
18
3.4 Resistive FET-mixer
In a resistive FET-mixer’s the resistance between the drain and source is modulated by the LO-signal, applied to the gate of the FET. With no applied bias at the drain the slope of the I-V curves can be changed by the applied
gsV voltage, the LO-signal, and therefore the conductance can change very much.
Ideally, the LO switch the conductance between an on-state, when the device is near forward turn-on, and an off-state when the device is in pinch-off. The I-V curves for small dsV and different gsV for the Cold-FET9 model (used in this work) can be seen in Figure 4. From this figure it is clear that the I-V relationship is almost linear for low dsV voltages. The threshold voltage for this FET is -0.95 V. The right graph in Figure 4 is a close up of the left one, from this, the drain to source resistance for 0gsV = and 0.8gsV = − was estimated
as dVRdI
= . For 0gsV = the value is about 15 ohm and for 0.8gsV = − the
value is about 300 ohm. From the graph it can be seen that the resistance is approaching infinity when gsV is approaching the threshold voltage. The
conductance shows an inverse relationship with gsV voltage.
-0.4 -0.2 0.0 0.2 0.4-0.6 0.6
-40
-30
-20
-10
0
10
20
30
-50
40
VGS=-2.000VGS=-1.800VGS=-1.600VGS=-1.400VGS=-1.200VGS=-1.000VGS=-0.800VGS=-0.600
VGS=-0.400
VGS=-0.200
VGS=0.000
VDS
DC
.IDS
.i, m
A
Device I-V Curves
-0.1 0.0 0.1-0.2 0.2
-12-9-6-30369
12
-15
15
VGS=-2.000VGS=-1.800VGS=-1.600VGS=-1.400VGS=-1.200VGS=-1.000VGS=-0.800
VGS=-0.600
VGS=-0.400
VGS=-0.200VGS=0.000
VDS
DC
.IDS
.i, m
A
Device I-V Curves
Figure 4 I-V curves for a FET operating as a resistive FET-mixer.
For very small values of dsV the drain current can be modeled by Shockley theory [13], however here an approximate analysis [14] is made to predict the conversion gain or conversion loss.
Let us assume that the conductance can be described by the following equation
( ) if
0 if g P g P
dsg P
K V V V VG
V V
⎧ − >⎪= ⎨≤⎪⎩
(1.56)
where K is the slope of the channel conductance, gV is the gate voltage and
PV the pinch-off voltage.
9 Cold-FET is a special model that models the FETs behaviour at very low drain source voltages.
19
To see if this is reasonable a S-parameter simulation was done to estimate dsG as a function of gV . Here the input resistance, looking into the drain, was
simulated. So influences from the drain resistance, for example, are also included here. From the simulation results shown in Figure 5 the assumption that dsG is a linear function of gV seems pretty good at low gV , for higher
value of gV it can be seen that the curve deviate from being a linear curve. But according to the Shockley theory this is expected.
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1-1.0 0.0
0.02
0.04
0.06
0.00
0.08
Gate_bias
1/re
al(Z
(1,1
))Gd(Vg)
Figure 5 Conductance as a function of gate bias.
An equivalent circuit, as seen from the LO-port, can be made. The LO-signal is applied to the gate of the transistor. Remember also that the drain and source is assumed to be DC short circuit. The equivalent circuit for the LO is shown in Figure 6. The impedance ZDLO is assumed to be short-circuit for the LO-signal at the drain terminal, ZGLO is assumed to be the generator impedance for the LO and short circuit for all other frequencies. The left hand circuit in the figure can be simplified to the one shown to the right in the figure, under the assumption that gsC and gdC have approximately the same value
and sR and dR also have approximately the same value. This results in that no current will flow through dG because the potential is the same on the left and right side, therefore it can be removed. From this equivalent circuit it is also possible to estimate the input impedance for the LO-signal.
G
S
DD
S
G
CCgs1
CCgd1
RRg1
RZGLO1
VtSineLOsrc1
RZDLO1
RRd1
RRs1
RRs
RRd
RZDLO
VtSineLOsrc
RZGLO
RRg
CCgd
CCgs
RGd
Figure 6 Equivalent circuit for the LO, looking in to the gate.
20
D
SS
D
G
RRd1
RZDRF1
VtSineRFsrc1
RRs1
RGd1
RGdC
Cgd
CCgsR
RgRRs
RZGRF
VtSineRFsrc
RZDRF
RRd
Figure 7 Equivalent circuit for the input signal, looking in to the drain.
An equivalent circuit for the input RF-signal, looking in to the drain, can also be developed; this is shown in Figure 7. The simplification of the left circuit to the right one in Figure 7 is not too obvious. But here the fact that the reactance of gsC and gdC is much greater than sR and dR is used.
From the right circuit in Figure 7, the small-signal drain current can be derived. Assume that ( )1 cosRF RFRFsrc V tω= then the small-signal current can be derive as
( )
( )( ) ( )( )[ ]
,
,
,
cos1
cos
1
RF RFd
d sd g LO
d g LO RF RF
d g LO d s
V tI
ZDRF R RG V
G V V t
G V R R ZDRF
ω
ω
= =+ + +
+ + +
(1.57)
if we let
( ) ( )( )[ ]
,
,1d g LO
LOd g LO d s
G Vf t
G V R R ZDRFω =
+ + + (1.58)
then (1.57) becomes
( ) ( )cosd LO RF RFI f t V tω ω= (1.59)
If the transistor is biased near pinch-off, ( ),d g LOG V can be expressed as
( ) ( ),,
cos if 0.5 0.5
0 if 0.5 1.5g LO LO LO
d g LOLO
KV t tG V
t
ω φ π ω φ π
π ω φ π
⎧ + − < + <⎪= ⎨< + <⎪⎩
(1.60)
Hence (1.58) becomes
21
( ) ( )( )
,
,
cos1 [ ] cos
g LO LOLO
d s g LO LO
KV tf t
R R ZDRF KV tω φ
ωω φ
+=
+ + + + (1.61)
From (1.61) it is apparent that more LO power, and therefore a higher ,g LOV voltage, increases conversion gain or decreases conversion loss.
The drain current can now be predicted by the derived equations. To get the conversion gain the function ( )LOf tω needs to be described by a Fourier
transform, only the first term 1g is needed. It can be calculated numerically from the following integral
( ) ( )2
1
2
1 cosg f x x dx
π
ππ−
= ∫ (1.62)
where ( )f x is the same function as in (1.61)
The down-converted or up-converted drain current ( dI ) is then
( )1, cos
2RF
d IF LO RFg V
i t tω ω= − (1.63)
( )1, cos
2RF
d RF LO IFg V
i t tω ω= + (1.64)
Now the conversion gain or loss can be calculated. The conversion gain is
simply 1
2g
.
22
3.5 Balanced diode mixers
In today’s mixers the requirements on linearity, port-to-port isolation, noise, IM-suppression and so on are high, and a single ended mixer just is not enough. The solution to this is to use a balanced mixer topology which, inherently, performs well on these aspects. The drawback with this method is that it requires more LO-power since it uses two or more diodes. It can also be hard, and even impossible, to add bias to the diode which degrades the conversion gain.
The operation of single-balanced (SB) and double-balanced (DB) mixers will be described respectively in the following two sections. [2] [3] [9] [36] [37]
3.5.1 Single-balanced diode mixer
Figure 8 shows one example of a single-balanced mixer using two antiparallel diodes, a hybrid and a band-pass filter. The hybrid can either be a 180°-hybrid or a 90°-hybrid, but the latter one not commonly used in up-converters since its disability to produce positive mixing frequencies ( LO RFω ω+ ), which will be shown later. In Figure 8, the 180°-hybrid is used which, ideally, phase shifts the LO-signal 180° on the Δ -port and leave the phase of the LO untouched at the Σ -port. The IF-signal will be in phase at both of these ports10.
V_LO*V_IF
V_LOV_IF
C
I_RF2
I_RF1
B
A
BPF_ButterworthBPF1Diode
D2
DiodeD1
PortRFNum=3
Hybrid180HYB2
IN
ISO
PortLONum=2
PortIFNum=1
Figure 8 Single-balanced diode mixer.
Under the first half period of the LO-signal the unshifted part of the signal (V_LO) will make D1 conduct (if diodes are treated as switches) and the shifted part of the LO (V_LO*) will make D2 conduct. That is, in other words, both diodes are short circuit to the IF. Conversely, both diodes will be open circuits to IF during the second half period of the LO, this causes mixing in the same “switch-like” manner as in a single diode mixer. Since IF is in phase over the diodes and the diodes conduct simultaneously the RF-current, created by the conductance switching, will simply be summed in node C.
10 Since the RF-signal is inserted in phase, a balun can be used for the LO, and the RF is simply connected to the diodes directly.
23
Since the IF and LO are connected to mutually isolated ports of the hybrid (if such is used) their isolation depends solely on the performance of the hybrid. Ideally the single-balanced mixer in Figure 8 should have very good LO to RF isolation. This is because when the two LO-signals (one phase shifted 180°) enters node C11 they both cancels each other, ending up with no LO at the output. However, this is only ideally, in reality there is no such thing as a perfect 180° phase shift and there does not exist perfectly matched diodes either.
Considering the diode as a non-linear device the current produced in the diode can, again, be approximated using power series. Thus
2 31 2 3DiodeI V V Vα α α= + + +K (1.65)
describes the total current in the diode, where V is the total voltage over the diode and 1 2 3, ,α α α are constants. Independent of whatever phase shift that may occur in the hybrid one of the diodes is reversed with respect to the other; this will cause the voltage of one of the diodes to be opposite of the other. Currents and voltages over the two diodes are shown in a simplified picture of the mixer in Figure 9. Here the voltage over D1 will change sign, and hence the two currents I1 and I2 are
2 31 1 1 2 1 3 1
2 32 1 2 2 2 3 2
I V V V
I V V V
α α α
α α α
= − + − +
= + + +
K
K (1.66)
respectively. The total current at the output is
2 1RFI I I= − (1.67)
I_RF=I2-I1
C
B
A
I1
I2
- V2 +
- V1 +
PortRF
PortP1
PortP2
DiodeD2
DiodeD1
Figure 9 A simplified picture of the mixer.
11 The node C can, due to the symmetry of the circuit, be treated as a virtual ground to the LO.
24
In the general case, the voltages appearing at node A and B, and also over the diodes are
1 1, 1,
2 2, 2,
IF LO
IF LO
V V VandV V V
= +
= + (1.68)
where
1, 1,
1, 1,
2, 2,
2, 2,
cos( ),cos( ),cos( )
andcos( )
IF IF IF IF
LO LO LO LO
IF IF IF IF
LO LO LO LO
V A tV A tV A t
V A t
ω ϕ
ω ϕ
ω ϕ
ω ϕ
= +
= +
= +
= +
(1.69)
where IFA and LOA is the amplitude of the IF- and LO-signals, IFω and LOω is their frequencies and theϕ ’s is the phase shift that occurs in the hybrid.
If the hybrid in Figure 8 is used there will be a 180-degree phase shift from the LO to the Δ -port and thus the voltages, V1 and V2, over the diodes will be
1
2
cos( ) cos( )
cos( ) cos( )
IF IF LO LO
IF IF LO LO
V A t A tandV A t A t
ω ω
ω ω
= +
= − (1.70)
If V1 and V2 are inserted in the expression for the current at the output, and after some trigonometry12, the following expression is found
( )
( ) ( )( )( ) ( )( )
( )
32 1 3
23
2
3 23 3 1
1 cos 32
3 cos 2 cos 222 cos cos
3 3 2 cos2
RF IF IF
IF LO IF LO IF LO
IF LO IF LO IF LO
IF IF LO IF IF
I I I A t
A A t t t t
A A t t t t
A A A A t
α ω
α ω ω ω ω
α ω ω ω ω
α α α ω
= − = +
− + + −
− − + +
⎛ ⎞+ +⎜ ⎟⎝ ⎠
(1.71)
12 Some useful trigonometric identities are
cos(2 ) 12 2( cos( ))2
xta xt a
+= and cos( ) cos( ) 0.5 (cos( ) cos( ))a xt b yt ab xt yt xt yt⋅ = + + −
25
As seen in the expression (1.71) above and also according to Maas [3] the current at the output contains no spurious responses where m and n both are even. m and n are the coefficients appearing in IF LOm nω ω± ± . Also the spurious’ arising from the cases when m is even and n is odd vanishes. Mixing harmonics occurs only at order k, where | |k m n= + . Wanted mixing, when m and n are positive and 1, occurs, but also down-conversion when
1m = − and 1n = .
If the LO and IF input signals are interchanged the phase shift occurs at the IF instead. Thus
1
2
cos( ) cos( )
cos( ) cos( )
IF IF LO LO
IF IF LO LO
V A t A tandV A t A t
ω ω
ω ω
= +
= − + (1.72)
And the current appearing at the output now becomes
( )
( )
3 22 1 1 3 3
2
3
2
32 3 cos( t)+2
3 cos( 2 ) cos( 2 )2
1 cos(3 )2
2 cos( ) cos( )
RF LO LO LO IF LO
LO IF LO IF LO IF
LO LO
IF LO IF LO IF LO
I I I A A A A
cA A t t t t
cA t
A A t t t t
α α α ω
ω ω ω ω
ω
α ω ω ω ω
⎛ ⎞= − = + +⎜ ⎟⎝ ⎠
− + +
+ −
− + + +
(1.73)
A quick comparison between the results (1.71) and (1.73) shows that the only difference is that the elimination of the spurious’ that arose from the case when m was even and n odd are reversed, that is spurious’ are eliminated when m is odd and n even.
A more interesting result is when a 90-degree hybrid is used. In the same manner the voltages becomes
1
2
cos( ) cos( )cos( ) cos( )
IF IF LO LO
IF IF LO LO
V A t A tV A t A t
ω ωω ω
= − += −
(1.74)
The expression for the total output current becomes very long and is therefore presented in appendix C, Maple calculation 4. The main issue is however that there exist no frequency components where m and n are one and positive, only the down-conversion case. Hence a 90-degree hybrid could not be used in an up-converter. The result also shows that there is no “m even, n odd/m odd, n even” suppression in this case.
However, there is a solution to circumvent the unfortunate lack of up-conversion responses, and that is to connect the diodes parallel. This configuration, on the other hand, will only result in up-conversion, the down-conversion components vanish in this case.
26
To conclude this discussion the choice of hybrid preferably falls on a 180-degree if up-conversion is wanted. Considering what kind of spurious signals wanted (or unwanted) at the output the interconnection of the input signals to the hybrid becomes important. It might however be wise, in this application, to choose the one that causes 180-degree shift since this will eliminate the LO at the output due to the virtual ground at node C.
3.5.2 Double-balanced diode mixers
A double-balanced mixer [2] [3] [9] [36] [37] is actually two single-balanced diode mixers connected together, so whatever good features that comes with SB also comes with DB. To begin with, a DB uses a separate balun for the IF and RF-signal (the RF is tapped at the centre-tap of the IF balun) which gives it good IF to RF-isolation. This is due to the fact that the RF-port can be treated as a virtual ground when connected to the centre-tap of the balun, and therefore, the balance of this balun is important if high IF-suppression is wanted. Secondly, the LO to RF- and IF-isolation is caused in the same way as in SB. A basic DB mixer can be seen in Figure 10, here the input baluns are realized using ideal transformers.
Figure 10 A double-balanced mixer using ideal transformers as input baluns.
Again, due to symmetry, the nodes A and A’ is seen as virtual grounds to the LO and, conversely, the nodes B and B’ is seen as virtual grounds to the IF.
LO
IF
B
B'
A'A
PortRF_out
XFERTAPXFer2
PortIF1
PortIF2
XFERTAPXFer1
PortLO2
DiodeD1 Diode
D4
DiodeD3
DiodeD2
PortLO1
27
Looking upon the diodes as if they were ideal voltage controlled switches; a quantitative analysis of the circuit in Figure 10 can be made in the same way as in the SB case. The LO-input transformer (XFer1) will cause a 180-degree phase shift to be apparent at the bottom port of the LO-transformer, in the figure this port is connected to node B’ (the ‘prime’ denotes the inverse or the phase shift). The un-shifted part is connected to node B. During the first half period of the LO-pump, the diodes D3 and D4 are closed and D1 and D2 are opened. This will make the IF-transformer secondary (virtually) grounded at node A’ and open circuited at node A. In this case the phase shifted IF-signal is apparent at the RF output. During the other half period the situation is reversed; node A is grounded and A’ is open circuited, and also the unshifted IF-signal is apparent at the output. In other words, the IF-signal shifts polarity in the speed of LO-pumping, thus causing IF to be modulated with LO. This reasoning is easily verified using ADS and the circuit in Figure 11.
Vlo2
Vlo3
Vt3
Vt2
Vrf
Vif
V_nToneSRC2
V[1]=polar(1,0) VFreq[1]=1.485 GHz
V_nToneSRC3
V[1]=polar(-1,0) VFreq[1]=1.485 GHz
V_nToneSRC1
V[1]=polar(1,0) VFreq[1]=0.350 GHz
SwitchV_ModelSWITCHVM1
AllParams=V2=1.0 VR2=1.0 MOhmV1=0.0 VR1=1.0 Ohm
V
HarmonicBalanceHB1
Order[2]=10Order[1]=10Freq[2]=0.350 GHzFreq[1]=1.485 GHz
HARMONIC BALANCE
SwitchVSWITCHV1
V
SwitchVSWITCHV2
V
RR4R=50 Ohm
I_ProbeIt3
RR3R=50 Ohm
I_ProbeIt2
I_ProbeIrf
XFERTAPXFer2
RR2R=50 Ohm
RR1R=50 Ohm
Figure 11 Circuit to show the behaviour of the IF transformer.
In Figure 11 ideal 1 V-triggered voltage controlled switches (SWITCHV1 and SWITCHV2 in figure) are used to symbolize the two diode pairs. Tone generators are used to realize the input signals; SRC1 represent the IF and SRC2-3 represent the LO. Notice the ‘minus’-sign used to cause the phase shift in the voltage at SRC3. A harmonic balance simulation of order 10 is performed and the resulting output spectrum is plotted in Figure 12. As seen both the up-converted and down-converted signal is clearly visible at the Vrf node. Since this is a very ideal situation the isolation between ports is very good (and very unrealistic), there is, for example, no sign of the LO at the output.
28
0.5 1.0 1.5 2.00.0 2.5
-400
-300
-200
-100
0
-500
100
freq, GHzdB
m(V
rf)
m1 m2
m3
m1freq=dBm(Vrf)=-2.409
1.135GHzm2freq=dBm(Vrf)=-2.250
1.835GHzm3freq=dBm(Vrf)=-334.031
350.0MHz
Figure 12 Output spectrum of IF transformer simulation.
Since the IF balun can be removed (analytically) when analyzing the LO port the transformation seen in Figure 13 can be made. This figure shows that, due to symmetry, the LO-signal will be nulled out in the LO-virtual ground apparent at the nodes A and A’. The case will be the same for the IF-signal as seen from the input of the IF balun, hence the IF is also isolated from the LO.
LO
Virtual ground for LO
LOA A'
PortLO3
PortLO4
XFERTAPXFer2 Diode
D44
DiodeD11
DiodeD33
DiodeD22
PortLO1
DiodeD2 Diode
D3
DiodeD4
DiodeD1
PortLO2
XFERTAPXFer1
Figure 13 The LO-signal is cancelled at the output in same manner as in a SB mixer.
The picture shows an easy circuit transformation to convince.
29
By looking at Figure 13 again it is evident that there must be the same voltage over all diodes, only signs are different, and for the sake of convenience and symmetry only the upper half of the circuit will be treated further. The total current in the upper diode pair is denoted Iu (‘u’ as in upper) which is the sum of the currents through the diodes, I33 and I22 respectively. Hence,
33 22uI I I= − (1.75)
in the same manner as in SB mixers. Thus, also in same manner, the spurious mixing products with m and n even will cancel.
30
4 Requirements
The task was to construct an up-converter from 350 MHz IF to 1835 MHz RF, with high demands on linearity and LO to RF suppression. Below follows the data given: • IF frequency: 350 MHz • LO frequency: 1485 MHz • RF frequency :1835 MHz • Available LO power: ≤ 0 dBm • Available IF power: -20 dBm And the requirements were: • Output power of -10 dBm, translates to a conversion gain of 10 dB for an
input power of -20 dBm. • Suppression: -20 dB. • IIP3: 24 dBm.
31
5 Design
This chapter shows how the design of two up-converters is done, one with diodes, and the other with transistors. Due to the two designs, this chapter is divided in two main subchapters; one for the design of the diode mixer and the other for the design of the resistive FET-mixer.
The order of the designs presented here tries to reflect the order of the real design, but, since real circuit design is an iterative process this is just a hint of what could have been an ideal design flow. First, the design of the mixer core is performed, second the LO balun/amplifier is done and finally the output amplifier is designed. The goals for the different parts are not known from the beginning, but the result from one part gives the requirement for the other and so on. In the rest of this chapter the design of each part will be discussed and presented.
5.1 Diode mixer
5.1.1 Mixer core
The mixer core is responsible for the mixing function to translate our IF of 350 MHz to the RF of 1835 MHz.
Since both the Triquint HBT2 and Triquint pHEMT processes have diode models available both of them can be used to construct diode mixer cores. The first task was therefore to decide which process that was the best performing.
To do this an evaluation circuit was made. The test circuit was made as simple as possible using ideal lumped components. At the inputs there were one capacitance allowing the LO-signal to pass and one inductor allowing IF. At the output a band-pass filter for the RF-signal was made. The circuit is presented in Figure 14.
1 2
LL1
R=L=41 nH
21
CC1C=1.0 pF
1 2
DA_LCBandpassDT1_S_param_testbenchDA_LCBandpassDT1
DT1
PortRF_outNum=2
1 2
tqhbt2_dschD5w =Size um
1
PortIF_inNum=1
1
PortLO_inNum=3
Figure 14 Evaluation circuit for diodes.
To achieve the high LO to RF suppression specified, the most probable choice of topology is a double-balanced one and since there is not any known method of biasing such topology all evaluation was made with an unbiased diode. How this is possible is explained by the fact that the diodes can be biased through the LO-signal: the diodes are LO-pumped. This implied that the LO-signal had to be amplified to pump the diodes.
32
The evaluation process was pretty much straight forward, first deciding the diodes width using the best performing value in conversion gain and compression point simulations with the width swept. Next, using this width, the most appropriate LO-power was decided using the same simulations but sweeping the input LO-power instead. For simplicity the ADS design guides for both conversion gain and compression were used (‘Single-Ended Mixer Characterization>IF Spect., Isolation, Conv. Gain, Port Impedances’ and ‘Single-Ended Mixer Characterization>N-db Gain Compression Point’).
One conclusion that was made during the evaluation is that there were no big differences between the processes. The conversion gain was almost the same for both but as seen in Figure 15 the compression point was slightly better for the HBT diode, at least for higher values of LO-power. Basically it was this result that made the decision fall onto the HBT process.
2 4 6 8 10 12 14 16 18 20 22 240 26
-5
0
5
10
15
-10
20
P_LO
test
_N_D
B_co
mp_
HBT
..inp
wr[0
]te
st_N
_DB_
com
p_pH
EMT.
.inpw
r[0]
Figure 15 1-dB compression point versus LO-power.
The final values of this evaluation are summarized in Table 1. Notice that these values of LO-power and width were preliminary and they would change later in the work, but they were a good start.
It should also be mentioned that no IP3 simulations were involved in the evaluation, this is because the diode models used performs really bad at 2-tone simulations. Therefore the 10-dB rule of thumb13 has been applied whenever diodes are involved.
P_LO
(dBm) Width (um)
1-dB compression (dBm)
Conversion gain (dB)
TQT HBT2 15 30 12,3 -11 TQT pHEMT 15 30 10,6 -11,2
Table 1, resulting values from the evaluation.
13 The “10-dB rule of thumb”: 13 10dBIIP P−≈ +
33
Besides to determine the optimal diode width and process type the work on a single diode is a good chance for the designer to get familiar with the simulations and construction techniques that are used in mixer design. However, one cannot expect the performance to fulfil the specified requirements that this work is based on; therefore the single diode mixer topology was abandoned.
Except the early work with a single diode core mainly two mixer topologies were examined: single-balanced diode pair, in Figure 16 and double-balanced diode quad, in Figure 17. The theory regarding these two topologies is presented in more detail in chapter 3.5.
The single-balanced diode was early abandoned due to the superior performance of the double-balanced version. Therefore this single-balanced topology will not be discussed further.
Bandpass filter at RF-frequency
1 2
DA_LCBandpassDT1_S_param_testbenchDA_LCBandpassDT1
DT1
PortRF_outNum=2
1 2
tqhbt2_dschD2w=Size um
12
tqhbt2_dschD1w=Size um
1
PortIF_inNum=1
1
PortLO_inNum=3
4
31
2
Hybrid180HYB3
PhaseBal=3GainBal=0.5 dBLoss=0 dB
IN
ISO
Figure 16 Single-balanced diode pair with ideal ADS hybrid and filter. Notice that
some imbalances are added to the system using the settings ‘GainBal’ and ‘PhaseBal’ in the hybrid.
5.1.1.1 Double-balanced diode mixers
The double-balanced mixer topology used is the one showed in Figure 17. The mixer uses an input 180-degree LO-hybrid and an IF-transformer with a centre-tap. To achieve more realistic results some, not-unlike-to-occur14, imbalances were added to the system through, mainly the LO-hybrid. Since the IF-transformer is supposed to work on a frequency as low as 350 MHz it was decided that this component is bought and placed off-chip. This is due to the large λ a frequency of 350 MHz implies. Larger λ results in larger chip area and higher expenses, even if lumped components are used.
14 It is in fact based on results from the design of the baluns; all this work is indeed highly iterative.
34
Vin2
Vin1
IF-input transformer w ith the RF tapped from the center tap.
LO-input balun
4
3
1
5
2
6
TF3TF1
T2=1.0T1=1.1
1
2
3
3
1-
T1
1-
T2
1
1
2tqhbt2_dschD4w =DiodeScale um
1
2
tqhbt2_dschD3w =DiodeScale um
1
2
tqhbt2_dschD2w =DiodeScale um
1
2
tqhbt2_dschD1w =DiodeScale um
4
31
2
Hybrid180HYB1
PhaseBal=3GainBal=0.04 dBLoss=-0 dB
IN
ISO1
PortRF_outNum=2
1
PortIF_inNum=1
1
1
1
PortLO_inNum=3
Figure 17 The double-balanced diode ring mixer topology. Some imbalances are
added to the ideal balun and transformer.
As mentioned before the LO-signal had to be amplified, since < 0 dBm of LO-power (as specified) is not enough to properly pump the diodes, and the main topic now is to decide the optimal LO-power. Parameter sweep of LO-power shows that an input power around 6-7 dBm gives the best compromise between LO to RF isolation, conversion loss and linearity. This region is shown in Figure 18 inside the rectangle, for convenience this rectangle is further on referred to as the “trade-off area”.
ISOP_LO=LOtoRF_isolation=14.763
7.000
P1dbP_LO=CP_sim..inpw r[0]=8.453
6.000
ConvGP_LO=ConvGain_Up=-6.692
7.000
pow er1835P_LO=outpow er_1835=-26.692
7.000
pow er1485P_LO=outpow er_1485=-41.456
7.000
1 2 3 4 5 6 7 8 9 10 11 12 13 140 15
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
-55
25
-20
-15
-10
-5
0
5
10
15
20
-25
25
P_LO
outp
ower
_148
5
pow er1485
outp
ower
_183
5
pow er1835
LOtoR
F_isolation
ISO
ConvG
ain_Up
ConvGCP_
sim
..in
pwr[
0]
P1dbISOP_LO=LOtoRF_isolation=14.763
7.000
P1dbP_LO=CP_sim..inpw r[0]=8.453
6.000
ConvGP_LO=ConvGain_Up=-6.692
7.000
pow er1835P_LO=outpow er_1835=-26.692
7.000
pow er1485P_LO=outpow er_1485=-41.456
7.000
Trade-off area
Figure 18 In this figure the 1-dB compression point (‘CP_sim.inpwr[0]’ or green trace
in dBm), conversion loss (‘ConvGain_Up’ black trace in dB), LO to RF isolation (‘LOtoRF_Isolation’ magenta trace) in dB, LO-output power (‘outpower_1485’ blue trace in dBm) and up-converted frequency’s output power (‘outpower_1835’ red trace in dBm), is plotted versus input LO-power (in dBm). It is desired to have the LO-power within the rectangle or the so called “trade-off area”.
35
This “trade-off area” is mainly restricted by conversion loss and LO to RF isolation. As seen in Figure 18 there are peaks in the graphs around P_LO=2 to 5 dBm, this is where the forward voltage region of the diodes are passed and to reduce the losses the LO-power is selected above this. As the LO-input power increases the LO-power present at the output also increases and, as seen in the figure, the LO-output power tends to increase faster than the RF-output power; therefore the upper region of the “trade-off area” is restricted due to this. This differ from the value achieved in the early work were the LO-power was set to 15 dBm, which indeed pumps the diode, but a value this high degrades the LO to RF isolation.
From Figure 18 more observations can be made. For example the output power of the RF-signal, which is -26.7 dBm, has to be amplified at least 16.7 dB to achieve the specified RF-power of -10 dBm. The 1-dB compression point of 8.5 dBm might seem a bit low in order to fulfil the requirement of an IIP3 of 24 dBm but, luckily, this would increase in the final design. Considering that the imbalances added to the LO-hybrid are realistic the isolation of 14.8 dB, between LO to RF, was not enough at this stage. As seen later this has been taken care of by using a simple filter.
Some useful references are: [2] [3] [9]
5.1.2 Baluns15
The baluns main task is of course to transform an unbalanced input into two signals, separated 180-degrees in phase. But apart from this, the LO-input baluns used in this design, have to amplify the signal in order to achieve the power needed to properly pump the diodes (as stated previously).
To achieve this amplification two separate methods have been considered: (a) by using a fully active balun based on a differential amplifier [38] [39] [40] and (b) by using an amplifier preceded by a passive hybrid [2] [3] [9] [41] [42] [43] [44] [45]. In this part the design of both the active balun and passive hybrid will be described. Also the IF-balun [3] will be considered here.
15 Both the LO-hybrid and the IF-transformer are loosely referred to as baluns throughout this report.
36
5.1.2.1 Active LO-balun
The balun is basically a differential stage with a current source. The A-part seen in Figure 19 is the differential “core” and the B-part is the current source (current mirror). This section will begin with a short theory part trying to describe how the balun works.
B
A
I1I2
Mirror
Vin
1
1
2
V_DCSRC3Vdc=7.0 V
21
RR4R=60 Ohm
1
1
PortLO_out1Num=2
21
CC12C=Cr pF
2 1
CC32C=10 pF
1 12
V_DCSRC1Vdc=5 V
11 2
V_DCSRC2Vdc=5 V
1
PortLO_out2Num=3
1
PortLO_inNum=1
1
2
4 3
Tqhbt_3x3x45Tqhbt_2
temp=25area=135
e2 e1
c
b
1
2
4 3
Tqhbt_3x3x45Tqhbt_6
temp=25area=135
e2 e1
c
b
1
2
4 3
Tqhbt_3x3x45Tqhbt_5
temp=25area=135
e2 e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_8
temp=25area=135
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_7
temp=25area=135
e2e1
c
b
2
1RR32R=55 Ohm
2
1
RR31R=67.7 Ohm
2
1RR22R=55 Ohm
2
1
RR21R=67.7 Ohm
2
1RR12R=Rstab Ohm
2
1RR11R=Rstab Ohm
1
2
43Tqhbt_3x3x45Tqhbt_4
temp=25area=135
e2e1
c
b
1
2
43Tqhbt_3x3x45Tqhbt_3
temp=25area=135
e2e1
c
b
1
2
4 3Tqhbt_3x3x45Tqhbt_1
temp=25area=135
e2 e1
c
b
2
1RRL2R=(1.0*22) Ohm
2
1CC22C=20 pF
2
1CC21C=20 pF
2 1
CC1C=10 pF
2 1
CC31C=10 pF
2
1RRL1R=(1*22) Ohm
1
11
Figure 19 This is the complete active LO-balun. The different parts are A: differential
amplifier and B: current generator.
5.1.2.1.1 How the active LO-balun works
The basic function of the balun can be described in a classical balance scale sort of manner where the current generator represents the centre cone. One side of the “scale” has a constant well-defined “weight”, in this case the left side where the input is signal-grounded. The right side, or the side where unknown “weight” is placed, has the input LO-signal attached to it.
In other words, the current generator tries to keep a constant current which implies that the sum of the currents I1 and I2 in Figure 19 has to be constant. For example, if one consider the first half period of an input signal placed on port LO_in (number 1) in Figure 19 the rising sinus tries to increase the current I1 which will result in a decreasing I2 and therefore a decreasing collector current on the left side. Naturally the opposite of the above will be the case in the other half of the period.
37
5.1.2.1.2 Design of the active LO-balun
The first thing that had to be done was biasing the bases of the transistors in the differential stage. To do this a set of resistors were used (R21, R22, R31 and R32); the same base bias was used for all transistors and hence the values of the resistors are the same (the 67.7 and 55 ohm resistors in Figure 19). The differential stage utilizes negative feedback to stabilize the amplifier (R11 and R12 in figure). The reason this method was used is because it helps flattening the gain over frequency, and since the gain balance was important in the balun this was advantageous. The value of R11 and R12 (Rstab) was swept and chosen relatively high (300 Ohm) in order to guarantee stability even if there are process variations or if other parameters would vary. Another advantage of setting this value relatively high is that the noise current decreases with increasing Rstab.
Basically the value of RL1, RL2 and R4 controls the output power, or the gain, in one stage. Their value has been tuned in order to achieve the wanted 6-7 dBm into the mixer core and their present values can be seen in the schematic. But if for some reason one would like to change them, maybe to increase the out resistance, this can easily be done by performing a sweep like the one presented in Figure 20 where the values of R4 and RL1-2 have been swept. By choosing a point on one of the traces that crosses the blue horizontal line (or at least a neighbourhood of it), new values of the resistances can be achieved.
10 20 30 40 50 60 70 80 900 100
-25
-20
-15
-10
-5
0
5
10
-30
15
Rc
Out
put p
ower
, dB
m
Resindep(Res)=plot_vs(dBm(HB.Vut_mid1[1]),Rc)=7.0Rcurrent=60.000000
25.000
22 24 26 2820 30
3
4
5
6
7
8
9
2
10
Rcurrent=25.000
Rcurrent=45.000
Rcurrent=50.000
Rcurrent=55.000
Rcurrent=60.000
Rcurrent=65.000
Rcurrent=70.000
Rcurrent=75.000
Rcurrent=80.000
Rcurrent=85.000
Rcurrent=90.000
Rcurrent=95.000
Rcurrent=100.000Rcurrent=105.000Rcurrent=110.000Rcurrent=115.000Rcurrent=120.000Rcurrent=125.000Rcurrent=130.000Rcurrent=135.000
Rc
dBm
(HB
.Vut
_mid
1[1]
) Res
Resindep(Res)=plot_vs(dBm(HB.Vut_mid1[1]),Rc)=7.082Rcurrent=60.000000
25.000
7dBm
7dBm
Rc
Out power
Rcurrent
Increasing Rcurrent
Figure 20 This, somewhat extensive, figure shows how the values of RL1-2 and R4
(Rcurrent) affect the output power. The x-axis is different values of RL1-2 and for each value of RL1-2 the value of R4 has been swept; therefore each trace represents a different value of R4. This is only the output power in the right branch, but since the branches are equivalent there should not be any difference between them.
38
The reason there are two transistors in parallel is because this setup improved the balance of the circuit. Another reason is due to precaution. The circuit has performed well when the current generator generates a current around 90-100 mA. This will result in peak currents approaching 80 mA in the collectors of the differential stage and since the standard cell with emitter size 3x3x4516 um^2 is used, which only can handle 80 mA [57], this is motivated.
In order to fine tune the balance of the balun the value of C12 has been adjusted slightly compared to C11.
5.1.2.2 Passive LO-balun
The passive balun constructed is based on the classical 180-degree rat-race hybrid (Figure 21) that in normal cases uses microstrip lines. Here no microstrip lines are used. Instead, to reduce size, its lumped element equivalent circuit is used.
Figure 21 This picture represents a schematic sketch of a rat-race hybrid. ‘lambda’ is
the actual wavelength and Z0 is the system impedance. The four ports are the input (IN), the isolated port (ISO), the summation port (SIGMA) and the difference port (DELTA).
The lumped element representation of one microstrip line with characteristic impedance Z is shown in Figure 22. It can either be a tee-network or a pi-network. By using the design equations (found in the references stated earlier),
ZLω
= (1.76)
and
16 n w l× × , where n is the number of emitter fingers, w is the channel width and l is the channel length.
39
1CZω
= (1.77)
where 2 fω π= and where f is the actual frequency, the values of L and C is decided.
B
A
CC2C=C pF
CC3C=C pF
PortP3
PortP4
LL1
R=L=L nH
LL2
R=L=L nH
PortP2
PortP1 C
C1C=C pF
LL3
R=L=L nH
Figure 22 A: tee-representation of microstrip line and B: pi-representation of
microstrip line.
Now, by combining the pi- and tee-networks, each microstrip element of the rat-race hybrid in Figure 21 can be replaced by the lumped equivalent version. Notice that the value of Z is calculated by 02Z Z= where 0Z is the system impedance (in this case 50 Ohm).
After some simplification and combination of networks [43] [44] the final lumped element representation of the hybrid is shown in Figure 23.
40
VARVAR1485
L=7.578C=1.5157
EqnVar
CC4C=C pF
CC5C=C pF
CC1C=C pF
CC6C=C pF
CC2C=(2*C) pF
CC3C=(2*C) pF
LL2
R=L=L nH
LL3
R=L=L nH
LL4
R=L=L nH
LL1
R=L=L nH
Figure 23 The final lumped element representation of the rat-race hybrid using ideal
components.
Now, if the ISO is used as input and IN is terminated, the desired 180-degree phase difference is apparent between the DELTA and SIGMA ports (this will be shown in the result chapter).
5.1.2.2.1 Amplifier
A simple amplifier with decoupled emitter resistance [38] was designed to be used with the passive balun. This uses the same bias network as in the active balun, except some adjustments in values to tune the bias point and amplification. But this was made in the final design with layout components.
Also the same stabilization method as used in the active balun is used here. The design with ideal components can be seen in Figure 24.
41
b
c
e2e1
Tqhbt_3x3x45Tqhbt
temp=25area=135
e2e1
c
b
RR31R=Rstab Ohm
CC31C=20 pF
RR12R=55 Ohm
RR11R=67.7 Ohm
CC11C=20 pF
RR21R=7 Ohm
CC21C=20 pF
CC12C=20 pFPort
LO_inNum=1
PortLO_outNum=2
V_DCSRC1Vdc=5 V
LL1
R=L=5.0 nH
Figure 24 The LO-amplifier.
5.1.3 RF power amplifier
In order to have the desired -10 dBm RF-output power the signal has to be amplified. Therefore the power amplifier showed in Figure 25 [38] [48] had to bee designed.
It was obvious that this amplifier needed to have high linearity and therefore a survey in technical articles [47]-[56] was made to find linearization techniques. Many different techniques were found but most of them just were not worth the effort (for example predistortion). One technique, which is described in detail in appendix A, seemed very promising until it was discovered that this ruined the IP3 performance. Late in the design it turned out that, although simple, a large emitter area gave the best result [48]. This was realized by using four transistor cells in parallel. By increasing area the gain reduces, so compromises between these factors have been made but this has been considered further in the result section.
Otherwise the design of this was pretty much straight forward. The resistor R2 stabilizes the amplifier. The bias was set by, first sweeping a ideal current generator, choosing the optimal base current (which turned out to be 810 uA) and then designing the appropriate resistor network (R30 and R31). To have higher output power no collector or emitter resistors were used, just the RF-choke L1. L2 and L3 are just DC-feeders.
42
1
PortP1Num=1
1
PortP2Num=2
21
CC2C=C pF
21
RR2R=Rstab Ohm
VARVAR7
A=200Bias=14Rstab=10C=20
EqnVar
21
CC3C=C pF
1
1 2LL3
R=L=5.0 nH
1
2
V_DCSRC3Vdc=5 V
1
2
1RR30R=50 Ohm
11
2
1RR31R=18 Ohm
1
2
LL2
R=L=5.0 nH
1
2
V_DCSRC1Vdc=Bias V
1 2LL1
R=L=5.0 nH
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x5
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x4
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x3
temp=25area=A
e 2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x1
temp=25area=A
e2e1
c
b
Figure 25 The RF power amplifier. Observe that the area is reduced to 150 in the
final design with layout components.
5.1.4 IF-balun
As mentioned before the balun at the IF-input has to be bought and placed off-chip since the large
0 0
1 239.4 mmp
r r
vf f
λε ε μ μ
= = = (1.78)
in GaAs at this “low” frequency makes impossible to have the balun on the chip. In (1.78) the constants 12
0 8.854 10 F/mε −= × and 6 2
0 1.257 10 N/Aμ −= × were used and the values of rε and rμ used is 12.8 and 1 respectively.
In the diode mixer case the balun, or transformer, has to have a centre tap to where to “tap” the RF-signal. In ADS there are ideal transformers (TF3 and XFERTAP for example) but during simulations an ideal 180-degree hybrid with the RF “tapped” from the IN-port is used (this configuration can be seen in next section where the complete diode up-converter is shown). By using this hybrid instead of transformers, imbalances and losses can be simulated.
A transformer to be placed off-chip could be found at MiniCircuits. For instance their TC1-1T [46] (or TC1-1T+ for RoHS compliant) costs $1.19 for a quantity of 10-49 pieces.
5.1.5 The complete up-converter
To fulfil this design section about diode mixers all the pieces has to be put together. There are two configurations available, one with passive LO-balun and one with active LO-balun. The latter one is shown in Figure 26, the passive balun-version looks just about the same except that the LO-balun is different.
43
Vy
Vin2
Vin1
active LO-balun
Diode quad, mixer core
IF-transformer with RF "center-tap"
LC-filter, 1485 MHzRF-amp
activeLObalunLayout_TQTsTransistors_utan_slutsteg2_subcomponentX15
OutPrim e1
LO_in
OutPhas e1
PA5_subcomponentX9
PortRF_outNum=2
tqhbt2_dschD11w=DiodeScale um
tqhbt2_dschD12w=DiodeScale um
tqhbt2_dschD9w=DiodeScale um
tqhbt2_dschD10w=DiodeScale um
PortLO_inNum=3
PortIF_inNum=1
Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw10
LV=205 umLH=205 umS1=7 umN1=7W1=7 um
12
Tqhbt_mim_capTqhbt_mim_cap7
W1=50.8 umL1=35.9944 um
12
Hybrid180HYB2
PhaseBal=2GainBal=0.1 dBLoss=1 dB
IN
ISO
Figure 26 This is the complete diode up-converter. Notice how HYB2 is used as an
IF-transformer with the RF “center-tapped”.
To represent the off-chip RF-transformer an ideal 180-degree hybrid, with imbalances and loss added, was used. The RF-signal is tapped from the IN-port of the hybrid.
What has not been mentioned earlier is the filter preceding the RF-amplifier, this filter is simply a series LC-filter with resonance frequency at LO. This will help to suppress the LO-signal about 10 dB at the output.
It has also been discovered that an increase of the diode width to 50 um gives better overall performance at this stage.
44
5.2 FET-mixer
5.2.1 FET-mixer core
The basic topology of a resistive mixer is shown in Figure 27. It is a little bit simplified but will help to decide how to design the different parts. The filters used are usually simple low-pass, high-pass or band-pass filters, but other types of filters can be used. These filters can also act as matching network to some extension. To affect the performance of the mixer core, basically the following could be done:
• Decide the dimension for the transistor. In our case the width and number of fingers can be selected.
• Select a bias point.
• Design the filter and matching networks.
• Decide the LO power to use.
25_25MMWPHEMT_100_1218_4x25_eeX1
S
G
D
VbiasRR1
PortLO_IN DC_Block
DC_Block1
PortRF_OUT
PortIF_IN
HPF_ButterworthHPF1
LPF_ButterworthLPF1
Figure 27 Basic topology of a resistive FET mixer.
To do this, the mixer design guide with the “Single-Ended Mixer Characterization>IF Spect., Isolation, Conv. Gain, Port Impedances” simulation in ADS is used.
At the beginning the transistor dimensions were fixed at their standard values and the LO power was 0 dBm. One ideal high-pass filter and one ideal low-pass filter was used, the conversion gain was then investigated for different bias values and for some different transistor dimensions, scaled between -50 and 50% of the original value, the scaling was based on the manufacturing recommendations. The dimension and bias value that give the best performance is then used.
45
After this, the ideal filters are substituted by real ones. The complexity of the filters is as low as possible to keep the size down. The low-pass filter is for example substituted by a series LC circuit and becomes in fact a simple band--pass filter. The component values were calculated by using standard values from the layout library for the inductor, then the correspondingly capacitor
value is calculated from the well-known formula1
2cf LCπ= and the
performance is simulated to decide the best component values.
There is no special reason that a low-pass and high-pass filter was used for the ideal filters in the beginning, band-pass filters could also be used for example. The important is that the IF and RF ports are well isolated, that is the RF-signals sees a high impedance to the IF port and vice versa. To arrive with a good performance it is necessary to iterate the procedure described here with different filter types, different bias and transistor dimensions.
The simulation showed in Figure 28 shows that the best LO-power to use is between 10 to 15 dBm. This simulation also shows that the gate bias voltage impact on the conversion gain becomes negligible for LO-powers higher then about 10 dBm. This can be explained by that the LO-signal is strong enough to drive the transistor between an on- and off-state (see chapter 3.4) without bias.
-5 0 5 10 15 20 25-10 30
-60
-40
-20
-80
0
HB.P_LO
Con
vGai
n_U
p
-1.0 -0.5 0.0 0.5 1.0-1.5 1.5
-60
-40
-20
-80
0
HB.Gate_Bias
Con
vGai
n_U
p
Figure 28 The LO power (dBm) and gate bias impact on the conversion gain (dB);
the left graph shows that the gate bias impact can be neglected for P_LO > 10 dBm. For P_LO < 10 dBm the gate bias impact is quite important, referring to the right graph a value of about – 0.8 V is optimal.
Two more simulations is needed to decide the performance, simulation of the compression point, in the design guide for mixers “Single-Ended Mixer Characterization>N-db Gain Compression Point” as well as simulation of the linearity, in the design guide for mixers “Single-Ended Mixer Characterization>2nd- and 3rd-Order IMD and Conv. Gain”
Unfortunately the bias, dimensions and filters that give the best performance in one case do not give the best in another, therefore compromises must be done. Even simple things as the value of the bias feed resistor have a big impact on the linearity [29] performance of the mixer and needs to be carefully investigated. After an approximate design is done, it is a good idea to use optimization to get even better result.
46
A simulation of the IP3 for different gate bias and LO powers shows that the best values for the conversion gain are nearly optimal for the linearity too. Therefore the LO power is selected to 10 dBm and the gate bias to -0.8 V, for this values the conversion gain is about -8 dB and the IIP3 about 20.6 dBm. These optimal values are expected to change somewhat when real components are used, however, this is a good start.
Using the procedure just described an initial design of the mixer core with ideal components can be made and is shown in Figure 29.
VRF_outVload_drain
VIF_in
VLO_in
GD
S1 25_25MMWPHEMT_100_1218_4x25_eeX1
Wgu=widthNfgr=N
S
G
D
PortPort_IF_350Num=1
V_DCSRC1Vdc=Vbias V
CC18C=10 pF
I_ProbeI_LOinPort
Port_LONum=3
RR17R=1000 Ohm
PortPort_out_RFNum=2
I_ProbeI_RFout
LL10
R=1e-12 OhmL=3.8 nH
CC28C=1.3 pF
CC30C=2.3 pF
RR20R=1 mOhm
I_ProbeI_IFin
LL6
R=L=5 nH
CC22C=41.35 pF
RR19R=1 mOhm
Figure 29 The mixer core implemented with ideal passive components.
In Figure 29 the simple series LC circuit is used for the IF-signal and on the RF output a low-pass filter is used. Notice that on the initial design a high-pass filter was assumed here. However, simulation showed that this kind of filter is better; one reason is that higher order terms are highly attenuated and this is good for the linearity of the circuit. The small resistors on the drain are only for convergence purposes in the simulator and not of any practically meaning.
At the moment the isolation from the input IF port to the output RF port can be expected to be very poor since the IF-signal almost pass without any attenuation to the output port. The purpose is however to use two mixer cores in a balanced structure and the nature of balancing will take care of this problem.
5.2.1.1 Balancing of the cores
The balanced topology used is shown in Figure 30. There are three ideal hybrids used, HYB1 is used to split the LO-signal with 180 degrees of phase shift, HYB3 is in the same way used to split the input signal with 180 degrees of phase shift. Finally HYB2 is used to add the two outputs from the mixers in phase. This configuration will ideally suppress the LO and IF-signal on the output, however differences in the phase and gain balances means that some power of the LO and IF-signal will pass. Therefore, the variables for gain and phase balance can be used to estimate the demands on the hybrids.
47
How the output signal will look for different types of balancing can be calculated, it is however a little bit cumbersome and the interested reader is referred to appendix C, Maple calculation 5, where one calculation is made to show the idea. The results is shown in Table 2, apparently the case with both the LO and the IF-signals out of phase with 180-degrees is the most optimal and is therefore used.
LO-LO IF-IF RF out LO feed through
IF feed through
In phase In phase 22α
1 3922
α α+ 1 3922
α α+
In phase 180 out of phase
0 1 3
922
α α+ 0
180 out of phase
In phase 0 0 1 3
922
α α+
180 out of phase
180 out of phase
22α 0 0
Table 2, four possible configurations of the phase relationship between the two LO-signals and the two IF-signals and the resulting output, LO feed through and IF feed through.
1
PortLO_INNum=3
1
PortIF_INNum=1
4
31
2
Hybrid180HYB2
PhaseBal=RF_PBGainBal=RF_GB dBLoss=RF_loss dB
IN
ISO
12
1RR1R=50 Ohm
1
PortRF_OUTNum=2
3
21
FET_Start_DesignFET_Start_Design_sub2
Vbias=biasN=Nwidth=width
3
21
FET_Start_DesignFET_Start_Design_sub1
Vbias=biasN=Nwidth=width
4
31
2
Hybrid180HYB1
PhaseBal=LO_PBGainBal=LO_GB dBLoss=LO_loss dB
IN
ISO
4
31
2
Hybrid180HYB3
PhaseBal=IF_PBGainBal=IF_GB dBLoss=IF_loss dB
IN
ISO
1
1
Figure 30 Balancing of the mixer cores. The upper mixer core in the figure is feeded
with a LO and IF-signal with 0 degrees of phase shift relative to the LO and IF-input signal. The lower mixer core is feeded with a LO and IF-signal 180 degrees out of phase compared to the upper mixer core. This configuration suppresses the LO and IF feed through.
48
5.2.1.2 Alternative balanced mixer
A star like mixer, shown in Figure 31, was also investigated. However this mixer topology was far away as good as the balanced mixer discussed in chapter 5.2.1.1; the main drawback for this kind was the linearity performance. The simulated IIP3 was only about 10 dBm. The conversion gain of -4.2 dB and the LO suppression on the output of nearly -40 dB is good and on the pros side for this type of mixer. These results were for a gain difference of 0.5 dB and a phase difference of 2 degrees in the ideal baluns. The LO power was 10 dBm. However this mixer type was rejected in favor of the mixer type discussed in chapter 5.2.1.1 and will not be further discussed.
Hybrid180HYB4
PhaseBal=0.1GainBal=0.1 dBLoss=0 dB
IN
ISO
Hybrid180HYB3
PhaseBal=0.1GainBal=0.1 dBLoss=0 dB
IN
ISO
PortRF_balanced_inNum=1
RR8R=50 OhmRR2R=0.0001 Ohm
PortLO_balanced_inNum=3
RR4R=0.0001 Ohm
RR7R=50 Ohm
DC_FeedDC_Feed1
V_DCSRC1Vdc=Gbias V
DC_BlockDC_Block2
DC_BlockDC_Block1
DC_BlockDC_Block3
V_DCSRC2Vdc=Gbias V DC_Feed
DC_Feed2
GD
S1
25_25MMWPHEMT_100_1218_4x25_eeX3
Wgu=FwidthNfgr=N
S
G
D
GD
S125_25MMWPHEMT_100_1218_4x25_eeX5
Wgu=FwidthNfgr=N
S
G
D
Hybrid180HYB1
PhaseBal=0.1GainBal=0.1 dBLoss=0 dB
IN
ISO
PortIF_balanced_outNum=2
RR6R=50 Ohm R
R5R=0.0001 Ohm
DC_BlockDC_Block4
GD
S1
25_25MMWPHEMT_100_1218_4x25_eeX4
Wgu=FwidthNfgr=N
S
G
D
GD
S1
25_25MMWPHEMT_100_1218_4x25_eeX6
Wgu=FwidthNfgr=N
S
G
D
Figure 31 A star like mixer.
5.2.2 Active balun
The active balun with pHEMT transistors is almost the same as in the HBT case, the balun will be used for the splitting of the LO-signal. The emphasis is therefore on the differences in the design. The balun [16] [17] consist of a differential amplifier with one of the inputs grounded and the input signal on the other. The output from each drain then feed an amplifier stage.
5.2.2.1 The differential amplifier
The configuration of the differential amplifier is seen in Figure 32.
49
Vsrc
Vdrain1DiffOut1
Vin
DiffOut2 Vdrain2
VARstd_vars2
input_freq=1485 MHzRstab1=3000Rdrain1=150
EqnVar
I_ProbeIsrc
RR3R=6.6 Ohm
PLCPLC1
C=10.725 pFL=1.071 nH
RR1R=Rdrain1 Ohm
CC1C=1.0 pF
V_DCSRC1Vdc=5.0 V
P_1TonePORT1
Freq=input_freqP=polar(dbmtow(0),0)Z=50 OhmNum=1
CC3C=2.0 pF
RR7R=Rstab1
CC2C=1.0 pF
RR2R=Rdrain1 Ohm
RR8R=1
tom3_holderTMH3
I_ProbeIdrain2
I_ProbeIdrain1
tom3_holderTMH4
Figure 32 Differential amplifier as a part of the active balun.
There is no active current source used in the differential amplifier, instead a simple resistor (R3) in series with a parallel resonance circuit (PLC1) is used for the bias. The purpose of the resonance circuit is to make the sources look like an open circuit for the input frequency of 1485 MHz and therefore emulate an ideal current source. The design of the component values is quite straightforward, the values were chosen to allow the output signal to vary symmetrically about the bias point, make the circuit stable and to get a good phase and gain balance. The size of the transistors used is 100 um. The setup needed to simulate the parameters just discussed is shown in Appendix B in Figure 85.
5.2.2.2 The amplifier
The purpose of the amplifier is to amplify the signal from each drain in the differential amplifier so an appropriate gain is achieved. For this a simple common source amplifier is used, shown in Figure 33. Resistor R18 is for stabilization and R16 to set the bias point. Both resistors can be used to set the gain. The gain needs to be around 7-10 dB17, this gain was taken from the best LO power to feed the mixer with.
17 An input power of 10 dBm into the hybrid means that each output have half the input power (assuming no losses), or in dBm: 10 – 3 = 7 dBm.
50
DiffOut1
Vd
Vout1
RR18R=150 Ohm
+ TermTerm2
Z=50 OhmNum=2
CC9C=2 pF
tom3_holderTMH1
V_DCSRC8Vdc=5 V
RR16R=100 Ohm
I_ProbeIdrain4
Figure 33 Amplifier used in the active balun.
5.2.3 Passive balun
The design of the passive balun was exactly done as in the HBT case, but for a frequency of 1835 MHz instead. The balun was then optimized to get a low as possible phase and gain difference for the frequencies 350, 1485 and 1835 MHz, so the balun create a good suppression of the LO-signal as well as the IF-signal on the output when used in the balanced mixer.
5.2.4 RF power amplifier
A standard common source amplifier stage is used for the amplifier. In this amplifier not only the gain is important, even linearity is of great concern to meet the linearity requirements for the whole mixer circuit. From the simulations of the mixer core, the minimum requirements for the amplifier can be calculated. The most important steps in the design are to decide:
• The size of the transistors.
• Number of transistors to use in parallel.
• Bias and filtering.
The gain, IP3 and compression point was investigated for different sizes on the transistor. The bias point was fixed to a standard value found in the “materka” model for the transistor. The schematic of the amplifier used to simulate linearity and gain for is shown Figure 34, the small value resistors is only to help the simulator to converge to a solution and have no practically meaning.
51
Vout
VdrainVin
Vgate
VARVAR1
gate_bias=0.476drain_bias=3input_f req=1835 MHz
EqnVar
DC_FeedDC_Feed3
+ TermTerm2
Z=50 OhmNum=2
I_ProbeIout
materka_sddMFET1
Finger=FingerSize=Size
I_ProbeIsource
RR4R=0.001 Ohm
DC_FeedDC_Feed2
V_DCSRC2Vdc=drain_bias V
V_DCSRC1Vdc=gate_bias V
I_ProbeIin
P_1TonePORT1
Freq=input_f reqP=polar(dbmtow(10),0)Z=50 OhmNum=1
DC_BlockDC_Block1
RR6R=0.001 Ohm
RR5R=0.001 Ohm
I_ProbeIdrain
I_ProbeIgate DC_Block
DC_Block2
Figure 34 Circuit to decide the size of the transistor for good linearity and gain.
From the simulations it turned out that a size of 200 um (4x50) and three transistors in parallel is a good tradeoff between size and performance. When more than one transistor in parallel is used the gain and compression point increases, but the IP3 decreases. The purpose of using three transistors in parallel is therefore mainly to achieve an acceptable compression point.
To get the required gain and meet the demands on linearity, two stages are used in series. The main problem was to get a good linearity and many different theories (references [19] to [35]) and ideas were tested. For example: feedback and pre-distortion. More advanced solutions like feed forward or derivative superposition18 (references [32] to [35]) turned out to be to complex to implement in this work, but otherwise a good candidate when high linearity is needed, see [12] for a general discussion.
The final schematic design of the amplifier is shown in Figure 35. Here the “TOM3” model is used for the transistors instead of the “materka” model, due to that the “TOM3” model seems better for (non-)linearity predictions.
18 Reference [32] is an excellent way to become familiar with this interesting method.
52
EqnVar
Figure 35 The complete amplifier.
The Rstab resistors are used to set the gain and keep the amplifier stable. By changing the gain of the circuit even the linearity is affected. On the drain one parallel RLC circuit is used. At DC, the voltage source at 7 V feeds the drain of each transistor and together with the gate bias; the DC operating point is set. At the output frequency of 1835 MHz the LC tank is at resonance and the impedance seen between the drain and the DC voltage source is 250 ohm, the resistance helps to achieve better linearity [29][30]. On the input, output and between the stages, traditional decoupling capacitors are used. Simulations showed that better linearity can be achieved by short circuiting the 3 RFω frequency at the output. This is done by the series LC circuit SLC2. The simulation to decide the values for Rstab and Rdrain is shown in Figure 36. As can be seen, the Rdrain value for best IIP3 is about 200 ohm, but a higher Rdrain value means higher gain. A value of 250 ohm was selected. Rstab was then used to set the gain and IIP3, clearly a tradeoff is needed here. The amplifier is stable for all the simulated values of Rdrain and Rstab. The simulation setup can be seen in appendix in Figure 86.
53
50 100 150 200 2500 300
20
25
30
35
15
40
HB.Rstab
dB(S
(2,1
))
100 150 200 250 300 350 400 45050 500
10
15
20
25
5
30
HB.Rdrain
IIP3
Eqn IIP3=ip3_in(Vout,dB(S21)[0],{1,0},{2,-1},50)
100 150 200 250 300 350 400 45050 500
20
25
30
35
15
40
HB.Rdrain
dB(S
(2,1
))
50 100 150 200 2500 300
10
15
20
25
5
30
HB.Rstab
IIP3
Figure 36 Gain and IIP3 dependent on Rstab and Rdrain, in the upper graphs the
gain is shown both as a function of Rdrain as well as a function of Rstab, in the lower graphs the IIP3 dependency on Rstab and Rdrain is shown. The unit for IIP3 is dBm.
5.2.5 The complete up-converter
The complete up-converter is shown in Figure 37.
VLO2
VIF2
VLO1Vmout1
Vmout2
Output Amplif ierRatrace balunActiv e LO balun
VIF1
Ratrace_Lumped_1835_tolay_subcircuitX1
RR1R=50 Ohm
Output_Amplifier_tolay_subcircuitOutput_Amplifier_tolay_subcircuit1
PortRF_OUTNum=2
FET_Start_Design_tolay_subcircuitFET_Start_Design_tolay_subcircuit2
Vbias=biasN=NX=15width=width
Hybrid180HYB1
PhaseBal=0.1GainBal=0.1 dBLoss=0 dB
IN
ISO FET_Start_Design_tolay_subcircuitFET_Start_Design_tolay_subcircuit1
Vbias=biasN=NX=15width=width
Active_Balun_DiffAmp_with_Amps_tolay_subcircuitActive_Balun_DiffAmp_with_Amps_tolay_subcircuit1
RR2R=50 Ohm
PortIF_INNum=1
PortLO_INNum=3
Figure 37 The complete up-converter with the ideal components substituted by the
real ones.
Clearly, there is not much changes compared to the design used in the start, shown in Figure 30. The only differences is now that the LO balun and the RF balun is substituted by the ones just developed, and the addition of an output amplifier for the RF-signal.
54
6 Results
6.1 Diode mixer
6.1.1 Active LO-balun
In the following subsections the simulated results of the active HBT LO-balun will be presented. Both circuits using ideal passive components and the final “layout circuits” are simulated. The parameters simulated are: gain difference and gain; phase balance and finally stability. Observe that it is the large-signal S-parameters that have been used. Note also that the strange notation ‘$A_balun_layout’ that shows up in some of the graphs is an ADS feature and is used to refer to aliases of datasets.
6.1.1.1 Gain difference and gain
Based on simulation experiments involving the whole mixer setup it has been concluded that the most important parameter of the LO-balun is the gain difference, since it affects the LO cancellation most. The gain difference in the circuit using ideal passive components is shown in Figure 38 and for the circuit using “layout components” in Figure 39. In both cases the value of the bypass capacitor C12 in Figure 24 on page 41 has been adjusted to tune the gain difference.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-0.8
0.1
Freq, GHz
GD
1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.541.34 1.56
0.02
0.03
0.04
0.05
0.06
0.07
0.01
0.08
Freq, GHz
GD
Figure 38 The gain difference (GD) in dB plotted versus frequency (Freq) in Hz for
the circuit with ideal passive components.
55
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
-0.4
-0.3
-0.2
-0.1
0.0
-0.5
0.1
Freq, GHz
GD
_lay
out
1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.541.36 1.56
0.060
0.065
0.070
0.075
0.080
0.085
0.055
0.090
Freq, GHz
GD
_lay
out
Figure 39 The gain difference (GD_layout) in dB plotted versus frequency (Freq) in
Hz for the circuit with “layout components”.
As mentioned earlier the desired LO-output power is supposed to be around 6-7 dBm which implies that a forward transmission gain of 6-7 dB is needed in each side of the differential amplifier in the balun. As seen in Figure 40, this is the case for the circuit using ideal passive components. Also the circuit using “layout components” matches this requirement, as seen in Figure 41. If desired, the amplification can be further tuned by changing the value of the resistor in the current generator.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
4.5
5.0
5.5
6.0
6.5
4.0
7.0
Freq, GHz
dB(H
B.S
(2,1
))dB
(HB
.S(3
,1))
Figure 40 The input to output gain in dB over frequency for each side of the
differential amplifier in the LO-balun. This is the circuit using ideal passive components.
56
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
4.5
5.0
5.5
6.0
6.5
7.0
4.0
7.5
$A_balun_layout..Freq, GHz
dB($
A_ba
lun_
layo
ut..H
B.S(
2,1)
)dB
($A_
balu
n_la
yout
..HB.
S(3,
1))
Figure 41 The input to output gain in dB over frequency for each side of the
differential amplifier in the LO-balun. This is the circuit using “layout components”.
6.1.1.2 Phase balance
Another important parameter is of course the phase balance between the two outputs of the balun. This is plotted in Figure 42 and Figure 43. The deviation from the desired 180 degree is somewhere between 2 to 3 degrees, which is fully acceptable.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
182
183
184
185
186
187
188
181
189
Freq, GHz
PB
Figure 42 The phase balance (PB) in degrees over frequency (Freq) for the circuit
using ideal passive components.
57
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
183
184
185
186
187
182
188
$A_balun_layout.Freq, GHz
PB
_lay
out
Figure 43 The phase balance (PB_layout) in degrees over frequency
($A_balun_layout.Freq) in for the circuit using “layout components”.
6.1.1.3 Stability
The stability [2] of the circuit was determined by using the Rollett factor, k, and Δ . As seen in Figure 44 the circuit is unconditionally stable since k>1
and Δ <1.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
4.90
4.95
5.00
5.05
4.85
5.10
0.36
0.38
0.40
0.42
0.34
0.44
Freq, GHz
LSdelta_P
21LSK
_P21
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.2 2.0
20
30
40
10
50
0.25
0.30
0.35
0.40
0.20
0.45
Freq, GHz
LSdelta_P
31LSK
_P31
Figure 44 The stability factors for each side of the differential step in the balun. The
Rollett factor k is the blue plots (LSK_P21 and LSK_P31) and Δ is the red plots (LSdelta_P21 and LSdelta_P31).
6.1.2 Passive LO-balun
Also the passive LO-balun was simulated, both a version with ideal component and another with the “layout components”. The results reported below is the loss difference between the in and out ports, phase difference between the two outputs and finally some port to port isolation is presented.
58
6.1.2.1 Loss difference
Considering the case where ideal components were used there is only, as seen in Figure 45, the minimum 3 dB loss between ports. The loss difference is practically zero. A more interesting result should be the one for the “layout components” presented in Figure 46 where the loss is slightly higher and the difference, which is shown in Figure 47, is in the upper region of what is acceptable for this application. As seen in the close up around the frequency of interest the loss difference appears to be just below 0.3 dB.
loss1freq=dB(S(2,4))=-3.010
1.490GHz
0.5 1.0 1.50.0 2.0
-10
-8
-6
-4
-2
-12
0
freq, GHz
dB(S
(2,4
))
loss1
dB(S
(3,4
))loss1freq=dB(S(2,4))=-3.010
1.490GHzloss2freq=dB(S(2,1))=-3.010
1.490GHz
0.5 1.0 1.50.0 2.0
-15
-10
-5
-20
0
freq, GHz
dB(S
(2,1
))
loss2
dB(S
(3,1
))
loss2freq=dB(S(2,1))=-3.010
1.490GHz
Figure 45 The input to output losses in the hybrid. The left picture is the ISO-port to
SIGMA and DELTA losses. In the right picture there is the IN-port to the SIGMA and DELTA port losses. This shows the simulations of the circuit with ideal components.
loss1freq=dB(S(2,4))=-4.146
1.490GHz
0.5 1.0 1.50.0 2.0
-8
-7
-6
-5
-9
-4
freq, GHz
dB(S
(2,4
))
loss1
dB(S
(3,4
))
loss1freq=dB(S(2,4))=-4.146
1.490GHzloss2freq=dB(S(2,1))=-4.398
1.490GHz
0.5 1.0 1.50.0 2.0
-10
-8
-6
-12
-4
freq, GHz
dB(S
(2,1
))
loss2
dB(S
(3,1
))
loss2freq=dB(S(2,1))=-4.398
1.490GHz
Figure 46 As in Figure 45 but with the circuit using “layout components”.
59
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0
-2
0
2
4
6
-4
8
freq, GHzdb
(S(3
,4))
-db(
S(2,
4))
db(S
(3,1
))-d
b(S(
2,1)
)
1.40 1.45 1.50 1.551.35 1.60
-0.5
0.0
0.5
-1.0
1.0
freq, GHz
db(S
(3,4
))-d
b(S(
2,4)
)db
(S(3
,1))
-db(
S(2,
1))
Figure 47 The loss difference (about 0.2 to 0.3 dB) between the two outputs SIGMA
and DELTA with reference to one of the input ports ISO and IN. The trace in blue refers to IN and the one in red refers to ISO.
6.1.2.2 Phase balance
In the ideal case there is not so much to say about the phase balance except maybe that it is perfect at the desired frequency, as seen in Figure 48.
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0
-160
-140
-120
-100
-80
-60
-40
-20
-180
0
freq, GHz
Pha
seD
iff
m1
m1freq=PhaseDiff=-179.999
1.490GHz
Figure 48 The phase difference between the SIGMA and DELTA ports. This is the
circuit with ideal components.
Also the case with “layout components” the deviation in phase is minimal, which can be seen in Figure 49.
60
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0
-180
-160
-140
-120
-100
-80
-60
-40
-20
-200
0
freq, GHz
Pha
seD
iff
m1
m1freq=PhaseDiff=-180.080
1.490GHz
Figure 49 The phase difference between the SIGMA and DELTA ports. This is the
circuit with “layout components”.
6.1.2.3 Port to port isolation
Two other important parameters of the hybrid are the input-input isolation and output-output isolation. This is reported in Figure 50 for the ideal case and in Figure 51 for the “layout component” case. A possible improvement could be to optimize the components used in the latter case, this in order to shift the peak in isolation so that it appears at LO frequency.
0.5 1.0 1.50.0 2.0
-50
-100
0
freq, GHz
dB(S
(4,1
))
iso1
dB(S
(3,2
))
iso1freq=dB(S(4,1))=-96.975
1.480GHz
Figure 50 SIGMA-DELTA isolation (dB(S(3,2))) and IN-ISO isolation (dB(S(4,1))
which is actually covered by dB(S(3,2))). This is the ideal circuit.
61
0.5 1.0 1.50.0 2.0
-40
-20
-60
0
freq, GHz
dB(S
(4,1
))
iso1dB
(S(3
,2))
iso1freq=dB(S(4,1))=-37.448
1.480GHz
Figure 51 SIGMA-DELTA isolation (dB(S(3,2))) and IN-ISO isolation (dB(S(4,1))
which is actually covered by dB(S(3,2))). This is the circuit with “layout components”.
6.1.3 LO amplifier
Only the forward transmission gain will be reported as a result of the LO amplifier, this is shown in Figure 52, and this is the simulation on the circuit using “layout components” and microstripline.
1.2 1.4 1.6 1.81.0 2.0
8
10
12
14
6
16
freq, GHz
dB(S
(2,1
))
m2
m2freq=dB(S(2,1))=12.588
1.484GHz
Figure 52 The forward transmission gain for the LO amplifier using “layout
components” and microstripline.
As seen in Figure 52 the present configuration gives an amplification of about 12.6 dB but this is easily tuned by changing the value of the emitter resistance.
62
6.1.4 RF power amplifier
Except the forward transmission gain both the linearity and stability of the output amplifier is of interest. The results reported below are based on the design with “layout components” without microstrip. Also a minor change in the value of resistor R31 since Figure 25 on page 42 has been made to adjust the bias slightly.
6.1.4.1 Forward transmission gain
A large-signal S-parameter simulation was performed over frequency and as seen in Figure 53 the gain of the amplifier is about 18.4 dB at RF frequency. Actually this needs to be a few dB higher in order to manage an output power of 10 dBm (as seen in next section about the complete up-converter). Unfortunately the S21-peak is around 700 MHz.
1 2 30 4
10
15
20
5
25
Freq, GHz
dB(S
(2,1
))
RFLO
RFindep(RF)=plot_vs(dB(S(2,1)), Freq)=18.388=0
1.800E9
LOindep(LO)=plot_vs(dB(S(2,1)), Freq)=19.913=0
1.500E9
Figure 53 Forward transmission gain (in dB) of the power amplifier.
6.1.4.2 Linearity
Both 1-dB compression point and input third-order interception point (IIP3) has been simulated and in this case the 10-dB rule of thumb actually seems to hold. The 1-dB compression point is 16.2 dB and IIP3 is 26.3 dB at RF-frequency. IIP3 has been simulated using the ADS design guide ‘2-Tone Nonlinear Simulations>Spectrum, Gain, TOI and 5thOI Points’ found in the amplifier section and the simulation setup can be seen Figure 83 in the appendix. Actually the resulting IIP3 might be unnecessary large in the final design and by reducing the transistor area this point is decreased. By decreasing the area would also increase the gain and thus approaching the goal of -10 dBm output power. The simulation setup used for compression point is shown in Figure 84 also in appendix.
63
6.1.4.3 Stability
Just for the sake of completeness the stability plots are shown in Figure 54 and as can be seen the circuit is unconditionally stable over a large frequency span.
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
4
6
8
10
12
14
2
16
0.30
0.35
0.40
0.45
0.25
0.50
Freq, GHz
LSdelta_P21LSK_
P21
Figure 54 The Rollett factor, k, (LSK_P21) and Δ (LSdelta_P21) over frequency.
6.1.5 The complete up-converter
To fulfil the result section about the diode mixer the whole up-converter needs to be simulated. The parameters that have been tested are conversion gain, RF-output power, isolation, 1-dB compression point and IIP3. Also the two mixer topologies have been compared with each other. The diodes that have been used in both topologies are the Schottky diodes supplied in the TQTHBT2 v1.41 design kit, their emitter width is set to 50 um.
6.1.5.1 Conversion gain, output power and suppression
Conversion gain, output power and LO to RF suppression can all be read from the output power spectrum of the mixer. This spectrum for the mixer using active LO-balun is shown in Figure 55 and for the passive LO-balun version it is shown in Figure 56. This is for an input power of -20 dBm, in Figure 57 and Figure 58 is the result when using an input power of -5 dBm.
64
LOfreq=IF_spectrum=-35.611
1.485GHzRFfreq=IF_spectrum=-14.138
1.835GHzIFfreq=IF_spectrum=-13.778
1.135GHz
1 2 3 40 5
-200
-150
-100
-50
-250
0
freq, GHz
Out
put s
pect
rum
, dBm
LORFIF
LOfreq=IF_spectrum=-35.611
1.485GHzRFfreq=IF_spectrum=-14.138
1.835GHzIFfreq=IF_spectrum=-13.778
1.135GHz
EqnSupression_LOtoRF=LO-RF Eqn RF_output_power=RF
Eqn Conversion_Gain=10*log(dbmtow(RF)/dbmtow(P_IF))
Supression_LOtoRF-21.474
RF_output_power-14.138
Conversion_Gain5.862
EqnP_IF=-20
Figure 55 Output spectrum of the mixer with active LO-balun with an input IF at -20 dBm.
LOfreq=IF_spectrum=-47.900
1.485GHzRFfreq=IF_spectrum=-17.067
1.835GHzIFfreq=IF_spectrum=-16.324
1.135GHz
1 2 3 40 5
-200
-150
-100
-50
-250
0
freq, GHz
Out
put s
pect
rum
, dBm
LORFIF
LOfreq=IF_spectrum=-47.900
1.485GHzRFfreq=IF_spectrum=-17.067
1.835GHzIFfreq=IF_spectrum=-16.324
1.135GHz
EqnSupression_LOtoRF=LO-RF Eqn RF_output_power=RF
EqnConversion_Gain=10*log(dbmtow(RF)/dbmtow(P_IF))
Supression_LOtoRF-30.833
RF_output_power-17.067
Conversion_Gain2.933
Eqn P_IF=-20
Figure 56 Output spectrum of the mixer with passive LO-balun with an input IF at -20 dBm.
Notice that the RF-output needs more amplification to fulfil the requirement.
65
LOfreq=IF_spectrum=-35.813
1.485GHzRFfreq=IF_spectrum=1.054
1.835GHzIFfreq=IF_spectrum=1.418
1.135GHz
1 2 3 40 5
-100
-50
0
-150
50
freq, GHz
Out
put s
pect
rum
, dBm
LO
RFIF
LOfreq=IF_spectrum=-35.813
1.485GHzRFfreq=IF_spectrum=1.054
1.835GHzIFfreq=IF_spectrum=1.418
1.135GHz
EqnSupression_LOtoRF=LO-RF Eqn RF_output_power=RF
EqnConversion_Gain=10*log(dbmtow(RF)/dbmtow(P_IF))
Supression_LOtoRF-36.867
RF_output_power1.054
Conversion_Gain6.054
Eqn P_IF=-5
Figure 57 Output spectrum of the mixer with active LO-balun with an input IF at -5 dBm.
LOfreq=IF_spectrum=-55.635
1.485GHzRFfreq=IF_spectrum=-1.893
1.835GHzIFfreq=IF_spectrum=-1.088
1.135GHz
1 2 3 40 5
-100
-50
0
-150
50
freq, GHz
Out
put s
pect
rum
, dBm
LO
RFIF
LOfreq=IF_spectrum=-55.635
1.485GHzRFfreq=IF_spectrum=-1.893
1.835GHzIFfreq=IF_spectrum=-1.088
1.135GHz
EqnSupression_LOtoRF=LO-RF Eqn RF_output_power=RF
EqnConversion_Gain=10*log(dbmtow(RF)/dbmtow(P_IF))
Supression_LOtoRF-53.742
RF_output_power-1.893
Conversion_Gain3.107
Eqn P_IF=-5
Figure 58 Output spectrum of the mixer with passive LO-balun with an input IF at -5 dBm.
As can be seen the performance is much better with an input IF at -5 dBm, and -5 dBm is more close to the real value for this application.
66
6.1.5.2 1-dB compression point and IIP3
For the active LO-balun version the 1-dB compression point occurs at a IF-input power level of 14.9 dBm which corresponds to a IF voltage of 1.65 V. The conversion gain at this point is 4.7 dB. The passive versions 1-dB compression point occurs at 12.5 dBm of input power, this point corresponds to a voltage of 1.46 V and a conversion gain of 2.5 dB.
As for the IIP3 the simulated values achieved are 8.6 dBm for the active version and 10.3 dBm for the passive version. However, the question is if those values can be trusted. First it deviates from the 10-dB rule of thumb and also the diodes used are reported to perform badly in 2-tone simulations.
The increased IF-power does not affect the compression point.
All information above has been gathered by using the ADS design guide: ‘Mixers>Single-Ended Mixer Characterization>N-dB Gain Compression Point’ and ‘Mixers>Single-Ended Mixer Characterization>2nd- and 3rd-Order IMD and Conv. Gain’.
67
6.1.5.3 Summary
Parameter Requirement Up-converter with active balun
Up-converter with passive balun
Conversion gain ≥ 10 dB 5.7 dB 2.9 dB
Ouput power in RF-tone
≥ -10 dBm -14.1 dBm -17.1 dBm
Suppression ≤ -20 dB -21.5 dB -30.8 dB
IIP3 ≥ 24 dBm 8.6 dBm 10.3 dBm
Compression point, P-1dB
N/A 14.9 dBm 12.5 dBm
Table 3, the -20 dBm IF-power version.
Parameter Requirement Up-converter with active balun
Up-converter with passive balun
Conversion gain ≥ 10 dB 6.1 dB 3.1 dB
Ouput power in RF-tone
≥ -10 dBm 1.1 dBm -1.9 dBm
Suppression ≤ -20 dB -36.9 dB -53.7 dB
IIP3 ≥ 24 dBm N/A N/A
Compression point, P-1dB
N/A 14.9 dBm 12.5 dBm
Table 4, the -5 dBm IF-power version.
68
6.2 FET mixer
6.2.1 LO balun
For the baluns the gain, gain difference and phase difference is the most important parameters and the results from a harmonic balance (HB) and a large-signal S-parameter (LSSP) simulation are presented for the active balun. Then the results from a S-parameter (SP) simulation is shown for the passive balun.
6.2.1.1 HB simulation of gain, gain and phase difference for the active balun
Note that the input power used for the simulations is 0 dBm, therefore the output power in dBm is equal to the gain in dB.
2 4 6 8 100 12
-50
-40
-30
-20
-10
0
-60
10
f req, GHz
dBm
(HB
.Vou
t1)
2 4 6 8 100 12
-150
-100
-50
0
50
100
150
-200
200
f req, GHz
phas
e(H
B.Vo
ut1)
2 4 6 8 100 12
-50
-40
-30
-20
-10
0
-60
10
f req, GHz
dBm
(HB
.Vou
t2)
2 4 6 8 100 12
-150
-100
-50
0
50
100
150
-200
200
f req, GHz
phas
e(H
B.Vo
ut2)
f req
0.0000 Hz1.485 GHz2.970 GHz4.455 GHz5.940 GHz7.425 GHz8.910 GHz10.40 GHz
dBm(HB.Vout1)
<inv alid>8.634
-18.990-20.068-38.475-40.985-45.491-55.759
...se(HB.Vout1)
0.00027.127
-158.180-169.199-93.380172.295-92.011-29.975
dBm(HB.Vout2)
<inv alid>8.638
-17.997-20.853-36.261-39.814-45.599-61.061
...se(HB.Vout2)
0.000-152.351-151.740
14.284-72.954-1.458
-100.192154.966
GainDif f
<inv alid>0.0040.992
-0.7852.2151.172
-0.108-5.302
PhaseDif f
0.000-179.478
6.441183.48320.426
-173.753-8.181
184.941
Figure 59 The gain, gain balance and phase balance for the active amplifier with ideal components.
69
2 4 6 8 100 12
-50
-40
-30
-20
-10
0
-60
10
f req, GHz
dBm
(HB
.Vou
t1)
2 4 6 8 100 12
-150
-100
-50
0
50
100
150
-200
200
f req, GHz
phas
e(H
B.V
out1
)
2 4 6 8 100 12
-50
-40
-30
-20
-10
0
-60
10
f req, GHz
dBm
(HB
.Vou
t2)
2 4 6 8 100 12
-150
-100
-50
0
50
100
150
-200
200
f req, GHz
phas
e(H
B.V
out2
)
f req
0.0000 Hz1.485 GHz2.970 GHz4.455 GHz5.940 GHz7.425 GHz8.910 GHz10.40 GHz
dBm(HB.Vout1)
<inv alid>7.518
-24.625-25.750-43.681-46.377-55.114-71.807
...se(HB.Vout1)
0.00024.884
-138.823-174.713-108.513172.111
-126.177-125.986
dBm(HB.Vout2)
<inv alid>7.526
-19.908-26.711-46.763-46.808-55.262-85.533
...se(HB.Vout2)
0.000-155.324-159.439
7.485-76.203-13.754
-110.033123.926
GainDif f
<inv alid>0.0084.717
-0.961-3.083-0.432-0.148
-13.726
PhaseDif f
0.000-180.207-20.615182.19832.310
-185.86616.144
249.912
Figure 60 The gain, gain balance and phase balance for the active amplifier with layout components.
Figure 59 and Figure 60 shows that the gain difference is very good. The phase difference is less then 0.6 degrees at 1485 MHz. The gain is a little bit lower (~1.1 dB) when real layout components are used; this is expected due to the resistive losses in the inductors and capacitors.
6.2.1.2 LSSP simulation of gain, gain- and phase difference versus frequency for the active balun
2.0E8
4.0E8
6.0E8
8.0E8
1.0E9
1.2E9
1.4E9
1.6E9
1.8E9
0.0
2.0E9
-25-20-15
-10-5
05
10
-30
15
input_freq
dB(S
21)
2.0E8
4.0E8
6.0E8
8.0E8
1.0E9
1.2E9
1.4E9
1.6E9
1.8E9
0.0
2.0E9
-25-20-15
-10-5
05
10
-30
15
input_freq
dB(S
31)
2.0E8
4.0E8
6.0E8
8.0E8
1.0E9
1.2E9
1.4E9
1.6E9
1.8E9
0.0
2.0E9
0
5
10
-5
15
input_freq
Gai
n di
ffere
nce
(dB
)
2.0E8 4.0E8 6.0E8 8.0E8 1.0E9 1.2E9 1.4E9 1.6E9 1.8E90.0 2.0E9
140
150160170
180190
200210
130
220
input_freq
Pha
se d
iffer
ence
(deg
rees
)
70
Figure 61 Gain, gain difference and phase difference between the input and the two output ports versus frequency. From the ideal circuit (Red) and with layout components (Blue).
Figure 61 shows that the performance for the ideal circuit as well as the circuit with layout components seems to match quite well for the frequency band 0.1 GHz to 2 GHz.
6.2.1.3 LSSP simulation of the isolation and reverse transmission versus frequency for the active balun.
2.0E8
4.0E8
6.0E8
8.0E8
1.0E9
1.2E9
1.4E9
1.6E9
1.8E9
0.0
2.0E9
-160
-140
-120
-100
-80
-180
-60
input_freq
dB(S
(3,2
)[0])
dB(S
(2,3
)[0])
2.0E8
4.0E8
6.0E8
8.0E8
1.0E9
1.2E9
1.4E9
1.6E9
1.8E9
0.0
2.0E9
-180
-160
-140
-120
-100
-200
-80
input_freq
dB(S
(1,2
)[0])
dB(S
(1,3
)[0])
Figure 62 Isolation between the two output ports and the reverse transmission. This
is for the active amplifier with layout components.
Figure 62 shows that the isolation between the output ports is less then -60 dB and the reverse transmission is less then –80 dB.
6.2.1.4 SP simulation of gain, gain- and phase differences versus frequency for the passive balun.
For the passive balun the gain and phase balance is important, especially at the frequency of 1485 MHz so the LO is well suppressed, but also at the IF and RF frequency. In Figure 63 the gain, phase, gain difference and phase difference is simulated between 0.1 GHz to 4 GHz. The red traces are for ideal components and the blue with layout components. Note that some optimization have been done for the case with layout components, therefore the graphs is shifted in relation to each other. In Table 5 the exact values for the most interesting frequencies are presented. The high loss of about 6 dB at the RF frequency is due to the fact that the inductor values were scaled down, and the capacitors values scaled up by a factor of approximately two to decrease the area used by the inductors.
71
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-30
-20
-10
-40
0
freq, GHz
dB(S
21)
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-30
-20
-10
-40
0
freq, GHz
dB(S
24)
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-150
-100
-50
0
50
100
150
-200
200
freq, GHz
phas
e(S
21)
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-150
-100
-50
0
50
100
150
-200
200
freq, GHz
phas
e(S
24)
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-22.5-20.0-17.5-15.0-12.5-10.0
-7.5-5.0-2.50.02.55.07.5
-25.0
10.0
freq, GHz
Gai
n di
ffere
nce
(dB
)
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-75-252575
125175225275325
-125
350
freq, GHz
Pha
se d
iffer
ence
(deg
rees
)
Figure 63 Simulation of gain, phase, gain difference and phase difference for the
ratrace balun. With ideal components (Red) and with layout components (Blue).
Frequency Gain difference in dB Phase difference in degrees
350 MHz -0.13 (0.19) -10.56 (-9.82)
1485 MHz -0.17 (2.23) 0.09 (1.22)
1835 MHz 0.29 (0.00) -8.09 (-0.01) Table 5, gain difference and phase difference at the most important frequencies for
“layout components”. The values within parenthesis are for ideal components.
6.2.2 RF amplifier
For the output amplifier the gain and linearity is important, therefore simulations for gain, compression point and IIP3 was made.
72
6.2.2.1 LSSP simulation of gain
5.0E81.0E91.5E92.0E92.5E93.0E93.5E90.0 4.0E9
-80
-60
-40-20
0
20
-100
40
input_freqdB
(S21
)
1.45E9
1.50E9
1.55E9
1.60E9
1.65E9
1.70E9
1.75E9
1.80E9
1.85E9
1.90E9
1.95E9
2.00E9
2.05E9
1.40E9
2.10E9
15
20
25
30
35
10
40
input_freq
dB(S
21)
Figure 64 Gain for the output amplifier. With ideal components (Red) and with layout
components (Blue).
6.2.2.2 XDB simulation of the P-1dB compression point
5.0E8 1.0E9 1.5E9 2.0E9 2.5E9 3.0E9 3.5E90.0 4.0E9
-5
0
5
10
15
20
25
-10
30
input_freq
P-1
dB c
ompr
essi
on p
oint
(dBm
Figure 65 The P-1dB compression point. For ideal components (Red) and with layout
components (Blue).
6.2.2.3 TOI simulation of the IIP3
5.0E8 1.0E9 1.5E9 2.0E9 2.5E9 3.0E9 3.5E90.0 4.0E9
10
20
30
40
0
50
input_freq
IIP3
(dB
m)
Figure 66 Input third-order interception point, IIP3 for ideal components (Red) and
with layout components (Blue).
6.2.2.4 Summary
73
Gain P-1dB IIP3 Ideal components
29.8 dB -2.9 dBm 17.4 dBm
Layout components
29.2 dB -2.4 dBm 15.4 dBm
Table 6, the important parameters for the output amplifier at the output frequency of 1835 MHz.
6.2.3 The complete up-converter
This section shows the simulated performance of the complete up-converter. In the summary section the simulation results and the requirements are compared to see how well the mixer performs. In the following simulations a LO power of 0 dBm, IF power of -20 dBm and a gate bias of -0.9 V is assumed unless otherwise specified. Small changes in the LO power is however expected to occur so the same simulations were done for a LO power of -2.5 dBm and 2.5 dBm to see how they affect the results, this is shown in the summary section in Table 7.
6.2.3.1 Conversion gain, port impedances, port to port isolation, and suppression simulation.
1.135 GHz -7.509 0.013 / 53.344
Zload50.0 / 0.0
1.835 GHz 11.040 0.113 / -117.948
Input Frequency RF voltage RF Pavailable
INPUT DATA
350.0 MHz 0.015 / 21.915 -20.000
LO Frequency LO voltage LO Pavailable
1.485 GHz 0.621 / -3.530 0.000
Output Frequency
P_LO2IF
58.5
P_LO2RF
23.6
P_RF2IF
58.5
LO to Outputisolation (dB)
LO to Inputisolation (dB)
PORT-TO-PORT ISOLATIONInput to Outputisolation (dB)
Eqn Z0=50Ref erence Impedance f or Rho(ref election coef f icient) andVSWR calculations.
1.84 GHz 59.50 - j39.42 0.35 / -56.65 2.07
1.13 GHz 3.59 - j16.15 0.88 / -1.44E2 15.39
1.49 GHz 1.95E2 - j7.46E2 0.97 / -7.18 61.22
350. MHz 13.21 + j7.13 0.59 / 1.63E2 3.87
Frequency ImpedanceReflection Coefficient VSWR
Looking into the RF (Input) Port:
ImpedanceReflection Coefficient VSWR
Looking into the LO Port:
ImpedanceReflection Coefficient VSWR
Looking into the IF (Output) Port at thedownconversion frequency:
ImpedanceReflection Coefficient VSWR
Looking into the IF (Output) Port at theupconversion frequency:
Frequency
Frequency
Frequency
Down Conversion Gain (dB)
Output voltage
Output Frequency
Up Conversion Gain (dB)
Output voltage
Eqn Suppression=dBm(mix(HB.Vload,{1,0}))-dBm(mix(HB.Vload,{1,1}))
freq
<invalid>Hz
Suppression
-49.512
Figure 67 Conversion gain, port-to-port isolation, impedances and suppression. The
up conversion gain is 11 dB and the LO suppression is -49.5 dB.
74
6.2.3.2 TOI simulation.
Conversion Gain, dB
-24.50 -7.50
Output Power in BothFundamentals dBm
18.47 18.48
Low and High Side Output TOI Points, dBm
25.97 25.98
Low and High Side Input TOI Points, dBm
These become invalid as the mixer is driven into compression. If the low and high side IP3sare not nearly equal, the mixer is either driven too hard or you need to increase the max order, LO order, RF order, and possibly include oversampling in the HB controller.
The conversion gain is calculated from the total fundamental input and output powers.
91.962 91.983
Carrier to 3rd order IMD ratio LSB USB
1.1347
1.1348
1.1349
1.1350
1.1351
1.1352
1.1353
1.1346
1.1354
-150
-100
-50
-200
0
freq, GHzS
pect
rum
, dB
m
Output Spectrum (Down Conversion)
3rd Order IMD
37.02 37.04
Low and High Side Output TOI Points, dBm
25.97 25.99
Low and High Side Input TOI Points, dBm
91.969 91.995
Carrier to 3rd order IMD ratio LSB USB
1.8347
1.8348
1.8349
1.8350
1.8351
1.8352
1.8353
1.8346
1.8354
-150
-100
-50
-200
0
freq, GHz
Spec
trum
, dBm
Output Spectrum (Up Conversion)
Fundamental Output Freqs.(Up Conv ersion)
Fundamental Output Freqs.(Down Conv ersion)
3rd Order IMD
-5.95 11.05
Down Conversion Up Conversion
These become invalid as the mixer is driven into compression. If the low and high side Iare not nearly equal, the mixer is either driven too hard or you need to increase the max order, LO order, RF order, and possibly include oversampling in the HB controller.
Output Power in BothFundamentals dBm
Conversion Gain, dB The conversion gain is
calculated from the total fundamental input and output powers.
Figure 68 The TOI simulation. The IIP3 is almost 26 dBm.
6.2.3.3 P-1dB compression point
350.0 MHz 0.833 15.185 10.147
dB compression input powerand associated conversion gain
0.621 / -3.531 0.000
LO voltage LO Power @ LOfreq (dBm - 50 ohms)
1.0
50.000 + j0.000
Load Impedance R + jX
1.0 dB gain compression Conversioninput power level (dBm) gain
Mix_SE_PNdB
freq
1.135 GHz
V_dwnconv
0.549 / 56.897
freq
1.835 GHz
V_upconv
5.843 / -122.288
IF Output Voltage
1.485E9
LOfrequency
RF frequency RF Input voltage
Figure 69 The P-1dB simulation. The P-1dB input power is 15.2 dBm and the
corresponding output power (input power + conversion gain) is 25.3 dBm.
75
6.2.3.4 Summary
The following two tables show the simulated results vs. the requirements, for an IF-power of -20 dBm and -5 dBm. Note that the IP3 simulation is dependent on this IF-power and should be well below the P-1dB compression point to give an accurate result, therefore the simulated values for IP3 with an IF-power of -5 dBm is probably incorrect.
Parameter Requirement Simulated@LO power -2.5 dBm
Simulated@LO power 0 dBm
Simulated@LO power 2.5 dBm
Conversion gain
≥10 dB 10.9 dB 11.0 dB 11.0 dB
Suppression ≤ -20 dB -45.6 dB -49.5 dB -29.8 dB
IIP3 ≥24 dBm 26.4 dBm 26.0 dBm 28.1 dBm
Compression point, P-1dB
N/A 15.5 dBm 15.2 dBm 15.2 dBm
Table 7, the important parameters and how they are affected by the LO power. A value of -20 dBm is used for the IF-power in this case.
Parameter Requirement Simulated@LO power -2.5 dBm
Simulated@LO power 0 dBm
Simulated@LO power 2.5 dBm
Conversion gain
≥ 10 dB 11.0 dB 11.1 dB 11.0 dB
Suppression ≤ -20 dB -58.6 dB -65.3 dB -45.1 dB
IIP3 ≥ 24 dBm 17.4 dBm 19.4 dBm 23.0 dBm
Compression point, P-1dB
N/A 15.5 dBm 15.2 dBm 15.2 dBm
Table 8, the important parameters and how they are affected by the LO power. A value of -5 dBm is used for the IF-power in this case.
76
7 Layout and chip area
The generation of the layout is simply made in the following steps:
1 Change every ideal component to the corresponding layout component
2 Fine tune the component values if needed
3 Use the ADS command Generate/Update layout
4 Place the components and connect them using microstrip in the ADS layout-tool, keeping in mind to use as small chip-area as possible
5 Re-updating the schematic with Generate/Update schematic and re-simulating the complete circuit with microstrip lines19
In step four bond pads and subvias are also added.
In the FET-mixer or pHEMT case the models and artwork needed in the layout was included in the pHEMT design kit, so that was pretty much straight forward. For the diode mixer or HBT case there were better libraries available then the one included in the design kit. Therefore the libraries used were tqthbt_dist2004_05_18 and tqt_lib_extras2004_10_14 which both contains in-house developed models and artwork.
Usually, the inductor value is allowed to deviate some from the wanted value. The reason for this is that the parameters that decide the value of an inductor are selected in discrete steps and because of this, the inductor will also take discrete values. For example the number of turns is selected as an integer. The value of the capacitors on the other hand is only affected by the area of the plates, and can therefore be selected more exactly. The design flow is therefore to first select an appropriate inductor and fine tune the capacitors value to get the required performance.
7.1 Diode mixer
7.1.1 Active LO-balun
In Figure 70 is the layout of the active LO-balun presented. With an area of 0.64 2mm this part is most area-consuming of all the components.
19 This step has not been performed for all designs due to the time consuming work an un-nesting of the auto generated schematic implies. Also, the adding of microstrip lines should not and does not affect the performance that much at these frequencies.
77
Figure 70 The active LO-balun.
7.1.2 LO-amplifier
Here, in Figure 71, is the amplifier to be used with the passive balun. The area of this is approximately 0.33 2mm .
78
Figure 71 The LO-amplifier.
7.1.3 Passive LO-balun
In Figure 72 is the passive LO-balun (or hybrid to be exact). The area this consumes is 0.49 2mm .
79
Figure 72 This is the passive LO-balun or hybrid.
7.1.4 LO-filter
The LO-filter used before the RF-amplifier consists of only an inductor and a capacitance so the layout of this will not be shown here. The area is approximately 0.06 2mm .
7.1.5 RF-amplifier
The RF-amplifier can be seen in Figure 73 and the area of this is approximately 0.41 2mm .
80
Figure 73 The RF-amplifier.
7.1.6 An estimation of the complete chip-area
To make a rough estimation of how much chip-area the final layout would occupy all the parts were placed in a new layout and space was left to allow microstrip connections between the parts. The area for the HBT diode mixer was estimated to 1.8 2mm , not including bond-pads This is the version with active LO-balun.
81
7.2 FET mixer
7.2.1 Layout of the mixer core
Figure 74, the size of one mixer core is about 0.24 2mm . The different input and output ports are labelled in the picture.
82
7.2.2 Layout of the active LO balun
In Figure 75 the layout of the active balun is shown. In the design of the active LO balun the balance is very important. Therefore, symmetry is used in the layout to maintain the balance as much as possible. The different input and output ports are labelled in the picture. In the middle the two transistors for the differential amplifier stage are seen, the two transistors at the edges are for the amplifier stages. The area used is about 0.16 2mm .
Figure 75 Layout of the active LO balun.
83
7.2.3 Layout of the output RF amplifier
Figure 76 The layout of the output RF amplifier clearly shows the use of three
transistors connected in parallel, the first stage is to the left and the second to the right. The different input and output ports are labelled in the picture. The area used is about 0.22 2mm .
7.2.4 Layout of the whole up-converter
The chip-area used to implement the whole resistive FET-mixer was estimated by placing the different parts side by side with enough space between them to allow interconnections. There was no layout done for the rat-race balun used in the resistive FET-mixer, instead the area used by this balun was estimated to be approximately the same as for the one used in the HBT case. Based on this, the chip-area was estimated to 1.9 2mm .
84
8 Conclusion
The main task in this thesis work was to construct an up-converter on GaAs, in either pHEMT or HBT, which could be a possible replacement of the bought up-converter used today. Also a filter that is located after this up-converter is very expensive and one reason of this work is to see if this filter can be removed or at least replaced by a cheaper one. Therefore one of the most critical parameters to fulfill was LO to RF suppression. Also the linearity turned out to be hard to fulfill. It was required that the up-converter managed to suppress the LO -20 dB (or more) relative the RF and the IIP3 should be at least 24 dBm (see the more comprehensive specification in the requirements chapter). If those requirements are fulfilled, and if the expense of the solution does not exceed the solution of today, it might be possible to replace this externally manufactured up-converter.
The conclusion based on these requirements is that it is possible to construct an up-converter that matches those requirements. This thesis has showed that it is for example possible to achieve an LO suppression (relative RF) of -49.5 dB with a pHEMT based resistive FET-mixer and -21.5 dB with an HBT based diode mixer. It is possible to achieve an IIP3 of 26 dBm for the pHEMT case and approximately20 25 dBm for the HBT case.
The circuits that have given those result occupy (if the IF-balun is placed off-chip) a chip-area of about 1.9 2mm for the pHEMT and about 1.8 2mm for the HBT circuit. The price per square millimetre was estimated to be twice as much for the pHEMT process, relative the HBT process.
Due to this it might be possible to replace both the up-converter used today and possibly also the expensive filter.
Criticism against some results is legitimized, especially since the models used are not optimized for the low frequency span (350-1835 MHz) this work is based on. Also, the models, the HBT diodes in particular, are reported not to perform well in two-tone simulations (such as IP3). But, since the ADS simulations are all the data available at this stage, they have to be trusted and hopefully the measurements, in the event of manufacturing, matches the simulations.
20 Based on the “10-dB rule of thumb” 13 10dBIIP P−≈ +
85
9 Acknowledgements
A special thanks to our supervisors Martin Johansson and Per Gustafson at Ericsson. We would also like to thank Joakim Een, Martin Emanuelsson and all other at Ericsson that has helped us during the work.
We would also like to thank our supervisor/examiner Adriana Serban at Linköping University.
86
10 References [1] http://users.ece.gatech.edu/~shensc/publications/procieeefeb04.pdf, 060210
[2] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design, Prentice-Hall Inc., 2000
[3] Stephen A. Maas, Microwave Mixers Second Edition, Artech House Inc., 1993
[4] Peter H. Ladbrooke, MMIC Design, GaAs FETs and HETMs, Artech House Inc., 1989
[5] Devendra K. Mistra, Radio-Frequency and Microwave Communication Circuits: Analysis and Design., John Wiley & Sons, Inc., 2001 ISBN 0-471-22435-9
[6] Stephen A. Maas, Nonlinear Microwave and RF circuits 2nd edition, Artech house Inc., 2003 ISBN 0-58053-484-8
[7] John Rogers and Calvin Plett, Radio Frequency Integrated Circuit Design, Artech house, Inc., 2003, ISBN 0-58053-502-x
[8] Rowan Gilmore and Les Besser, Practical RF Circuit Design for Modern Wireless Systems, Volume 2, Active Circuits and Systems., Artech house, Inc., 2003, ISBN 1-58053-522-4
[9] I.D.Robertson and S.Lucyszyn, RFIC and MMIC design and technology, IEE
[10] Behzad Razavi, RF microelectronics, Prentice Hall, 1998
[11] Jasprit Singh, Semiconductor devices, John Wiley & Sons, Inc., 2001
[12] Peter B. Kenington, High-Linearity RF Amplifier Design, Artech House, 2000
[13] Maas, S.A.; “A GaAs MESFET Mixer with Very Low Intermodulation” Microwave Theory and Techniques, IEEE Transactions on Volume 35, Issue 4, Apr 1987 Page(s):425 - 429
[14] Peng, S.; “A simplified method to predict the conversion loss of FET resistive mixers” Microwave Symposium Digest, 1997., IEEE MTT-S International Volume 2, 8-13 June 1997 Page(s):857 - 860 vol.2
[15] Thodesen, Y.; “A novel method for nulling the LO leakage in resistive FET mixers” Microwave Symposium Digest., 2000 IEEE MTT-S International Volume 3, 11-16 June 2000 Page(s):1597 - 1600 vol.3
[16] Lin, J.; Zelley, C.; Boric-Lubecke, O.; Gould, P.; Yan, R.; “A silicon MMIC active balun/buffer amplifier with high linearity and low residual phase noise” Microwave Symposium Digest., 2000 IEEE MTT-S International, Volume 3, 11-16 June 2000 Page(s):1289 - 1292 vol.3
[17] Rajashekharaiah, M.; Upadhyaya, P.; Deukhyoun Heo; Chen, E.; “A new 0.25um CMOS on-chip active balun with gain controllability for 5GHz DCR [direct conversion receiver]” SoutheastCon, 2005. Proceedings. IEEE, 8-10 April 2005 Page(s):71 – 74
[18] Kawashima, M.; Nakagawa, T.; Araki, K.; “A novel broadband active balun” Microwave Conference, 2003. 33rd European, Volume 2, 7-9 Oct. 2003 Page(s):495 - 498 vol.2
[19] Chen-Kuo Chu; Hou-Kuei Huang; Chih-Cheng Wang; Yeong-Her Wang; Chuan Chien Hsu; Wang Wu; Chang-Luen Wu; Chian-Sern Chang; “A 3.3 V
87
self-biased 2.4-2.5GHz high linearity PHEMT MMIC power amplifier” Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European, 16-18 Sept. 2003 Page(s):667 – 670
[20] Jeng-Han Tsai; Hong-Yeh Chang; Pei-Si Wu; Tian-Wei Huang; Huei Wang; ”A 44-GHz high-linearity MMIC medium power amplifier with a low-loss built-in linearizer” Microwave Symposium Digest, 2005 IEEE MTT-S International, 12-17 June 2005 Page(s):1575 – 1578
[21] Junghyun Kim; Moon-Suk Jeon; Jaehak Lee; Youngwoo Kwon; “A new "active" predistorter with high gain and programmable gain and phase characteristics using cascode-FET structures” Microwave Theory and Techniques, IEEE Transactions on, Volume 50, Issue 11, Nov. 2002 Page(s):2459 – 2466
[22] Yamauchi, K.; Mori, K.; Nakayama, M.; Mitsui, Y.; Takagi, T.; ”A microwave miniaturized linearizer using a parallel diode with a bias feed resistance” Microwave Theory and Techniques, IEEE Transactions on, Volume 45, Issue 12, Part 2, Dec. 1997 Page(s):2431 – 2435
[23] Yamauchi, K.; Mori, K.; Nakayama, M.; Itoh, Y.; Mitsui, Y.; Ishida, O.; ”A novel series diode linearizer for mobile radio power amplifiers” Microwave Symposium Digest, 1996., IEEE MTT-S International, Volume 2, 17-21 June 1996 Page(s):831 - 834 vol.2
[24] Gupta, N.; Tombak, A.; Mortazawi, A.; ”A predistortion linearizer using a tunable resonator” Microwave and Wireless Components Letters, IEEE [see also IEEE Microwave and Guided Wave Letters], Volume 14, Issue 9, Sept. 2004 Page(s):431 – 433
[25] Iommi, R.; Macchiarella, G.; Meazza, A.; Pagani, M.; ”Study of an active predistorter suitable for MMIC implementation” Microwave Theory and Techniques, IEEE Transactions on, Volume 53, Issue 3, Part 1, March 2005 Page(s):874 – 880
[26] Min-Gun Kim; Chung-Hwan Kim; Hyun-Kyu Yu; Jaejin Lee; ”An FET-level linearization method using a predistortion branch FET” Microwave and Guided Wave Letters, IEEE [see also IEEE Microwave and Wireless Components Letters], Volume 9, Issue 6, June 1999 Page(s):233 - 235
[27] Nakayama, M.; Mori, K.; Yamauchi, K.; Itoh, Y.; Takagi, T.; ”A novel amplitude and phase linearizing technique for microwave power amplifiers” Microwave Symposium Digest, 1995., IEEE MTT-S International, 16-20 May 1995 Page(s):1451 - 1454 vol.3
[28] Yamauchi, K.; Nakayama, M.; Ikeda, Y.; Nakaguro, H.; Kadowaki, N.; Araki, T.; “An 18 GHz-band MMIC linearizer using a parallel diode with a bias feed resistance and a parallel capacitor” Microwave Symposium Digest., 2000 IEEE MTT-S International, Volume 3, 11-16 June 2000 Page(s):1507 - 1510 vol.3
[29] Brinkhoff, J.; Parker, A.E.; Leung, M.; “Baseband impedance and linearization of FET circuits” Microwave Theory and Techniques, IEEE Transactions on, Volume 51, Issue 12, Dec. 2003 Page(s):2523 – 2530
[30] Iwai, T.; Ohara, S.; Yamada, H.; Yamaguchi, Y.; Imanishi, K.; Jeshin, K.; “High efficiency and high linearity InGaP/GaAs HBT power amplifiers: matching techniques of source and load impedance to improve phase distortion and linearity” Electron Devices, IEEE Transactions on, Volume 45, Issue 6, June 1998 Page(s):1196 – 1200
88
[31] Tilston, N.; McLachlan, A.D.; Sangster, A.J.; ”Operating limits for distortion reduction by the augmentation technique in nonlinear transistor amplifiers” Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems], Volume 151, Issue 5, 15 Oct. 2004 Page(s):385 – 394
[32] Webster, D.R.; Haigh, D.G.; Scott, J.B.; Parker, A.E.; “Derivative superposition-a linearisation technique for ultra broadband systems” Wideband Circuits, Modelling and Techniques, IEE Colloquium, 10 May 1996 Page(s):3/1 – 314
[33] Webster, D.R.; Ataei, G.R.; Parker, A.E.; Haigh, D.G.; “Developments in linear and nonlinear FET circuit design using derivative superposition” Analog Signal Processing (Ref. No. 1998/472), IEE Colloquium on, 28 Oct. 1998 Page(s):1/1 – 110
[34] Webster, D.R.; Haigh, D.G.; “Low-distortion MMIC power amplifier using a new form of derivative superposition” Microwave Theory and Techniques, IEEE Transactions on, Volume 49, Issue 2, Feb. 2001 Page(s):328 – 332
[35] Aparin, V.; Larson, L.E.; “Modified derivative superposition method for linearizing FET low-noise amplifiers” Microwave Theory and Techniques, IEEE Transactions on, Volume 53, Issue 2, Feb 2005 Page(s):571 – 581
[36] http://www.wjcommunications.com/pdf/technotes/Mixers_part1.pdf, 060211
[37] http://www.wjcommunications.com/pdf/technotes/Mixers_part_2.pdf, 060211
[38] B. Molin, Analog elektronik, Studentlitteratur, 2001
[39] David A. Johns and Ken Martin, Analog integrated circuit design, John Wiley & Sons Inc., 1997
[40] Kobayashi, K.W.; “A novel HBT active transformer balanced Schottky diode mixer” Microwave Symposium Digest, 1996., IEEE MTT-S International Volume 2, 17-21 June 1996 Page(s):947 - 950 vol.2
[41] Kuylenstierna, D.; Gunnarsson, S.E.; Zirath, H.; “Lumped-Element Quadrature Power Splitters Using Mixed Right/Left-Handed Transmission Lines” Microwave Theory and Techniques, IEEE Transactions on Volume 53, Issue 8, Aug. 2005 Page(s):2616 - 2621
[42] Kuylenstierna, D.; Linner, P.; “Design of broad-band lumped-element baluns with inherent impedance transformation” Microwave Theory and Techniques, IEEE Transactions on Volume 52, Issue 12, Dec. 2004 Page(s):2739 - 2745
[43] Parisi, S.J.; “180° lumped element hybrid” Microwave Symposium Digest, 1989., IEEE MTT-S International 13-15 June 1989 Page(s):1243 - 1246 vol.3
[44] http://mmic.snu.ac.kr/papers/shlee_2004_spring_rat_coupler.pdf, 060213
[45] Hwann-Kaeo Chiou; Yu-Ru Juang; Hao-Hsiung Lin; “Miniature MMIC star double-balanced mixer using lumped dual balun” Electronics Letters Volume 33, Issue 6, 13 March 1997 Page(s):503 – 505
[46] http://www.minicircuits.com/cgi-bin/spec?cat=tranfrmr&model=TC1-1T&pix=at224.gif&bv=4, 060211
[47] Noh, Y.S.; Park, C.S.; “An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications” Solid-State Circuits, IEEE Journal of Volume 39, Issue 6, June 2004 Page(s):967 – 970
[48] http://electriceng.com/papers.htm, 060213
89
[49] Youn Sub Noh; Chul Soon Park; “PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit” Solid-State Circuits, IEEE Journal of Volume 37, Issue 9, Sep 2002 Page(s):1096 – 1099
[50] Yong-Joon Jeon; Hyung-Wook Kim; Min-Seok Kim; Young-Sik Ahn; Jong-Won Kim; Ji-Youn Choi; Doo-Chan Jung; Jin-Ho Shin; “Improved HBT linearity with a "post-distortion"-type collector linearizer” Microwave and Wireless Components Letters, IEEE [see also IEEE Microwave and Guided Wave Letters] Volume 13, Issue 3, March 2003 Page(s):102 – 104
[51] Sivonen, P.; Vilander, A.; Parssinen, A.; “Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors” Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on] Volume 52, Issue 2, Feb. 2005 Page(s):305 – 317
[52] Yoshimasu, T.; Tanba, N.; Hara, S.; “An HBT MMIC linear power amplifier for 1.9 GHz personal communications” Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1994. Digest of Papers., IEEE 1994 22-25 May 1994 Page(s):59 – 62
[53] Jia Sun; Yan Wah Michael Chia; Bin Li; “A new BJT linearizer design for RF power amplifier” Microwave Conference, 2000 Asia-Pacific 3-6 Dec. 2000 Page(s):1117 – 1121
[54] Bruck, Yu.M.; “Fifth-order linearization of p-n junction and BJT by linear resistance only” Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean Volume 1, 18-20 May 1998 Page(s):489 - 493 vol.1
[55] Yoshimasu, T.; Akagi, M.; Tanba, N.; Hara, S.; “An HBT MMIC power amplifier with an integrated diode linearizer for low-voltage portable phone applications” Solid-State Circuits, IEEE Journal of Volume 33, Issue 9, Sept. 1998 Page(s):1290 – 1296
[56] Kim, J.H.; Noh, Y.S.; Park, C.S.; “MMIC power amplifier adaptively linearized with RF coupled active bias circuit for W-CDMA mobile terminals applications” Microwave Symposium Digest, 2003 IEEE MTT-S International Volume 3, 8-13 June 2003 Page(s):2209 - 2212 vol.3
[57] TriQuint Semiconductor, TQTHBT2 Design Manual v. 2.2, TriQuint Semiconductor, 2004
90
Appendix A
Additional design: adaptive bias circuit
During the design of the HBT power amplifier different methods of increasing the linearity was tested, one of them was a slightly modified version of the adaptive bias circuit (ABC) found in [47]. Indeed, this circuit increases the 1-dB compression point (as shown below) but this method suffers from one major drawback: it completely ruins the IP3 performance of the amplifier! And since IP3 was one of the most important figures of merit in the requirements that this work is based on, the ABC is not included in the design. But, since the design itself inherited some interesting features and due to the fact that it can heavily increase the 1-dB compression point the design and its results are discussed below.
ABC
Vb
Vbbias
Vut
PortInNum=1
tqhbt2_hbtsQ3
m=2l=40 umw=3 umn=3
RR1R=Rstab Ohm
CC1C=30 pF
RRbR=Rb Ohm
V_DCSRC1Vdc=5 V
RR5R=15 Ohm
CC3C=Cb pF
tqhbt2_hbtsQ2
m=2l=50 umw=3 umn=3
RR4R=20 Ohm
CC2C=Cbypass pF
RR3R=20 Ohm
tqhbt2_hbtsQ1
m=M_biasl=L_bias umw=3 umn=3
LL1
R=L=5.0 nH
V_DCSRC5Vdc=1.3 V
RR2R=60 Ohm
VARVAR4
M_amp=5W_amp=3 {t}L_amp=30Rstab2=100Rstab=16
EqnVar
PortOutNum=2
CCF1C=11.25 pF {t}
CC5C=30 pF
CCF2C=11.25 pF {t}
LLF
R=L=1.3 nH {t}
V_DCSRC2Vdc=14 V
RR6R=10 Ohm
CC4C=75 pF
tqhbt2_hbtsQ4
m=M_ampl=L_amp umw=2 umn=3
LL2
R=1e-12L=5.0 nH
VARVAR3
M_bias=1W_bias=3 {t}Rb=100R1=50Cbypass=75Cb=75L_bias=18
EqnVar
Figure 77 A version of the PA with the ABC inside of the blue rectangle.
A version of the power amplifier (not the final one) is shown in Figure 77. This circuit uses the ABC and it is the part inside the rectangle. The function of the ABC can be described as follows. The transistor Q1 together with Rb senses the incoming input power and when this power increases the collector current of Q1 will increase. This increasing collector current will result in a decreasing base current into Q2 which on its turn will increase the base current into Q3, resulting in an increasing quiescent current into the amplifying transistor; which is wanted. The emitter area of Q1 and the value of Rb are used to tune the sensitivity of the bias circuit.
The capacitor C2 is used to by-pass the amplified and unwanted input signal; and the capacitor C3 is used to increase linearity [47].
91
-10 0 10 20-20 30
5
10
0
15
Input Power, dBmP
ower
Gai
n, d
B
1-dB compression point without ABC (dBm)
inpwr[0]
7.946
1-dB compression point with ABC (dBm)
PA4_abc..inpwr[0]
20.227
Figure 78 The power gain of the power amplifier. The gain of the circuit using the
ABC is the red trace and the blue trace is the same circuit but with the ABC replaced by a current source. To the right is the 1-dB compression point for each circuit.
The results of this ABC is shown in Figure 78, notice that the ABC kicks in around -3 dBm of input power and moves the 1-dB compression point as much as 12 dB.
Layout
Since the drawbacks of this linearization method were discovered relatively late in the work also a layout was made, this can be seen in Figure 79.
92
Figure 79 The layout of the amplifier using ABC .
93
Appendix B
Workbenches
VLOinVRFin
The mixer
Vload
Vload VloadVload
Vload
SIMULATION CONTROL
Set the following parameters:1) LO frequency, LOfreq2) RF frequency, RFfreq3) RF power, P_RF4) LO power, P_LO5) Load impedance, Zload Set the harmonic amplitudes
relative to the LO power
ParamSweepSweep1
Step=0.5Stop=15Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB2"SweepVar="P_LO"
PARAMETER SWEEP
VARR2
Zload=50+j*0P_LO=7 _dBmP_RF=-20 _dBmRFfreq=350 MHzLOfreq=1485 MHz
EqnVar
31 2
AndreaDiodeRingVersionA_reportpictureX23
RF_outIF_in
LO_in
tqhbt2_incNET
Statistical_Info=OnStatistical_Analysis=Offk_IS=0.0k_RNI=1.0k_BF=75
TQHBT2Netlist Include
HarmonicBalanceHB2
UseKrylov=autoSS_Freq=1 kHzSS_MixerMode=yesOrder[2]=3Order[1]=7Freq[2]=RFfreqFreq[1]=LOfreqMaxOrder=8
HARMONIC BALANCE
OptionsOptions1
MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-8 AI_RelTol=1e-3V_AbsTol=1e-4 VV_RelTol=1e-3Tnom=25Temp=25
OPTIONS
12I_Probe
I_LOin
1
2
P_1TonePORT1
Freq=RFfreqP=dbmtow(P_RF)Z=50Num=1
1
2
P_nHarmPORT3
P[3]=polar(dbmtow(P_LO-100),0)P[2]=polar(dbmtow(P_LO-100),0)P[1]=polar(dbmtow(P_LO),0)Freq=LOfreqZ=50 OhmNum=3 1
1
2
TermTerm4
Z=ZloadNum=4
1 11
2
I_1ToneSRC4
I_USB=1 mAFreq=RFfreq+LOfreqI=
1
2
I_1ToneSRC3
I_LSB=1 mAI_USB=1 mAFreq=IFfreqI=
1 2
I_ProbeI_load
1 2
I_ProbeI_RFin
1
1
Figure 80 The simulation setup for LO-input power. This is based on the ADS design
guide for conversion gain, isolation and port impedance found under ‘DesignGuide>Mixers’ and ‘Single-Ended Mixers Characterization’.
Vin
The mixer
VLOin
Vload
SIMULATION CONTROL
N dB Compression Simulation
Set the harmonic amplitudesrelative to the LO power
The XDB controller is an easy w ay to f ind theP1dB. It produces tw o results: inpw r and outpw r.inpw r is the input pow er required for N dB of gaincompression. outpw r is the corresponding outputpow er. Thus, the conversion gain at the N dB compression point is also available.
Set the following parameters:1) LO frequency, LOfreq2) RF frequency, RFfreq3) Equation for the IF frequency4) LO power, P_LO5) Load impedance, as complex number6) Gain compression, N, in dB
CP_sim
tqhbt2_incNET
Statistical_Info=OnStatistical_Analysis=Offk_IS=0.0k_RNI=1.0k_BF=75
TQHBT2Netlist Include
31 2
AndreaDiodeRingVersionA_reportpictureX21
RF_outIF_ in
LO_in
OptionsOptions1
MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-8 AI_RelTol=1e-3V_AbsTol=1e-4 VV_RelTol=1e-3Tnom=25Temp=25
OPTIONS
XDBHB2
GC_OutputFreq=IFfreqGC_InputFreq=RFfreqGC_OutputPort=2GC_InputPort=1GC_XdB=NFundOversample=2Order[2]=3Order[1]=11Freq[2]=RFfreqFreq[1]=LOfreqMaxOrder=9
GAIN COMPRESSION
ParamSweepSweep1
Step=1Stop=15Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB2"SweepVar="P_LO"
PARAMETER SWEEP
VARVAR1
N=1Zload=50 +j*0P_LO=7 _dBmIFfreq=mag(RFfreq-LOfreq)RFfreq=350 MHzLOfreq=1485 MHz
EqnVar
1
2
P_1TonePORT1
Freq=RFfreqP=dbmtow(-20)Z=50 OhmNum=1
1
2
TermTerm2
Z=ZloadNum=2
11
1
2
P_nHarmPORT3
P[3]=polar(dbmtow(P_LO-100),0)P[2]=polar(dbmtow(P_LO-100),0)P[1]=polar(dbmtow(P_LO),0)Freq=LOfreqZ=50 OhmNum=3 1
Figure 81 This is the simulation setup used to see how LO-input power affects the 1-
dB compression point. It is basically based on the ADS design guide ‘N-dB gain compression point’ found under ‘DesignGuide>Mixers’ and ‘Single-Ended Mixers Characterization’.
94
Mirror
Vin
Vut_mid1
Vut_mid2
ParamSweepSweep1
Step=0.1Stop=2Start=0.3SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB3"SweepVar="Freq"
PARAMETER SWEEP
HarmonicBalanceHB1
Order[1]=7Freq[1]=1.485 GHz
HARMONIC BALANCE
LSSPHB3
LSSP_FreqAtPort[3]=Freq GHzLSSP_FreqAtPort[2]=Freq GHzLSSP_FreqAtPort[1]=Freq GHzOrder[1]=7Freq[1]=Freq GHz
LSSP
S_ParamSP1
Step=0.01 GHzStop=2 GHzStart=0.1 GHz
S-PARAMETERS
DCDC1
DC
OptionsOptions1
MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-12 AI_RelTol=1e-6V_AbsTol=1e-6 VV_RelTol=1e-6Tnom=25Temp=25
OPTIONS
tqhbt2_incNET
Statistical_Info=OnStatistical_Analysis=Offk_IS=0.0k_RNI=1.0k_BF=75
TQHBT2Netlist Include
VARVAR4
mcc=1.0mcr=1.0mch=1.0
EqnVar
VARVAR2
P_LO=0Freq=1.485
EqnVar
VARVAR1
Cr=14Rstab=300
EqnVar
12
I_ProbeI2
1
2
4 3
Tqhbt_3x3x45Tqhbt_2
temp=25area=135
e2 e1
c
b
1
2
V_DCSRC3Vdc=7.0 V
1 2
V_DCSRC2Vdc=5 V
12
V_DCSRC1Vdc=5 V
21
RR4R=60 Ohm
1
2
4 3
Tqhbt_3x3x45Tqhbt_6
temp=25area=135
e2 e1
c
b
1
2
4 3
Tqhbt_3x3x45Tqhbt_5
temp=25area=135
e2 e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_8
temp=25area=135
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_7
temp=25area=135
e2e1
c
b
2
1RR32R=55 Ohm
2
1
RR31R=67.7 Ohm
2
1RR22R=55 Ohm
2
1
RR21R=67.7 Ohm
2
1RR12R=Rstab Ohm
2
1RR11R=Rstab Ohm
1
2
43
Tqhbt_3x3x45Tqhbt_4
temp=25area=135
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3
temp=25area=135
e2e1
c
b
1
2
4 3
Tqhbt_3x3x45Tqhbt_1
temp=25area=135
e2 e1
c
b
2
1RRL2R=(1.0*22) Ohm
2
1CC22C=20 pF
2
1CC21C=20 pF
1
2 1
CC1C=10 pF
21
CC12C=Cr pF
2 1
CC31C=10 pF
2 1
CC32C=10 pF
2
1RRL1R=(1*22) Ohm
1
1 2I_ProbeI1
1
1
1
2
TermTerm2
Z=50 OhmNum=2
11
1
12I_ProbeI_out_50ohm2
1
1
2
TermTerm3
Z=50 OhmNum=3
1 1
1 2I_ProbeI_out_50ohm1
1
2
P_1TonePORT1
Freq=Freq GHzP=polar(dbmtow(P_LO),0)Z=50 OhmNum=1
Figure 82 The simulation setup used for the active LO-balun.
Vload
Set these values:
Set Load and Source impedances at baseband,fundamental and harmonic frequencies
HarmonicBalanceHB1
UseKrylov=yesOrder[2]=15Order[1]=15Freq[2]=RFfreq+fspacing/2Freq[1]=RFfreq-fspacing/2MaxOrder=Max_IMD_order
HARMONIC BALANCE
1
2
P_nTonePORT1
P[2]=dbmtow(RFpower-3)P[1]=dbmtow(RFpower-3)Freq[2]=RFfreq+fspacing/2Freq[1]=RFfreq-fspacing/2Z=Z_sNum=1
1
2
P_1TonePORT4
Freq=FreqP=polar(dbmtow(-20),0)Z=50 OhmNum=1
VARVAR2Z0=50;Load Impedaneces=Z_l_bb=Z0+j*0Z_l_fund = Z0 + j*0Z_l_2 = Z0 + j*0Z_l_3 = Z0 + j*0Z_l_4 = Z0 + j*0Z_l_5 = Z0 + j*0;Source Impedances=Z_s_bb=Z0+j*0Z_s_fund = Z0 + j*0Z_s_2 = Z0 + j*0Z_s_3 = Z0 + j*0Z_s_4 = Z0 + j*0Z_s_5 = Z0 + j*0
EqnVar
VARglobal VAR6
f_4 = 4.5*RFfreqf_3 = 3.5*RFfreqf_2 = 2.5*RFfreqf_1 = 1.5*RFfreqf_bb=0.5*RFfreq
EqnVar
VARVAR1
Max_IMD_order=20RFpower=-20 _dBmfspacing=10 kHzRFfreq=1835 MHz
EqnVar
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x1
temp=25area=A
e2e1
c
b
1 2
Tqhbt_res_nicrTqhbt_res_nicr15
W1=30 umL1=6 um
C1 2 1
2
43
Tqhbt_3x3x45Tqhbt_3x3x5
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x4
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x3
temp=25area=A
e2e1
c
b
1
2
Tqhbt_res_nicrTqhbt_res_nicr16
W1=20 umL1=20 umC
12
1
2
Tqhbt_res_nicrTqhbt_res_nicr14
W1=30 umL1=10.79 umC
12
11
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw14
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
TermTerm1
Z=Z_loadNum=2
1 2
I_ProbeIload
1 2
Tqhbt_mim_capTqhbt_mim_cap8
W1=110.37 umL1=100 um
1 2
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw11
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
V_DCSRC1Vdc=Bias V
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw15
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
V_DCSRC3Vdc=5 V
1
1 2
Tqhbt_mim_capTqhbt_mim_cap9
W1=110.37 umL1=100 um
1 2
1
Figure 83 Simulation setup used to simulate IIP3. Notice the 2-tone input port. This is
the circuit with “layout components”.
95
Vload
XDBHB2
GC_MaxInputPower=100GC_OutputPowerTol=1e-3GC_InputPowerTol=1e-3GC_OutputFreq=1.835 GHzGC_InputFreq=1.835 GHzGC_OutputPort=2GC_InputPort=1GC_XdB=1Order[1]=7Freq[1]=1.835 GHz
GAIN COMPRESSION
VARVAR8Freq=1.835E9
EqnVar
ParamSweepSweep6
Step=0.1E9Stop=4E9Start=0.3E9SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB3"SweepVar="Freq"
PARAMETER SWEEP
LSSPHB3
LSSP_FreqAtPort[2]=FreqLSSP_FreqAtPort[1]=FreqOrder[1]=8Freq[1]=Freq
LSSP
1
2
P_1TonePORT4
Freq=FreqP=polar(dbmtow(-20),0)Z=50 OhmNum=1
1
2
P_nTonePORT1
P[2]=dbmtow(RFpower-3)P[1]=dbmtow(RFpower-3)Freq[2]=RFfreq+fspacing/2Freq[1]=RFfreq-fspacing/2Z=Z_sNum=1
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x1
temp=25area=A
e2e1
c
b
1 2
Tqhbt_res_nicrTqhbt_res_nicr15
W1=30 umL1=6 um
C1 2 1
2
43
Tqhbt_3x3x45Tqhbt_3x3x5
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x4
temp=25area=A
e2e1
c
b
1
2
43
Tqhbt_3x3x45Tqhbt_3x3x3
temp=25area=A
e2e1
c
b
1
2
Tqhbt_res_nicrTqhbt_res_nicr16
W1=20 umL1=20 umC
12
1
2
Tqhbt_res_nicrTqhbt_res_nicr14
W1=30 umL1=10.79 um
C1
2
11
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw14
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
TermTerm1
Z=Z_loadNum=2
1 2
I_ProbeIload
1 2
Tqhbt_mim_capTqhbt_mim_cap8
W1=110.37 umL1=100 um
1 2
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw11
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
V_DCSRC1Vdc=Bias V
1
2Tqhbt_spiral_rect_ccwTqhbt_spiral_rect_ccw15
LV=209 umLH=209 umS1=7 umN1=7W1=7 um
12
1
1
2
V_DCSRC3Vdc=5 V
1
1 2
Tqhbt_mim_capTqhbt_mim_cap9
W1=110.37 umL1=100 um
1 2
1
Figure 84 The simulation setup used for forward transmission gain and 1-dB
compression point. Same as the IIP3 simulation, the circuit with “layout components” has been used.
DiffOut1
Vd
Vout1
Vout2
DiffOut2
Vsrc
VinVgate1
Vdrain1 Vdrain2
Vgate2
DiffOut1 DiffOut2
RR18R=150 Ohm
+ TermTerm2
Z=50 OhmNum=2
CC9C=2 pF
tom3_holderTMH1
V_DCSRC8Vdc=5 V
RR16R=100 Ohm
I_ProbeIdrain4
+ TermTerm3
Z=50 OhmNum=3
CC17C=2 pF
tom3_holderTMH2
V_DCSRC9Vdc=5 V
RR19R=150 Ohm
RR20R=100 Ohm
I_ProbeIdrain5
tom3_holderTMH4
I_ProbeIdrain1
I_ProbeIdrain2
tom3_holderTMH3
RR8R=1
RR2R=Rdrain1 Ohm
CC2C=1.0 pF
CC3C=2.0 pF
V_DCSRC1Vdc=5.0 V
CC1C=1.0 pF
RR1R=Rdrain1 Ohm
PLCPLC1
C=10.725 pFL=1.071 nH
RR3R=6.6 Ohm
I_ProbeIsrc
VARstd_vars2
input_freq=1485 MHzRstab1=3000Rdrain1=150
EqnVar
P_1TonePORT1
Freq=input_freqP=polar(dbmtow(0),0)Z=50 OhmNum=1
RR7R=Rstab1
DCDC1
DC
HarmonicBalanceHB1
Order[1]=7Freq[1]=input_freq
HARMONIC BALANCE
LSSPHB3
LSSP_FreqAtPort[3]=input_freqLSSP_FreqAtPort[2]=input_freqLSSP_FreqAtPort[1]=input_freqOrder[1]=5Freq[1]=input_freq
LSSP
S_ParamSP1
Step=0.01 GHzStop=4 GHzStart=0.1 GHz
S-PARAMETERS
XDBHB2
GC_MaxInputPower=200GC_OutputPowerTol=1e-3GC_InputPowerTol=1e-3GC_OutputFreq=input_freqGC_InputFreq=input_freqGC_OutputPort=2GC_InputPort=1GC_XdB=1Order[1]=3Freq[1]=input_freq
GAIN COMPRESSION
OptionsOptions1
MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-8 AI_RelTol=1e-3V_AbsTol=1e-4 VV_RelTol=1e-3Tnom=25Temp=25
OPTIONS
SweepPlanSwpPlan1
Reverse=noSweepPlan=UseSweepPlan=Start=0.1 GHz Stop=2 GHz Step=0.01 GHz Lin=Pt=1.485 GHz
SWEEP PLAN
ParamSweepSweep3
Step=0.01 GHzStop=2 GHzStart=0.1 GHzSimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB3"SweepVar="input_freq"
PARAMETER SWEEP
Figure 85 Simulation setup used for the active LO balun.
96
Dataset Output_Amplifier_LSSPDataset Output_Amplifier_SP Dataset Output_Amplifier_XDB Dataset Output_Amplifier_HB
When IP3 is simulated the SP1 simulation controller should also be activated!
PARAMETER SWEEP
LSSPHB3
LSSP_FreqAtPort[2]=input_freqLSSP_FreqAtPort[1]=input_freqOrder[1]=5Freq[1]=input_freq
LSSPS-PARAMETERS
PARAMETER SWEEPPARAMETER SWEEP
SWEEP PLAN
ParamSweepSweep4
Step=1Stop=10Start=1SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]="XDB"SimInstanceName[3]="SP1"SimInstanceName[2]="HB1"SimInstanceName[1]="HB3"SweepVar="input_freq"
PARAMETER SWEEP
OptionsOptions1
MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-8 AI_RelTol=1e-3V_AbsTol=1e-4 VV_RelTol=1e-3Tnom=25Temp=25
OPTIONS
GAIN COMPRESSION HARMONIC BALANCE
IP3inIP3in1IP3in1=ip3_in(Vout,dB(S21),{1,0},{2,-1},50)
P0
Pin
IP3in
2 1
3
2 1
3
21
2
1
21
1
1
2
11
2 1
32
1
21
11
2 1
3
2 1
3
2 1
3
2
1
1
2
21
1
2
1
1 11 1
21
1
2
2 1
2 1
EqnVar
1
2
1
2
1
2
Figure 86 Simulation setup for the output amplifier. Mainly used for small and large-
signal S-parameters, IIP3 and compression point simulation.
97
Appendix C
Maple calculation 1
98
Maple calculation 2
99
Maple calculation 3
100
101
Maple calculation 4
102
Maple calculation 5
Here one of the calculations that was made to decide the best configuration of the phase relationship between the LO-LO and IF-IF is shown. The idea is to express the output from each mixer with a power series, each output is dependent on the phase of the corresponding LO- and IF-signal, and finally the output is the sum of these two signals. In the calculation the power series is expanded to order three.
103
