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1. Different Architectures

Nyquist-Rate A/D Converters

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2. Integrating A/D Converters

In this type of A/D converters, the analogue input

signal is first converted into a time interval which

is then converted into a digital number using an

accurate clock and a counter. They are used in

measurement instruments such as voltage or

current meters.

2.1 Single-Slope A/D Converter

Initially the counter is reset and the capacitor is

discharged. At this point, Vo > Vin and so the the

comparator output goes HIGH. This enables the

clock to the counter and starts the ramp

generator. Once Vo = Vin, the ramp is reset and

the binary count is stored in the latches.

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Thus, n is the quantised value and digital

representation of Vin. The accuracy of the

converter is a function of the reference voltage Vref,

the clock period TC and the time-constant RC

(which tends to drift with time and temperature).

where, t1 is the time needed for the integrator to

reach Vin, RC is the time-constant of integrator, Tcis the clock period, n is the number of clock

counts, and N the resolution of the converter.

ref

in

V

VRCt =

1 CnTt 1ref

inN

V

Vn 2

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Employs both a variable-slope and a fixed-sloperamp. At the end of phase 1, Vo is given by:

2.2 Dual-Slope A/D Converter

ref

inC

No

V

VTV 2=

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Combining the above two equations, we have:

In phase 2 the integrator discharges from Vo to

zero in a time interval t2 given by:

ref

oC

V

RCVnTt

==

2

ref

inN

VVn 2=

The dual-slope A/D converter has several

advantages over the single-slope converter. The

accuracy is independent of the clock frequency

and the integrator time-constant RCbecause they

effect the up- and down-ramp voltages in the

same way.

The linearity is excellent because the digital

counter generates all codes, and all codes are

inherently present.Suitable for high-accuracy applications with low

conversion rates, e.g., precision digital voltmeter.

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3. Successive Approximation ADC

It is a feedback scheme that uses a trial-and-error

technique to approximate each analogue sample

with a corresponding digital word.

The N inputs of the D/A converter are enabled

(set to 1) one at a time starting with the MSB (b1).

If the error signal is positive (i.e., VDAC < Vin) thecomparator output goes LOW causing the bit in

the successive-approximation register (SAR) to

reset to 0. If is negative, the 1 bit is retained in

the SAR. The process is repeated with the next

MSB, etc.

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Example of 4-bit Conversion

Assume that Vin is constant at 5.1V and the D/A

converter output voltages (VDAC

) are 8V for the

MSB, 4V for the 22 bit, 2V for the 21 bit and 1V for

the LSB.

MSB trial

22-bit trial

21-bit trial LSB trial

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4. Counting and Tracking ADCs

These are the two main classes of digital-ramp

converters. The counting type is shown below:

Initially the outputs of the counter and the D/A

converter are set to LOW.

When Vin is applied and Vin > Vo, the comparator

output goes HIGH and the counter starts counting

the input pulses. The output of the digital counter

is applied to the D/A converter which creates a

staircase analogue output. The countingcontinues until Vo > Vin. At this point, the output of

the digital counter is the required output word and

its dumped into a storage register.

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A 4-bit counting example is shown below:

Although quite simple in concept, this converter

has the disadvantage of being very low speed for

a given resolution. Also, the conversion time is a

function of the analogue input signal level.

An alternative type is the trackingA/D converter,

which is realised by replacing the unipolar digital

counter with an up-down counter. In this case, if

Vin > Vo, the counter counts up, and if V in < Vo, the

counter counts down. The counter is never

cleared. The tracking action of a 4-bit converter isshown below:

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5. Flash A/D Converters

They are the fastest and conceptually the

simplest A/D converters. In an N-bit converter,

2N-1 analogue latching comparators and voltage

references are used to convert the analogue

voltage to a digital word. The structure of a 3-bit

flash A/D converter is shown below:

The 7 comparators generate a thermometer code

which is then processed by the encoder/decoder

logic to produce a 3-bit digital word.

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When everything is working ideally, the pattern ofthe comparator outputs should resemble that of a

thermometer, all 0s above the input level, all 1s

below. However, under extremely high input

slew-rate conditions or timing differences

between various signal paths, a 1 may be found

above a 0 in the thermometer code even though

this cannot happen at dc. Errors of this type are

referred to as bubbles.

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A common method to compress bubbles to to use

a 3-input AND gate that compares the logic of

each comparator with those immediately above

and below. This would then require two 1s and a

0 to cause the encoder output to be true.

However, This technique will not remove bubble

errors where two or more string of 0s are

surrounded by 1s.

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In bipolar technology, flash A/D converters

operate in a continuous-time mode because

sample-and-hold (S/H) circuits cannot be used.

CMOS flash A/D converters, on the other hand

can operate in either continuous or discrete-time

mode. In the latter mode, a S/H circuit can be

combined with the comparator input stage. The

details of a small CMOS clocked comparator are

shown below:

When is HIGH, the inverter is set to its bistable

operating point and the other side of the capacitor C

is charged to Vri. When goes LOW, the inverter is

free to fall either HIGH or LOW depending on itsinput voltage. At the same time the other side of C is

pulled to Vin. Since the inverter side of C is floating,

C must keep its original charge, and therefore the

inverters input will change by (Vri Vin). Since the

inverters input was at its bistable point, the sign of

(Vri Vin) will determine which direction the inverters

output will fall.14

6. Two-step A/D Converters

The circuit complexity of the flash A/D converters

increases very rapidly with increasing N. For large

values of N (N > 8), the two-step flash architecture

is a good alternative. It uses coarse and fine

quantisation to increase the resolution.

The circuit operates on Vin in two serial steps. First

an N-bit coarse flash ADC determines N MSBs

which are then converted to an analogue value(VDAC) using an N-bit DAC. VDAC is subtracted from

Vin and the difference is applied to an M-bit fine

flash ADC that generates the M LSBs. In most

cases N and M are equal.

For an 8-bit ADC, the two-step flash approach

reduces the comparator count from 255 to 30.

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7. Time-Interleaved ADCs

Very high-speed A/D conversions can be

realised by operating many ADCs in parallel. The

system architecture for a four-channel ADC is

shown below:

0 is the clock at four times the rate of1 to 4.

Also, 1 to 4 are delayed with respect to eachother by the period of0, such that each converter

will get successive samples of Vin. With this

approach, the input S/H is very critical and is

sometimes realised in GaAs while the other S/Hs

can be realised in silicon.