AN_SPMC75_0019_en_V1.3

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Creating Sine-Wave Modulated

PWM Signal

V1.2 - May 29, 2006

English Version

19, Innovation First Road Science Park Hsin-Chu Taiwan 300 R.O.C.

Tel: 886-3-578-6005 Fax: 886-3-578-4418 E-mail: [email protected]

http://www.sunplusmcu.com http://mcu.sunplus.com

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Creating Sine-Wave Modulated PWM Signal

Sunplus Technology Co., Ltd. PAGE 1 V1.2 May 29, 2006

Important Notice

SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information

provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS

TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS

TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No

responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third

parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical

components in life support systems or aviation systems, where a malfunction or failure of the product may

reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.

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Revision History

Revision Date By RemarkPage

Number(s)

V1.3 2006/12/22 Li Jing Proofreading

V1.2 2006/05/29 Li JingTranslate Creating Sine-Wave Modulated PWM

Signal V1.2, Chinese version

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Table of Content

PAGE

1 System Design Summary .................................................................................................................. 1

1.1 System Design .............................................................................................................................. 1

1.2 Sine-Wave Generating Principle ................................................................................................... 1

2 Design Tips ......................................................................................................................................... 4

2.1 Demo ............................................................................................................................................. 4

3 Flow Charts......................................................................................................................................... 7

3.1 Main Process Description.............................................................................................................. 7

3.2 ISR Description.............................................................................................................................. 7

4 MCU Resource.................................................................................................................................... 9

5 Test..................................................................................................................................................... 10

5.1 Test Circuit................................................................................................................................... 10

5.2 Test Waveform............................................................................................................................. 10

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1 System Design Summary

1.1 System Design

MCP timer on the SPMC75F2413A chip is dedicated to driving a motor which can generate

various PWM signals according to user settings. This application selects TMR3 to generate

six programmable center-aligned SPWM waveform output signals with 120 degrees out of

phase. The hardware structure is shown in Figure 1-1.

Figure 1-1 Hardware Structure

Where, PWMUN = ! PWMU, PWMVN = ! PWMV, PWMWN = ! PWMW. Affected by

dead-time timer, these relations are not absolutely true.

1.2 Sine-Wave Generating Principle

Figure 1-2 uses sawtooth wave to generate the three-phase SPWM waveform. When the

input voltage is higher than sawtooth voltage, PWM outputs high; otherwise, PWM outputs

low. If the frequency of sawtooth wave is higher than that of input voltage, PWM duty will

vary linearly with the input voltage and the period of PWM wave is the same as that of

sawtooth wave.

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Figure 1-2 Three-Phase SPWM Generating Principle

The PWM wave can be described by a Fourier decomposition as a Fourier series, thus the

amplitude of the lowest frequency can be obtained as:

])12cos(1

1[1

1 =

=N

i

mm

Ni

NUU

(1-1)

Where, N is the number of pulses within half waveform and is the amplitude of input

voltage.

mU

When N>1, , thus the fundamental wave of output voltage is just the sine wave

needed. In this way we can inhibit the low order harmonic wave effectively.

mmUU =1

Practically, PWM waveform is not generated by comparing the values between sine-wave

and sawtooth wave. To reduce the CPU burden, the values of PWM duty register are

fetched from lookup table stored inside the program memory of CPU according to

sinusoidal wave.

The main controller generates SPWM by DDS algorithm. As shown in Figure 1-3, it is a

typical DDS system except for substituting PWM (with a carrier frequency of 10KHz) forDAC. The phase data is obtained by getting the high 10 bits in the 16-bit accumulator.

So we define a 2n

(1024) size of data table to speed up this procedure and save the

processing cycle in CPU. Accordingly, the error can be calculated as below:

The most error of phase is = 360/ 1024 = 0.3516 in theory. Even if we count

the software bouncing on, the phase error will not exceed 0.5 at most.

Since 1024 is not an integral multiple of 3, the phase-different constants of 120

and 240 have to be presented approximately with an error of 0.5. So the

phase-different constant is not the exact 120 or 240, but the error for Ti must be

within 180/2n.

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Additionally, the more depiction points are selected, the more precise the generated

waveform is, especially under the low frequency mode.

Figure 1-3 Three-Phase SPWM Generating Diagram

Note: The formulas listed above are only suitable for the case that phase error is lower

than that of amplitude. In fact, when amplitude error increases, the phase error will

increase accordingly. You can define all kinds of waveform in the 1024-point data table,

such as a third harmonic enhanced waveform.

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2 Design Tips

2.1 Demo

#include "Spmc75_regs.h"

#include "unspmacro.h"

void SPMC75_SPWM_Init(void);

void SPMC75_SPWM_ISR(void);

void SPMC75_SPWM(unsigned int F,unsigned int AM);

main()

{

Disable_FIQ_IRQ();

SPMC75_SPWM_Init();

INT_IRQ();

SPMC75_SPWM(0x3200,0); // Set output frequency as 50Hz

while(1);

}

//=====================================================================

// Description: IRQ3 interrupt source is XXX,used to XXX

// Notes:

//=====================================================================

void IRQ3(void) __attribute__ ((ISR));

void IRQ3(void)

{

if(P_TMR3_Status->B.TPRIF)

{P_TMR3_Status->B.TPRIF = 1; // Clear TPRIF flag

SPMC75_SPWM_ISR();

}

}

#include "Spmc75_regs.h"

const unsigned int Sin_TAB_dot = 1024;// Size of sine-wave lookup table

const unsigned int Phases_120 = 341;

// Offset at 120 degrees in sine-wave table

const unsigned int Phases_240 = 682;

// Offset at 240 degrees in sine-wave table

extern int iSin_TAB[];// Using DDFS algorithm to generate SPWM waveform

static unsigned int g_uiAM_Data; // SPWM amplitude

modulation coefficient

static unsigned int g_uiSPWM_phases_Add; // SPWM phase accumulation

static unsigned int g_uiPhases_Add_Data; // SPWM phase increment

static unsigned int PWM_shift;

void SPWM_AM_MUL(int *p_Data,unsigned int uiK);

unsigned int ASM_MUL(unsigned int a,unsigned int b);

//=====================================================================

// ----Function: void SPWM_TMR3_Init(void);

// -Description: TMR3_module initialize function

// --Parameters: None

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// -----Returns: None

// -------Notes:

//=====================================================================

void SPMC75_SPWM_Init(void)

{P_IOB_Dir->W |= 0x00bf; // IO setting 0x00ff

P_IOB_Attrib->W |= 0x00bf;

P_IOB_Buffer->W &= 0xff00;

P_IOB_Buffer->W |= 0x0047;

P_IOB_SPE->W |= 0x003f;

// MCP write enable

P_TPWM_Write->W |= CW_TWCR_TMR3WE;

/* Configure MCP control registers, make MCP operate on PWM mode, count on FCK/1,

at rising edge, clear on TPR match, interrupt every period. */

P_TMR3_Ctrl->B.PRDINT = CB_TMR3_PRDINT_Period;

P_TMR3_Ctrl->B.MODE = CB_TMR3_MODE_PWM_Center;

P_TMR3_Ctrl->B.CCLS = CB_TMR3_CCLS_TPR;

P_TMR3_Ctrl->B.CKEGS = CB_TMR3_CKEGS_Rising;

P_TMR3_Ctrl->B.TMRPS = CB_TMR3_TMRPS_FCKdiv1;

// Set dead time

P_TMR3_DeadTime->B.DTWE = 1;

P_TMR3_DeadTime->B.DTVE = 1;

P_TMR3_DeadTime->B.DTUE = 1;

P_TMR3_DeadTime->B.DTP = 4;

// Set timer period and initial duty

P_TMR3_TPR->W = 2048;P_TMR3_TGRA->W = (unsigned int)iSin_TAB[0];

P_TMR3_TGRB->W = (unsigned int)iSin_TAB[Phases_120];

P_TMR3_TGRC->W = (unsigned int)iSin_TAB[Phases_240];

// Set PWM output mode, output polarity, and IO

P_TMR3_OutputCtrl->B.DUTYMODE = CB_TMR3_DUTYMODE_Independent;

P_TMR3_OutputCtrl->B.POLP = CB_TMR3_POLP_Active_High;

P_TMR3_OutputCtrl->W |= CW_TMR3_UOC_Mode0 + CW_TMR3_VOC_Mode0;

P_TMR3_OutputCtrl->W |= CW_TMR3_WOC_Mode0 + CW_TMR3_WPWM_Out_PWM;

P_TMR3_OutputCtrl->W |= CW_TMR3_VPWM_Out_PWM + CW_TMR3_UPWM_Out_PWM;

P_TMR3_OutputCtrl->B.SYNC = CB_TMR3_SYNC_NoSync;

P_TMR3_IOCtrl->W = CW_TMR3_IOCMOD_Output_01+CW_TMR3_IOBMOD_Output_01;P_TMR3_IOCtrl->W |= CW_TMR3_IOAMOD_Output_01;

P_TMR_Output->W |= 0x003f;

P_TMR3_INT->B.TPRIE = CB_TMR3_TPRIE_Enable;

}

//=====================================================================

// ----Function: void SPWM_ISR(void);

// -Description: SPWM generating ISR

// --Parameters:

// -----Returns:

// -------Notes:

//=====================================================================

void SPMC75_SPWM_ISR(void)

{

unsigned int uiPhases_Temp;

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int iNEW_Data[3];

g_uiSPWM_phases_Add += g_uiPhases_Add_Data; // Phase accumulation

uiPhases_Temp = g_uiSPWM_phases_Add >> 6; // Obtain phase value

iNEW_Data[0] = iSin_TAB[uiPhases_Temp]; // Look up next data

iNEW_Data[1] = iSin_TAB[(uiPhases_Temp + Phases_120)&(Sin_TAB_dot - 1)];iNEW_Data[2] = iSin_TAB[(uiPhases_Temp + Phases_240)&(Sin_TAB_dot - 1)];

SPWM_AM_MUL(iNEW_Data,g_uiAM_Data); // Modulate amplitude

P_TMR3_TGRA->W = (unsigned int)iNEW_Data[0]; // Update data

P_TMR3_TGRB->W = (unsigned int)iNEW_Data[1];

P_TMR3_TGRC->W = (unsigned int)iNEW_Data[2];

P_TMR_LDOK->W |= CW_TMR_LDOK0;

// Enable data update synchronously

}

//=====================================================================

// ----Function: void SPMC75_SPWM(unsigned int F,unsigned int AM);

// -Description:

// --Parameters:

// -----Returns:

// -------Notes:

//=====================================================================

void SPMC75_SPWM(unsigned int F,unsigned int AM)

{

if(F > 0)

{

g_uiPhases_Add_Data = ASM_MUL(F,5726);

P_TMR_Start->B.TMR3ST = 1;

}

else

{

g_uiPhases_Add_Data = 0;P_TMR_Start->B.TMR3ST = 0;

}

g_uiAM_Data = AM;

}

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3 Flow Charts

3.1 Main Process Description

The main program mainly performs the system initialization, then calls SPMC75_SPWM

(unsigned int F, unsigned int AM) function to update the waveform parameters. Changing

the value of F (Q8 format) means to change the base frequency of SPWM and changing

the value of AM (Q16 format) means to change the amplitude of SPWM base frequency.

Figure 3-1 flow charts the main process.

Figure 3-1 Main Process

3.2 ISR Description

Once entering PWM period interrupt, system will perform DDS operation. By adding the

phase increment N (proportional to PWM frequency) to the initial phase, the new waveform

phase will be acquired, then look up the corresponding amplitude, 120-degree and

240-degree phase interval amplitudes. At last, multiply these three amplitude values by

AM (amplitude modulation coefficient), and then input them to PWM generating module togenerate corresponding PWM signals. Figure 3-2 flow charts the ISR process.

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Figure 3-2 ISR Process

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4 MCU Resource

CPU Type SPMC75F2413A Package QFP80-0.8

crystal Frequency 6MHz

Oscillator

external Input frequency

WATCHDOG Enable Disable

IO port Use

IOA[11]: TCLKA

IOA[12]: TCLKB

IOB[02]: PWM output

Timer MCP3 SPWM generator

Interrupt MCP3 (IRQ3): encoder interface

ROM 1.48K Words

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5 Test

5.1 Test Circuit

The test circuit, as shown in Figure 5-1, uses 2nd-order low-pass filter to filter the high

frequency component of SPWM signal thus to obtain the base frequency. In the circuit,

when andRCCRCR == 2211 21 RR

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Type

Time

Source

Delta

Coursor1

Coursor2

Type

Time

Source

Delta

Coursor1

Coursor2

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