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Non Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel

Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

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Page 1: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Non Von Neumann ArchitecturesBy Dylan Ayrey and Joshua Pueschel

Page 2: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

The agenda● Review of the Von Neumann Model● What is the Harvard Architecture● What is the Modified Harvard Architecture● Examples/Current Uses● SHARC● MIMD

Page 3: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

The Von Neumann Model● “Pure” von neumann model● Completed one after another● Limited by previous instruction

Page 4: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Von Neumann Bottleneck

● Wait for new instructions

● Idle time● “Hacky”

workarounds (caching, multi threading etc..)

Page 5: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Harvard Architecture: What is it?

● Von Neumann “alternative”

● Data memory and program instructions kept separate

● Parallel read/write from program instructions and data memory

○ Separate memory buses

Page 6: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Where did it come from?● Harvard Mark I

○ Started in 1937 by IBM○ Finished in 1944○ Used in war effort○ First program it ran created

by John Von Neumann to calculate nuclear bomb science

○ Paper punch tape

● Predates Von Neumann model (1945)

● Still used today

Page 7: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Modified Harvard Architecture● Common modifications

○ Shared memory/split cache● Most modern implementations are modified

○ Current ARM Architectures○ x86

Page 8: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Modern examples● ARM9/ARM11

○ Cellphones○ Raspberry pi○ Nintendo

● Digital Signal Processors

Page 9: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

AMD Athlon 64 Cache Hierarchy

● Modified harvard architecture split L1 Cache

● Shared L2 cache

Page 10: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Cache Structure of ARM9 Processor

● Two distinct caching levels

● Shared common memory

Page 11: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

SHARC Architecture● Extended cache for instruction reuse● Allows program bus to transfer data memory● DSP architecture

Page 12: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

SHARC Architecture

Page 13: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Modified Von Neumann● DSP Example● Need multiple memory accesses in a single

instruction● Speed up the memory clock to be faster than

a single instruction cycle

Page 14: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Other Non Von Neumann● Analog Computers● Optical Computers● Quantum Computers● Cell Processors● DNA● Neural Networks● MIMD architecture

Page 15: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Non Von Neumann● Parallelism

○ Complex / low programmability● uPD7281D

○ image pipelined processor○ Could process different commands simultaneously

Page 16: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

MIMD Architecture● Multiple Instruction stream, Multiple Data● Independent processors that operate on

separate data concurrently● Shared memory

Page 17: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

MIMD Architecture Cont.

Page 18: Architectures Non Von Neumann - Rochester Institute of ...meseec.ce.rit.edu/551-projects/spring2014/4-3.pdfNon Von Neumann Architectures By Dylan Ayrey and Joshua Pueschel. The agenda

Design problems● Processor design● Physical organization● Interconnection structure● Inter-processor communication protocols● Memory hierarchy● Cache organization and coherency● Operating system design● Parallel programming languages● Application software techniques