Bai tap VXL

i Hc Bch Khoa TP.HCM Khoa in-in T

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BI TP VI X L (H VI IU KHIN 8051) 1. CU TRC PHN CNG - GII M A CH 1.1 S dng 1 vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra cc tn hiu chn chip tng ng cc vng a ch sau: Tn hiu chn chipCS0 CS1 CS2 CS3 CS4

Vng a ch 0000H 3FFFH 4000H 7FFFH 6000H 7FFFH 8000H 87FFH 8800H 8FFFH

c tnh truy xutPSEN PSEN RD, WR RD WR

1.2 S dng 1 vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra cc tn hiu chn chip tng ng cc vng a ch sau: Tn hiu chn chipCS0 CS1 CS2 CS3

Vng a ch 9800H 9BFFH 9800H 9BFFH 9C00H 9DFFH 9E00H 9EFFH

c tnh truy xutPSEN RD, WR RD, WR RD, WR

1.3 Ch dng mt vi mch 74138 (khng dng thm cng), thit k mch gii m a ch to ra mt tn hiu chn chip /CS tng ng tm a ch F000H-F3FFH. 2. S DNG TP LNH Truy xut RAM ni

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2.1 Vit CT ghi 40H vo nh 30H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.2 Vit CT xa nh 31H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.3 Vit CT ghi ni dung thanh ghi A vo nh 32H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.4 Vit CT c nh 33H ca RAM ni vo thanh ghi A theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.5 Vit CT chuyn d liu nh 34H ca RAM ni vo nh 35H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). Truy xut RAM ngoi 2.6 Vit CT ghi 40H vo nh 0030H ca RAM ngoi. 2.7 Vit CT xa nh 0031H ca RAM ngoi. 2.8 Vit CT c nh 0032H ca RAM ngoi vo thanh ghi A. 2.8 Vit CT ghi ni dung thanh ghi A vo nh 0033H ca RAM ngoi. 2.10 Vit CT chuyn d liu nh 0034H ca RAM ngoi vo nh 0035H ca RAM ngoi. Truy xut Port 2.11 Vit CT xut 0FH ra Port 1. 2.12 Vit CT xut F0H ra Port 2. 2.13 Vit CT xut ni dung thanh ghi A ra Port 1. 2.14 Vit CT nhp t Port 1 vo thanh ghi A. 2.15 Vit CT nhp t Port 1 v xut ra Port 2. 2.16 Vit CT xut 1 (mc logic cao) ra chn P1.0 2.17 Vit CT xut 0 (mc logic thp) ra chn P1.1 Truy xut RAM ni, RAM ngoi v Port 2.18 Vit CT chuyn d liu nh 40H (RAM ni) n nh 2000H (RAM ngoi). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.19 Vit CT chuyn d liu nh 2001H (RAM ngoi) vo nh 41H (RAM ni). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.20 Vit CT nhp t Port 1 vo nh 42H (RAM ni). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip).

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2.21 Vit CT nhp t Port 1 vo nh 2002H (RAM ngoi). 2.22 Vit CT ly nh 43H (RAM ni) xut ra Port 1. Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.23 Vit CT ly nh 2003H (RAM ngoi) xut ra Port 1. S dng vng lp 2.24 Vit CT xa 20 nh RAM ni c a ch bt u l 30H. 2.25 Vit CT xa cc nh RAM ni t a ch 20H n 7FH. 2.26 Vit CT xa 250 nh RAM ngoi c a ch bt u l 4000H. 2.27 Vit CT xa 2500 nh RAM ngoi c a ch bt u l 4000H. 2.28 Vit CT xa ton b RAM ngoi c dung lng 8KB, bit rng a ch u l 2000H. 2.29 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l 30H n vng RAM ni c a ch u l 40H. 2.30 Vit CT chuyn mt chui d liu gm 100 byte trong RAM ngoi c a ch u l 2000H n vng RAM ngoi c a ch u l 4000H. 2.31 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l 30H n vng RAM ngoi c a ch u l 4000H. 2.32 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ngoi c a ch u l 5F00H n vng RAM ni c a ch u l 40H. 2.33 Cho mt chui d liu gm 20 byte lin tip trong RAM ni, bt u t a ch 20H. Hy vit CT ln lt xut cc d kiu ny ra Port 1. 2.34 Gi s Port 1 c ni n mt thit b pht d liu (v d nh 8 nt nhn). Hy vit CT nhn lin tip 10 byte d liu t thit b pht ny v ghi vo 10 nh (RAM ni) lin tip bt u t nh 50H. To tr (delay) 2.35 Vit CT con delay 100s, bit rng thch anh (xtal) dng trong h thng l: a. 12 MHz b. 6 MHz 2.36 Vit CT con delay 100ms, bit rng thch anh (xtal) dng trong h thng l: a. 12 MHz b. 11,0592 MHz 2.37 Vit CT con delay 1s, bit rng thch anh (xtal) dng trong h thng l: a. 12 MHz b. 24 MHzTrang 3/24


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To xung 2.38 Vit CT to mt xung dng ( 1ms, bit rng xtal l 12 MHz. 2.39 Vit CT to chui xung vung c f = 100 KHz ti chn P1.1 (Xtal 12 MHz). 2.40 Vit CT to chui xung vung c f = 100 KHz v c chu k lm vic D = 40% ti chn P1.2 (Xtal 12 MHz). 2.41 Vit CT to chui xung vung c f = 10 KHz ti chn P1.3 (Xtal 24 MHz). 2.42 Vit CT to chui xung vung c f = 10 KHz v c chu k lm vic D = 30% ti chn P1.3 (Xtal 24 MHz). 2.43 Vit CT to chui xung vung c f = 10 Hz ti chn P1.4 (Xtal 12 MHz). 2.44 Vit CT to chui xung vung c f = 10 Hz v c chu k lm vic D = 25% ti chn P1.5 (Xtal 12 MHz). Cc php ton 2.45 Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy vit CT con cng chui s ny v ghi kt qu vo nh 2FH (gi s kt qu nh hn hoc bng 255). 2.46 Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy vit CT con cng chui s ny v ghi kt qu vo nh 2EH:2FH ( nh 2EH cha byte cao ca kt qu v nh 2FH cha byte thp ca kt qu). 2.47 Cho mt chui s 16 bit khng du trong RAM ni gm 10 s bt u t nh 30H theo nguyn tc nh c a ch nh hn cha byte cao v nh c a ch ln hn cha byte thp. (V d: byte cao ca s 16 bit u tin c ct ti nh 30H v byte thp ca s 16 bit u tin c ct ti nh 31H). Hy vit CT con cng chui s ny v ct kt qu vo nh 2EH:2FH. 2.48 Vit CT con ly b 2 s 16 bit cha trong R2:R3. So snh 2.49 Cho hai s 8 bit, s th 1 cha trong (30H), s th 2 cha trong (31H). Vit CT con so snh hai s ny. Nu s th 1 ln hn hoc bng s th 2 th set c F0, nu ngc li th xa c F0. 2.50 Cho hai s 16 bit, s th 1 cha trong (30H):(31H), s th 2 cha trong (32H):(33H). Vit CT con so snh hai s ny. Nu s th 1 ln hn hoc bng s th 2 th set c F0, nu ngc li th xa c F0. ) ti chn P1.0 vi rng xung

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2.51 Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT xut cc k t in hoa c trong chui ny ra Port 1. Bit rng m ASCII ca k t in hoa l t 65 (ch A) n 90 (ch Z). 2.52 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v ghi c k t ny vo RAM. 2.53 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM. 2.54 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM m thay bng k t null (c m ASCII l 00H). 2.55 Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT i cc k t in hoa c trong chui ny thnh k t thng. Bit rng m ASCII ca k t thng bng m ASCII ca k t in hoa cng thm 32. 2.56 Cho mt chui k t s di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT i cc k t s ny thnh m BCD. Bit rng m ASCII ca cc k t s l t 30H (s 0) n 39H (s 9). S dng lnh nhy c iu kin 2.57 Cho mt chui d liu di dng s c du trong RAM ngoi, di 100 byte, bt u t a ch 0100H. Vit CT ln lt xut cc d liu trong chui ra Port 1 nu l s dng (xem s 0 l dng) v xut ra Port 2 nu l s m. 2.58 Cho mt chui d liu di dng s c du trong RAM ngoi, bt u t a ch 0100H v kt thc bng s 0. Vit CT ln lt xut cc d liu trong chui ra Port 1 nu l s dng v xut ra Port 2 nu l s m. 2.59 Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch 0100H v di chui l ni dung nh 00FFH. Vit CT m s s chn (chia ht cho 2) c trong chui v ct vo nh 00FEH. 2.60 Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch 0100H v di chui l ni dung nh 00FFH. Vit CT ghi cc s chn (xem s 0 l s chn) c trong chui vo RAM ni bt u t a ch 30H cho n khi gp s l th dng. 2.61 Vit CT con c nhim v ly 1 byte t 1 chui data gm 20 byte ct trong Ram ngoi bt u t a ch 2000H v xut ra Port1. Mi ln gi CT con ch xut 1 byte, ln gi k th xut byte k tip, ln gi th 21 th li xut byte u, ...

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3. TIMER 3.1 Vit CT con mang tn DELAY500 c nhim v to tr 0,5ms dng Timer. (Xtal 6MHz). 3.2 Vit CT con mang tn DELAY10 c nhim v to tr 10ms dng Timer. (Xtal 12MHz). 3.3 Dng CT con DELAY500 (bi 3.1) vit CT to sng vung f=1KHz ti P1.0. 3.4 Dng CT con DELAY10 (bi 3.2) vit CT to sng vung f=50Hz ti P1.1. 3.5 Dng CT con DELAY500 (bi 3.1) vit CT to sng vung f=500Hz (D=25%) ti P1.2. 3.6 Dng CT con DELAY10 (bi 3.2) vit CT to sng vung f=20Hz (D=20%) ti P1.3. 3.7 Vit CT dng Timer to sng vung f=500Hz ti P1.4. (Xtal 12MHz). 3.8 Vit CT dng Timer to sng vung f=20KHz ti P1.5. (Xtal 24MHz). 3.9 Vit CT dng Timer to 2 sng vung c cng f= 1KHz ti P1.6 v P1.7. Bit rng sng vung ti P1.7 chm pha hn sng vung ti P1.6 100(s. (Xtal 12MHz). 3.10 Vit CT dng Timer iu khin n giao thng ti mt giao l. Cho bit rng: n Bit iu khin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 33s 3s Th i gian 25s 3s

Xanh 1 Vng 1 1 Xanh 2 Vng 2 2 n sng khi bit iu khin bng 0. 4. SERIAL PORT

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4.1 Vit CT c 1 chui data cha trong RAM ni t a ch 30H n 50H v xut ra 1 thit b (v d nh mn hnh tinh th lng LCD) c ni vi port ni tip ca 8051 (ch UART 8 bit, 2400 baud). Cho Xtal 11,059 MHz. 4.2 Vit CT nhn 1 chui data t 1 thit b ngoi (v d nh my c m vch) ni vi 8051 qua port ni tip (ch UART 8 bit, 4800 baud) v ghi data vo RAM ni t a ch 40H. Bit rng chui data gm 20 byte v Xtal 11,059MHz. 4.3 Vit CT ly 1 chui data cha trong RAM ngoi bt u t a ch 2000H v xut ra 1 thit b c ni vi port ni tip ca 8051 (ch UART 8 bit, 1200 baud). Chui kt thc bi k t EOT (c m ASCII l 04H) v k t ny cng c xut ra (Xtal 11,059 MHz). 4.4 Lm li bi 4.3 nhng khng xut k t EOT. 4.5 Vit CT nhn 1 chui data t 1 thit b ngoi ni vi 8051 qua port ni tip (ch UART 8 bit, 9600 baud) v ghi data vo RAM ngoi bt u t a ch 4000H. Chui data bt u bng k t STX (02H) v kt thc bng k t ETX (03H). Khng ghi 2 k t ny vo RAM. Cho Xtal 11,059MHz. 4.6 Vit CT con mang tn XUAT c nhim v ly 1 chui data cha trong RAM ngoi xut ra port ni tip ch UART 9 bit. Bit th 9 l bit parity chn. Chui data kt thc bng k t null (00H). CT gi CT con XUAT s t a ch bt u ca chui vo DPTR trc khi gi CT con XUAT. Gi s port ni tip c khi ng. 4.7 Vit CT con mang tn NHAP c nhim v nhp 1 chui data gm 30 byte t port ni tip ch UART 9 bit, bit th 9 l bit parity l. Nu data nhn c khng b li th ghi vo 1 vng nh ca RAM ni, nu b li th khng ghi. CT gi CT con NHAP s t a ch u ca vng nh vo thanh ghi R0 trc khi gi CT con NHAP. Gi s port ni tip c khi ng. 5. INTERRUPT 5.1 Vit CT dng ngt Timer to sng vung f=2KHz ti P1.7. (Xtal 12MHz). 5.2 Vit CT dng ngt Timer to sng vung f=200Hz ti P1.6. (Xtal 12MHz). 5.3 Vit CT dng ngt Timer to ng thi 2 sng vung 1KHz v 50Hz ti P1.0 v P1.1. (Xtal 6MHz) 5.4 Vit CT ly 1 chui data cha trong Ram ngoi bt u t a ch 6200H n a ch 62FFH v xut ra Port1, mi ln xut cch nhau 50ms. S dng ngt Timer. Xtal 12MHz. 5.5 Vit CT nhp data t thit b ngoi kt ni vi 8051 qua Port1, mi ln nhp cch nhau 5s, data nhp v c ghi vo vng Ram ni bt u t a ch 50H

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n a ch 5FH. Bit rng sau khi ghi vo nh cui cng th tr li ghi vo nh u. S dng ngt Timer. Xtal 12MHz. 5.6 Vit CT pht lin tc chui s t 0 n 9 ra port ni tip theo ch UART 8 bit, 2400 baud. S dng ngt serial. Xtal 12MHz. 5.7 Vit CT ch nhn data t 1 thit b ngoi gi n 8051 qua port ni tip (ch UART 8 bit, 19200 baud). Nu nhn c k t STX (02H) th bt sng LED, nu nhn c k t ETX (03H) th tt LED, bit rng LED c iu khin bng ng P1.3 (LED sng khi bit iu khin bng 1). S dng ngt serial. Xtal 11,059MHz. 5.8 Vit CT ch nhn 1 xung cnh xung a vo chn /INT0 (P3.2), khi c xung th nhp data t Port1 v pht ra port ni tip ch UART 9 bit 4800 baud, bit th 9 l bit parity l. Xtal 6MHz. 5.9 Vit CT m s xung a vo chn /INT1 (P3.3) v iu khin relay thng qua chn P3.0 (relay ng khi P3.0 bng 1), ct s m vo nh 40H ca Ram ni, nu s m cha n 100 th ng relay, nu s m t 100 th ngt relay.

P N VI X L (H VI IU KHIN 8051) 1. CU TRC PHN CNG - GII M A CH 1.1 S dng 1 vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra cc tn hiu chn chip tng ng cc vng a ch sau: Tn hiu chn chip Vng a ch c tnh truy xut 0000H - 3FFFH 4000H - 7FFFH 6000H - 7FFFH 8000H - 87FFH 8800H - 8FFFH 1.2 S dng 1 vi mch 74138 v cc cng cn thit thit k mch gii m a ch to ra cc tn hiu chn chip tng ng cc vng a ch sau: Tn hiu chn chip Vng a ch c tnh truy xut

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9800H - 9BFFH 9800H - 9BFFH 9C00H - 9DFFH 9E00H - 9EFFH 1.3 Ch dng mt vi mch 74138 (khng dng thm cng), thit k mch gii m a ch to ra mt tn hiu chn chip /CS tng ng tm a ch F000H-F3FFH.

2. S DNG TP LNH Truy xut RAM ni2.1 Vit CT ghi 40H vo nh 30H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). Cch 1: nh a ch trc tip ORG 0000H MOV 30H,#40H END Cch 2: nh a ch gin tip ORG 0000H MOV R0,#30H MOV @R0,#40H END 2.2 Vit CT xa nh 31H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). HD: Xa l ghi gi tr 0. ORG 0000H MOV 31H,#OOOOH END. C2 ORG MOV R0,#31H MOV @R0,#0000H END. 2.3 Vit CT ghi ni dung thanh ghi A vo nh 32H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). CCH 1: ORG 0000HTrang 9/24


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MOV 32H,A END CCH 2: ORG 0000H MOV R0,#32H MOV @R0,A END 2.4 Vit CT c nh 33H ca RAM ni vo thanh ghi A theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). CCH 1: ORG 0000H MOV A,33H END CCH 2: ORG 0000H MOV R0,#33H MOV A,@R0 END 2.5 Vit CT chuyn d liu nh 34H ca RAM ni vo nh 35H ca RAM ni theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). CCH 1: ORG 0000H MOV 35H,34H END CCH 2: ORG 0000H MOV R0,#34H MOV A,@R0 INC R0 MOV @R0,A END Truy xut RAM ngoi 2.6 Vit CT ghi 40H vo nh 0030H ca RAM ngoi. ORG 0000H MOV A,#40H MOV DPTR,#0030H MOVX @DPTR,A END 2.7 Vit CT xa nh 0031H ca RAM ngoi. ORG 0000H MOV A,#0000H MOV DPTR,#0031H MOVX @DPTR,ATrang 10/24


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END. HD: Ghi gi tr 0. 2.8 Vit CT c nh 0032H ca RAM ngoi vo thanh ghi A. ORG 0000H MOV DPTR,#0032H MOVX A,@DPTR END 2.8 Vit CT ghi ni dung thanh ghi A vo nh 0033H ca RAM ngoi. ORG 0000H MOV DPTR,#0033H MOVX @DPTR,A END 2.10 Vit CT chuyn d liu nh 0034H ca RAM ngoi vo nh 0035H ca RAM ngoi. ORG 0000H MOV DPTR,#0034H MOVX A,@DPTR INC DPTR MOVX @DPTR,A END Truy xut Port 2.11 Vit CT xut 0FH ra Port 1. ORG 0000H MOV P1,#0FH END 2.12 Vit CT xut F0H ra Port 2. 2.13 Vit CT xut ni dung thanh ghi A ra Port 1. ORG 0000H MOV P1,A END 2.14 Vit CT nhp t Port 1 vo thanh ghi A. ORG 0000H MOV A,P1 END 2.15 Vit CT nhp t Port 1 v xut ra Port 2. 0FH ORG 0000H MOV 0FH,P1 MOV P2,#0FH END 2.16 Vit CT xut 1 (mc logic cao) ra chn P1.0 ORG 0000H SETB P1.0Trang 11/24


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END 2.17 Vit CT xut 0 (mc logic thp) ra chn P1.1 ORG 0000H CLR P1.1 END

Truy xut RAM ni, RAM ngoi v Port2.18 Vit CT chuyn d liu nh 40H (RAM ni) n nh 2000H (RAM ngoi). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). CCH 1: ORG 0000H MOV A,40H MOV DPTR,#2000H MOVX @DPTR,A END CCH 2: ORG 0000H MOV R0,#40H MOV DPTR,#2000H MOV A,@R0 MOVX @DPTR,A END 2.19 Vit CT chuyn d liu nh 2001H (RAM ngoi) vo nh 41H (RAM ni). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). ORG 0000H MOV DPRT,#2001H MOV A,41H MOVX A,@DPRT END C2 ORG 0000H 2.20 Vit CT nhp t Port 1 vo nh 42H (RAM ni). Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). CCH 1: ORG 0000H MOV 42H,P1 END CCH 2: ORG 0000H MOV R0,#40H MOV @R0,P1Trang 12/24


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END 2.21 Vit CT nhp t Port 1 vo nh 2002H (RAM ngoi). ORG 0000H MOV DPTR,#2002H MOV A,P1 MOVX @DPTR,A END 2.22 Vit CT ly nh 43H (RAM ni) xut ra Port 1. Lm theo 2 cch (nh a ch nh trc tip v nh a ch nh gin tip). 2.23 Vit CT ly nh 2003H (RAM ngoi) xut ra Port 1.

S dng vng lp2.24 Vit CT xa 20 nh RAM ni c a ch bt u l 30H. ORG 0000H MOV R0,#30H MOV R2,#20 laplai: MOV @R0,#0 INC R0 DJNZ R2,laplai END 2.25 Vit CT xa cc nh RAM ni t a ch 20H n 7FH. ORG 0000H MOV R0,#20H laplai: MOV @R0,#0 INC R0 CJNE R0,#80H,laplai END 2.26 Vit CT xa 250 nh RAM ngoi c a ch bt u l 4000H. ORG 0000H MOV DPTR,#4000H CLR A MOV R7,#250 lap1: MOVX @DPTR,A INC DPTR DJNZ R7,lap1 END 2.27 Vit CT xa 2500 nh RAM ngoi c a ch bt u l 4000H. ORG 0000H MOV DPTR,#4000H CLR A MOV R6,#10 lap2: MOV R7,#250Trang 13/24


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lap1: MOVX @DPTR,A INC DPTR DJNZ R7,lap1 DJNZ R6,lap2 END 2.28 Vit CT xa ton b RAM ngoi c dung lng 8KB, bit rng a ch u l 2000H. HD: 8KB = 8192Byte 2.29 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l 30H n vng RAM ni c a ch u l 40H. ORG 0000H MOV R0,#30H MOV R1,#40H MOV R2,#10 lap: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,lap END 2.30 Vit CT chuyn mt chui d liu gm 100 byte trong RAM ngoi c a ch u l 2000H n vng RAM ngoi c a ch u l 4000H. ORG 0000H MOV R0,#100H Lap MOV DPRT,#2000H MOVX A,@DPRT MOV DPRT,#4000H MOVX @DPRT,A INC DPRT DJNZ R0,Lap END.` 2.31 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ni c a ch u l 30H n vng RAM ngoi c a ch u l 4000H. ORG 0000H MOV R0,#30H MOV DPTR,#4000H MOV R3,#10 lap: MOV A,@R0 MOVX @DPTR,A INC R0 INC DPTR DJNZ R3,lap`Trang 14/24


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END 2.32 Vit CT chuyn mt chui d liu gm 10 byte trong RAM ngoi c a ch u l 5F00H n vng RAM ni c a ch u l 40H. 2.33 Cho mt chui d liu gm 20 byte lin tip trong RAM ni, bt u t a ch 20H. Hy vit CT ln lt xut cc d kiu ny ra Port 1. 2.34 Gi s Port 1 c ni n mt thit b pht d liu (v d nh 8 nt nhn). Hy vit CT nhn lin tip 10 byte d liu t thit b pht ny v ghi vo 10 nh (RAM ni) lin tip bt u t nh 50H. ORG 0000H MOV R0,#50H MOV R4,#10 loop: MOV @R0,P1 INC R0 DJNZ R4,loop END

To tr (delay)2.35 Vit CT con delay 100s, bit rng thch anh (xtal) dng trong h thng l: a. 12 MHz Vi thch anh 12MHz th chu k my TM = 1s. Do , 100 s = 100 TM (chu ky may)ctcondelay: MOV R2,#50 DJNZ R2,$ RET b. 6 MHz Vi thch anh 6MHz th chu k my TM = 2s. Do , 100 s = 50 TM ctcondelay: MOV R2,#25 DJNZ R2,$ RET 2.36 Vit CT con delay 100ms, bit rng thch anh (xtal) dng trong h thng l: a. 12 MHz Vi thch anh 12MHz th chu k my TM = 1s. Do , 100 ms = 100000 TM ctcondelay: MOV R3,#200 lap: MOV R2,#250 DJNZ R2,$ (lenh rong, tao xung 250) DJNZ R3,#lap RET b. 11,0592 MHz 2.37 Vit CT con delay 1s, bit rng thch anh (xtal) dng trong h thng l:1000ms a. 12 MHz b. 24 MHzTrang 15/24


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To xung2.38 Vit CT to mt xung dng ( ) ti chn P1.0 vi rng xung 1ms, bit rng xtal l 12 MHz. CCH 1: ORG 0000H CLR P1.0 SETB P1.0 MOV R3,#2 lap: MOV R2,#250 DJNZ R2,$ DJNZ R3,lap CLR P1.0 END CCH 2: ORG 0000H CLR P1.0 SETB P1.0 ACALL delay1ms CLR P1.0 SJMP ketthuc (la lenh nhay ngan, dieu khien chuong trinh re nhanh delay1ms: den dia chi duoc tro den) MOV R3,#2 lap: MOV R2,#250 DJNZ R2,$ DJNZ R3,lap RET ketthuc: NOP END 2.39 Vit CT to chui xung vung c f = 100 KHz ti chn P1.1 (Xtal 12 MHz). ORG 0000H lap: CPL P1.1 NOP NOP SJMP lap END 2.40 Vit CT to chui xung vung c f = 100 KHz v c chu k lm vic D = 40% ti chn P1.2 (Xtal 12 MHz). ORG 0000H lap: SETB P1.2 NOP NOPTrang 16/24


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NOP CLR P1.2 NOP NOP NOP SJMP lap END 2.41 Vit CT to chui xung vung c f = 10 KHz ti chn P1.3 (Xtal 24 MHz). ORG 0000H lap: CPL P1.3 ACALL delay50 SJMP lap delay50: MOV R4,#25 DJNZ R4,$ RET END 2.42 Vit CT to chui xung vung c f = 10 KHz v c chu k lm vic D = 30% ti chn P1.3 (Xtal 24 MHz). ORG 0000H lap: SETB P1.3 ACALL delay30 CLR P1.3 ACALL delay70 SJMP lap delay30: MOV R4,#15 DJNZ R4,$ RET delay70: MOV R4,#35 DJNZ R4,$ RET END 2.43 Vit CT to chui xung vung c f = 10 Hz ti chn P1.4 (Xtal 12 MHz). 2.44 Vit CT to chui xung vung c f = 10 Hz v c chu k lm vic D = 25% ti chn P1.5 (Xtal 12 MHz).

Cc php ton2.45 Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy vit CT con cng chui s ny v ghi kt qu vo nh 2FH (gi s kt qu nh hn hoc bng 255). ORG 0000H MOV R0,#30HTrang 17/24


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CLR A MOV R2,#10 lap: ADD A,@R0 INC R0 DJNZ R2,lap MOV 2FH,A END 2.46 Cho mt chui s 8 bit khng du trong RAM ni gm 10 s bt u t nh 30H. Hy vit CT con cng chui s ny v ghi kt qu vo nh 2EH:2FH ( nh 2EH cha byte cao ca kt qu v nh 2FH cha byte thp ca kt qu). ORG 0000H MOV R0,#30H ;a ch bt u MOV R2,#10 ;s ln lp CLR A ;byte thp ca kt qu MOV 2EH,#0000H ;byte cao ca kt qu CLR C lap: ADD A,@R0 JNC boqua ; (nhay neu co carry flag nho khong duoc set bang 1) INC 2EH boqua:INC R0 DJNZ R2,lap MOV 2FH,A END 2.47 Cho mt chui s 16 bit khng du trong RAM ni gm 10 s bt u t nh 30H theo nguyn tc nh c a ch nh hn cha byte cao v nh c a ch ln hn cha byte thp. (V d: byte cao ca s 16 bit u tin c ct ti nh 30H v byte thp ca s 16 bit u tin c ct ti nh 31H). Hy vit CT con cng chui s ny v ct kt qu vo nh 2EH:2FH. 2.48 Vit CT con ly b 2 s 16 bit cha trong R2:R3.

So snh2.49 Cho hai s 8 bit, s th 1 cha trong (30H), s th 2 cha trong (31H). Vit CT con so snh hai s ny. Nu s th 1 ln hn hoc bng s th 2 th set c F0, nu ngc li th xa c F0. ORG 0000H MOV A,30H CJNE A,31H,ke hoac CJNE A,31H,$+3 ke: JNC lonhoacbang JNC lonhoacbang CLR F0 SJMP tiep lonhoacbang: SETB F0Trang 18/24


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tiep: NOP END 2.50 Cho hai s 16 bit, s th 1 cha trong (30H):(31H), s th 2 cha trong (32H):(33H). Vit CT con so snh hai s ny. Nu s th 1 ln hn hoc bng s th 2 th set c F0, nu ngc li th xa c F0. 2.51 Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT xut cc k t in hoa c trong chui ny ra Port 1. Bit rng m ASCII ca k t in hoa l t 65 (ch A) n 90 (ch Z). ORG 0000H MOV R0,#50H MOV R3,#20 lap: MOV A,@R0 CJNE A,#65,ke hoac CJNE A,#65,$+3 ke: JC boqua JC boqua CJNE A,#91,ke2 CJNE A,#91,$+3 ke2: JNC boqua JNC boqua MOV P1,A boqua:INC R0 DJNZ R3,lap END 2.52 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v ghi c k t ny vo RAM. ORG 0000H MOV DPTR,#0000H tiep: MOV A,P1 MOVX @DPTR,A INC DPTR CJNE A,#0DH,tiep END 2.53 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM. ORG 0000H MOV DPTR,#0000H lap: MOV A,P1 CJNE A,#0DH,tiep SJMP ketthuc tiep: MOVX @DPTR,A INC DPTR SJMP lap ketthuc: NOPTrang 19/24


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END 2.54 Vit CT nhp mt chui k t t Port 1 di dng m ASCII v ghi vo RAM ngoi, bt u t a ch 0000H. Bit rng chui ny kt thc bng k t CR (c m ASCII l 0DH) v khng ghi k t ny vo RAM m thay bng k t null (c m ASCII l 00H). 2.55 Cho mt chui k t di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT i cc k t in hoa c trong chui ny thnh k t thng. Bit rng m ASCII ca k t thng bng m ASCII ca k t in hoa cng thm 32. 2.56 Cho mt chui k t s di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT i cc k t s ny thnh m BCD. Bit rng m ASCII ca cc k t s l t 30H (s 0) n 39H (s 9).

S dng lnh nhy c iu kin2.57 Cho mt chui d liu di dng s c du trong RAM ngoi, di 100 byte, bt u t a ch 0100H. Vit CT ln lt xut cc d liu trong chui ra Port 1 nu l s dng (xem s 0 l dng) v xut ra Port 2 nu l s m. ORG 0000H MOV DPTR,#0100H MOV R4,#100 lap: MOVX A,@DPTR JNB ACC.7,duong MOV P2,A SJMP tiep duong:MOV P1,A tiep: INC DPTR DJNZ R4,lap END 2.58 Cho mt chui d liu di dng s c du trong RAM ngoi, bt u t a ch 0100H v kt thc bng s 0. Vit CT ln lt xut cc d liu trong chui ra Port 1 nu l s dng v xut ra Port 2 nu l s m. ORG 0000H MOV DPTR,#0100H lap: MOVX A,@DPTR JNB ACC.7,duong MOV P2,A SJMP tiep duong:MOV P1,A tiep: INC DPTR CJNE A,#0,lap END 2.59 Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch 0100H v di chui l ni dung nh 00FFH. Vit CT m s s chn (chia ht cho 2) c trong chui v ct vo nh 00FEH.Trang 20/24


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HD: S chn c LSB=0 2.60 Cho mt chui d liu di dng s khng du trong RAM ngoi, bt u t a ch 0100H v di chui l ni dung nh 00FFH. Vit CT ghi cc s chn (xem s 0 l s chn) c trong chui vo RAM ni bt u t a ch 30H cho n khi gp s l th dng. 2.61 Vit CT con c nhim v ly 1 byte t 1 chui data gm 20 byte ct trong Ram ngoi bt u t a ch 2000H v xut ra Port1. Mi ln gi CT con ch xut 1 byte, ln gi k th xut byte k tip, ln gi th 21 th li xut byte u, ...

3. TIMER3.1 Vit CT con mang tn DELAY500 c nhim v to tr 0,5ms dng Timer. (Xtal 6MHz). MOV TMOD,#00000010B delay500: MOV TL0,#-250 SETB TR0 JNB TF0,$ CLR TR0 CLR TF0 RET 3.2 Vit CT con mang tn DELAY10 c nhim v to tr 10ms dng Timer. (Xtal 12MHz). MOV TMOD,#00000001B delay10: MOV TH0,#HIGH(-10000) MOV TL0,#LOW(-10000) SETB TR0 JNB TF0,$ CLR TR0 CLR TF0 RET 3.3 Dng CT con DELAY500 (bi 3.1) vit CT to sng vung f=1KHz ti P1.0. 3.4 Dng CT con DELAY10 (bi 3.2) vit CT to sng vung f=50Hz ti P1.1. 3.5 Dng CT con DELAY500 (bi 3.1) vit CT to sng vung f=500Hz (D=25%) ti P1.2. 3.6 Dng CT con DELAY10 (bi 3.2) vit CT to sng vung f=20Hz (D=20%) ti P1.3.Trang 21/24


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3.7 Vit CT dng Timer to sng vung f=500Hz ti P1.4. (Xtal 12MHz). 3.8 Vit CT dng Timer to sng vung f=20KHz ti P1.5. (Xtal 24MHz). 3.9 Vit CT dng Timer to 2 sng vung c cng f= 1KHz ti P1.6 v P1.7. Bit rng sng vung ti P1.7 chm pha hn sng vung ti P1.6 100(s. (Xtal 12MHz). 3.10 Vit CT dng Timer iu khin n giao thng ti mt giao l. Cho bit rng: n Bit iu khin Thi gian Xanh 1 P1.0 25s Vng 1 P1.1 3s 1 P1.2 Xanh 2 P1.3 33s Vng 2 P1.4 3s 2 P1.5 n sng khi bit iu khin bng 0.

4. SERIAL PORT4.1 Vit CT c 1 chui data cha trong RAM ni t a ch 30H n 50H v xut ra 1 thit b (v d nh mn hnh tinh th lng LCD) c ni vi port ni tip ca 8051 (ch UART 8 bit, 2400 baud). Cho Xtal 11,059 MHz. ORG 0000H MOV TMOD,#00100000B MOV SCON,#01010010B MOV TH1,#-12 SETB TR1 MOV R0,#30H lap: MOV A,@R0 JNB TI,$ CLR TI MOV SBUF,A INC R0 CJNE R0,#51H,lap END 4.2 Vit CT nhn 1 chui data t 1 thit b ngoi (v d nh my c m vch) ni vi 8051 qua port ni tip (ch UART 8 bit, 4800 baud) v ghi data vo RAM ni t a ch 40H. Bit rng chui data gm 20 byte v Xtal 11,059MHz. ORG 0000H MOV TMOD,#00100000B MOV SCON,#01010010B MOV TH1,#-6 SETB TR1 MOV R0,#40H MOV R2,#20 lap: JNB RI,$Trang 22/24


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CLR RI MOV A,SBUF MOV @R0,A INC R0 DJNZ R2,lap END 4.3 Vit CT ly 1 chui data cha trong RAM ngoi bt u t a ch 2000H v xut ra 1 thit b c ni vi port ni tip ca 8051 (ch UART 8 bit, 1200 baud). Chui kt thc bi k t EOT (c m ASCII l 04H) v k t ny cng c xut ra (Xtal 11,059 MHz). 4.4 Lm li bi 4.3 nhng khng xut k t EOT. 4.5 Vit CT nhn 1 chui data t 1 thit b ngoi ni vi 8051 qua port ni tip (ch UART 8 bit, 9600 baud) v ghi data vo RAM ngoi bt u t a ch 4000H. Chui data bt u bng k t STX (02H) v kt thc bng k t ETX (03H). Khng ghi 2 k t ny vo RAM. Cho Xtal 11,059MHz. 4.6 Vit CT con mang tn XUAT c nhim v ly 1 chui data cha trong RAM ngoi xut ra port ni tip ch UART 9 bit. Bit th 9 l bit parity chn. Chui data kt thc bng k t null (00H). CT gi CT con XUAT s t a ch bt u ca chui vo DPTR trc khi gi CT con XUAT. Gi s port ni tip c khi ng. 4.7 Vit CT con mang tn NHAP c nhim v nhp 1 chui data gm 30 byte t port ni tip ch UART 9 bit, bit th 9 l bit parity l. Nu data nhn c khng b li th ghi vo 1 vng nh ca RAM ni, nu b li th khng ghi. CT gi CT con NHAP s t a ch u ca vng nh vo thanh ghi R0 trc khi gi CT con NHAP. Gi s port ni tip c khi ng.

5. INTERRUPT5.1 Vit CT dng ngt Timer to sng vung f=2KHz ti P1.7. (Xtal 12MHz). 5.2 Vit CT dng ngt Timer to sng vung f=200Hz ti P1.6. (Xtal 12MHz). 5.3 Vit CT dng ngt Timer to ng thi 2 sng vung 1KHz v 50Hz ti P1.0 v P1.1. (Xtal 6MHz) 5.4 Vit CT ly 1 chui data cha trong Ram ngoi bt u t a ch 6200H n a ch 62FFH v xut ra Port1, mi ln xut cch nhau 50ms. S dng ngt Timer. Xtal 12MHz. 5.5 Vit CT nhp data t thit b ngoi kt ni vi 8051 qua Port1, mi ln nhp cch nhau 5s, data nhp v c ghi vo vng Ram ni bt u t a ch 50H n a ch 5FH. Bit rng sau khi ghi vo nh cui cng th tr li ghi vo nh u. S dng ngt Timer. Xtal 12MHz. 5.6 Vit CT pht lin tc chui s t 0 n 9 ra port ni tip theo ch UART 8 bit, 2400 baud. S dng ngt serial. Xtal 12MHz. 5.7 Vit CT ch nhn data t 1 thit b ngoi gi n 8051 qua port ni tip (ch UART 8 bit, 19200 baud). Nu nhn c k t STX (02H) th bt sngTrang 23/24


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LED, nu nhn c k t ETX (03H) th tt LED, bit rng LED c iu khin bng ng P1.3 (LED sng khi bit iu khin bng 1). S dng ngt serial. Xtal 11,059MHz. 5.8 Vit CT ch nhn 1 xung cnh xung a vo chn /INT0 (P3.2), khi c xung th nhp data t Port1 v pht ra port ni tip ch UART 9 bit 4800 baud, bit th 9 l bit parity l. Xtal 6MHz. 5.9 Vit CT m s xung a vo chn /INT1 (P3.3) v iu khin relay thng qua chn P3.0 (relay ng khi P3.0 bng 1), ct s m vo nh 40H ca Ram ni, nu s m cha n 100 th ng relay, nu s m t 100 th ngt relay. My ci ny c ch lm y pc no b qua thi l thi v th ng c m tic nghe:0y34: :01p2: :0y36:

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