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COMPUTER HARDWARELecture 5 - Combinational Logic (II)

Half Subtractor

It is a combination circuit with two inputs and two outputs (difference and borrow)It produces the difference between the two binary bits Also it produces a output (Borrow) to indicate if a 1 has been borrowedIn the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit

Full Subtractor

The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'.

C is the borrow produced by the previous stage,

D is the difference output

C' is the borrow output

Multiplexers

It is a digital circuit which selects one of the n data inputs and routes it to the output.

one out of n data sources is selected and transmitted to the single output Y

E is called the strobe or enable input

It is an active low terminal

Multiplexers come in multiple variations2 : 1 multiplexer4 : 1 multiplexer16 : 1 multiplexer32 : 1 multiplexer

2:1 Multiplexer

4-Input Multiplexer

Select Inputs

Implementing MultiplexerThe first n - 1 variables of the function are connected to the selection inputs of the multiplexer

The remaining single variable of the function is used for the data inputs

If the single variable is denoted by zdata input of the multiplexer will be z, z', 1 or O

EX : f(x, y, z) = (1,2,6,7)

Example

The two variables x and y are applied to the selection lines (respectively s1 & s0)

When xy= 00 output F = z because F = 0 when z = 0 and F = 1 when z = 1

so variable z be applied to data input O

the required input to data lines 1, 2 and 3 from the value of Fwhen xy = 01, 10, and 11 respectively

Result

Demultiplexers

It performs the reverse operation of a multiplexer i.e. it receives one input and distributes several outputsIt has only one input, n outputs, m select inputAt a time only one output line is selected by the select lines and the input is transmitted to the selected output lineDemultiplexers come in multiple variations1 : 2 demultiplexer1 : 4 demultiplexer1 : 16 demultiplexer1 : 32 demultiplexer

Mux/Demux Vocabulary

MULTIPLEXER (DATA SELECTOR)- circuit that can select one of a number of inputs and pass the logic level of that input to the output.

DEMULTIPLEXER (DATA DISTRIBUTOR)- circuit that depending on the status of its select inputs will channel its data input to one of several outputs.

SELECT INPUTS (ADDRESS LINES)- used by the mux to determine which data inputs will be switched to the output.

Mux / demux

DemultiplexerA decoder with enable input can function as a de-multiplexer

De-mux receives information from a single line and directs it to one of 2n possible output lines

The selection of a specific output is controlled by the bit combination of n selection lines

a decoder with an enable input is referred to as a decoder-demux

Decoder

It has n input and to a maximum m = 2n outputs

Decoder is identical to a demultiplexer without any data input

Examples of Decoders are following.Code convertersBCD to seven segment decoders

BinaryDecoder ninputs2n outputs2-to-4 Binary Decoders From truth table, circuit for 2x4 decoder is:Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

F0 = X'Y'F1 = X'YF2 = XY'F3 = XYXYTruth Table: 2-to-4DecoderXYF0

F1

F2

F3E2-to-4 Decoders : NAND ImplementationDecoder is enabled when E=0 and an output is active if it is 0

3-to-8 Decoder

3-to-8 Decoder

Connecting DecodersDecoders with enable inputs can be connected together to form a larger decoder circuit

When w = O Top decoder enabled & other disabled

When w = Ithe enable conditions are reversed

4 x 16 decoder with two 3 x 8 decordersCombining two 2-4 decoders to form one 3-8 decoder using enable switchThe highest bit is used for the enables

Demultiplexer 1-of-8 Decoder

Encoders

Digital circuit that performs the inverse operation of a decoder.

An encoder has 2n(or fewer) input lines and n output lines

3 OR Gates ImplementationA0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7

Examples of Encoders are following.Priority encodersDecimal to BCD encoderOctal to binary encoderHexadecimal to binary encode

ENCODE2nnPriority Encoder

Priority is given to the input lines.

If two or more input line are 1 at the same time, then the input line with highest priority will be considered.

Priority Encoder Circuit

Three-State GatesDigital circuits that exhibit three states

Two of the states logic 1 and logic 0 as in a conventional gateThe third state is a high -impedance state

Most commonly used is the buffer gate

Construction of multiplexers with three-state buffers

Questions

Implement the function with a multiplexer F(A,B,C,D) = (1,3,4,11,12,13,14,15)

Design a logic diagram of a 2-to-4 line decoder using NOR gates only andNAND gates only Use an enable input

Construct a 5- to-32 line decoder with four 3-to 8 line decoders with enable and a 2-to-4 line decoder. Use block diagram for the components

Construct a 4-to-16 line decoder with five 2-to-4 line decoders with enable.

5. Construct a 16 X 1 multiplexer with two 8 X 1 and one 2 X 1 multiplexers. Use block diagrams.

Questions Implement the following Boolean function with a multiplexerF(A,B,C,D) = (0,2,5,7,11,14)

Implement a full adder with two 4 x 1 multiplexers.

Design a combinational circuit that compares two four bit numbers to check if they are equal. The circuit output is equal to 1 if the two numbers are equal and 0 otherwise

An 8 X 1 multiplexer has inputs A, B and C connected to the selection inputs s2, s1 and s0 respectively. The data inputs I0through I7are as follows: I1 = I2 = I7=0 : I3=I5=1: I0=I4=D: and I6=D

Determine the Boolean function that the multiplexer implements. Draw the diagram

S1S0OUTPUT

00Z=I0

01Z=I1

10Z=I2

11Z=I3

XYF0F1F2F3

001000

010100

100010

110001