Chuong 12_LCD - ADC - Cam Bien - Smith.N Studio

8/2/2019 Chuong 12_LCD - ADC - Cam Bien - Smith.N Studio

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Ch-ng 12

Phi ghp vi th gii thc: LCD, ADC v cc cm bin

Ch-ng ny khm ph mt s ng dng ca 8051 vi th gii thc. Chng tagii thch lm cch no phi ghp 8051 vi cc thit b nh- l LCD, ADC v cc

cm bin.12.1 Phi ghp mt LCD vi 8051. phn ny ta s m t cc ch hot ng ca cc LCD v sau m t

cch lp trnh v phi ghp mt LCD ti 8051.12.1.1 Hot ng ca LCD.

Trong nhng nm gn y LCD ang ngy cng -c s dng rng ri thayth dn cho cc n LED (cc n LED 7 on hay nhiu on). l v cc nguynnhn sau:1. Cc LCD c gi thnh h.2. Kh nng hin th cc s, cc k t v ho tt hn nhiu so vi cc n LED

(v cc n LED ch hin th -c cc s v mt s k t).3. Nh kt hp mt b iu khin lm t-i vo LCD lm gii phng cho CPU cng

vic lm t-i LCD. Trong khi n LED phi -c lm t-i bng CPU (hoc bngcch no ) duy tr vic hin th d liu.

4. D dng lp trnh cho cc k t v ho.12.1.2 M t cc chn ca LCD.

LCD -c ni trong mc ny c 14 chn, chc nng ca cc chn -c chotrong bng 12.1. V tr ca cc chn -c m t trn hnh 12.1 cho nhiu LCD khcnhau.1. Chn V CC, V SS v V EE: Cc chn V CC, V SS v V EE: Cp d-ng ngun 5v v t

t-ng ng th VEE -c dng iu khin t-ng phn ca LCD.

2. Chn chn thanh ghi RS (Register Select).C hai thanh ghi rt quan trng bn trong LCD, chn RS -c dng chncc thanh ghi ny nh- sau: Nu RS= 0 th thanh ghi m lnh -c chn cho phpng-i dng gi mt lnh chng hn nh- xo mn hnh, -a con tr v u dngv.v Nu RS= 1 th thanh ghi d liu -c chn cho php ng-i dng gi d liucn hin th trn LCD.3. Chn c / ghi (R /W).

u vo c / ghi cho php ng-i dng ghi thng tin ln LCD khi R /W = 0hoc c thng tin t n khi R /W = 1.4. Chn cho php E (Enable).

Chn cho php E -c s dng b i LCD cht thng tin hin hu trn chnd liu ca n. Khi d liu -c cp n chn d liu th mtxung mc cao xungthp phi -c p n chn ny LCD cht d liu trn cc chn d liu.Xung nyphi rng ti thiu l 450ns.5. Chn D0 D7.

y l 8 chn d liu 8 bt, -c dng gi thng tin ln LCD hoc c nidung ca cc thanh ghi trong LCD.

hin th cc ch ci v cc con s, chng ta gi cc m ASCII ca cc ch ci t A nZ, a nf v cc con s t 0 9 n cc chn ny khi bt RS= 1.

Smith Nguyen S tudio.


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Cng c cc m lnh m c th -c gi n LCD xo mn hnh hoc -acon tr v u dng hoc nhp nhy con tr. Bng 12.2 lit k cc m lnh.

Chng ta cng s dng RS = 0 kim tra bt c bn xem LCD c s nsng nhn thng tin. C bn l D7 v c th -cc khi R /W = 1 v RS= 0 nh- sau:

Nu R /W = 1, RS = 0 khi D7 = 1 (c bn 1) th LCD bn b i cc cng vic

bn trong v s khng nhn bt k thng tin mi no. Khi D7 = 0 th LCD s n sngnhn thng tin mi. L-u chng ta nn kim tra c bn tr-c khi ghi bt k d liuno ln LCD.

Bng 12.1: M t cc chn ca LCD.

Chn K hiu I/O M t1 VSS t2 VCC D-ng ngun 5v3 VEE Cp ngun iu khin phn4 RS I RS = 0 chn thanh ghi lnh. RS= 1 chn

thanh d liu5 R /W I R /W = 1 c d liu. R /W = 0 ghi6 E I/O Cho php7 DB0 I/O Cc bt d liu8 DB1 I/O Cc bt d liu9 DB2 I/O Cc bt d liu

10 DB3 I/O Cc bt d liu11 DB4 I/O Cc bt d liu12 DB5 I/O Cc bt d liu13 DB6 I/O Cc bt d liu14 DB7 I/O Cc bt d liu

Bng 12.2: Cc m lnh LCD.

M (Hex) Lnh n thanh ghi ca LCD1 Xo mn hnh hin th2 Tr v u dng4 Gi con tr (dch con tr sang tri)6 Tng con tr (dch con tr sang phi)5 Dch hin th sang phi7 Dch hin th sang tri

8 T t con tr, tt hin thA T t hin th, bt con tr C Bt hin th, tt con tr E Bt hin th, nhp nhy con tr F T t con tr, nhp nhy con tr 10 Dch v tr con tr sang tri14 Dch v tr con tr sang phi18 Dch ton b hin th sang tri



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1C Dch ton b hin th sang phi80 p con tr V u dng th nhtC0 p con tr V u dng th hai38 Hai dng v ma trn 5 7

Ghi ch: Bng ny -c m rng t bng 12.4.

Hnh 12.1:Cc v tr chn ca cc LCD khc nhau caOptrex.12.1.3 Gi cc lnh v d liu n LCD vi mt tr.

gi mt lnh bt k t bng 12.2 n LCD ta phi -a chn RS v 0. ivi d liu th bt RS= 1 sau gi mt s-n xung cao xung thp n chn E cho php cht d liu trong LCD. iu ny -c ch ra trong on m ch-ng trnhd-i y (xem hnh 12.2).

; gi thi gian tr tr-c khi gi d liu/ lnh k tip.; chn P1.0 n P1.7 -c ni ti chn d d liu D0 D7 ca LCD.; Chn P2.0 -c ni ti chn RS ca LCD.; Chn P2.1 -c ni ti chn R/W ca LCD.; Chn P2.2 -c ni n chn E ca LCD.

ORGMOV A, # 38H ; Khi to LCD hai dng vi ma trn 5 7ACALL COMNWRT ; Gi ch-ng trnh con lnhACALL DELAY ; Cho LCD mt trMOV A, # 0EH ; Hin th mn hnh v con trACALL COMNWRT ; Gi ch-ng trnh con lnhACALL DELAY ; Cp mt tr cho LCDMOV AM # 01 ; Xo LCDACALL COMNWRT ; Gi ch-ng trnh con lnhACALL DELAY ; To tr cho LCDMOV A, # 06H ; Dch con tr sang phiACALL COMNWRT ; Gi ch-ng trnh con lnhACALL DELAY ; To tr cho LCDMOV AM # 48H ; -a con tr v dng 1 ct 4ACALL COMNWRT ; Gi ch-ng trnh con lnh

12 14

14 13

2 1

14 21 DMC20261DMC24227DMC24138DMC32132DMC32239DMC40131DMC40218

DMC1610ADMC1606CDMC16117DMC16128DMC16129DMC1616433DMC20434

DMC16106BDMC16207DMC16230DMC20215DMC32216



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ACALL DELAY ; To tr cho LCDMOV A, # N ; Hin th ch NACALL DATAWRT ; Gi ch-ng trnh con hin thij DISPLAYACALL DELAY ; To tr cho LCDMOV AM # 0 ; Hin th ch 0ACALL DATAWRT ; Gi DISPLAY

AGAIN: SJMP AGAIN ; Ch y

COMNWRT: ; Gi lnh n LCDMOV P1, A ; Sao chp thanh ghi A n cng P1CLR P2.0 ; t RS = 0 gi lnhCLR P2.1 ; t R/W = 0 ghi d liuSETB P2.2 ; t E = 1 choxung caoCLR P2.2 ; t E = 0 choxung caoxung thpRET

DATAWRT: ; Ghi d liu ra LCDMOV P1, A ; Sao chp thanh ghi A n cng P1SETB P2.0 ; t RS = 1 gi d liuCLR P2.1 ; t R/W = 0 ghiSETB P2.2 ; t E = 1 choxung cao

CLR P2.2 ; t E = 0 choxung caoxung thpRETDELAY: MOV R3, # 50 ; t tr 50ms hoc cao hn cho CPUnhanhHERE2: MOV R4, # 255 ; t R4 = 255HERE: DJNZ R4, HERE ; i y cho n khi R4 = 0

DJNZ R3, HERE2RETEND

Hnh 12.2:Ni ghp LCD.12.1.4 Gi m lnh hoc d liu n LCD c kim tra c bn.on ch-ng trnh trn y ch ra cch gi cc lnh n LCD m khng c

kim tra c bn (Busy Flag). L-u rng chng ta phi t mt tr ln trong qutnhxut d liu hoc lnh ra LCD. Tuy nhin, mt cch tt hn nhiu l hin th c bn tr-c khi xut mt lnh hoc d liu ti LCD. D-i y l mt ch-ng trnh nh- vy.; Kim tra c bn tr-c khi gi d liu, lnh ra LCD; t P1 l cng d liu

P2.1

D0

P1.0

P1.0

P2.2

D7R /W ERS VSS

VEE

VCC+5v

10KP OT

LCD8051



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; t P2.0 ni ti cng RS; t P2.1 ni ti chn R/W; t P2.2 ni ti chn E

ORGMOV A, # 38H ; Khi to LCD hai dng vi ma trn 5 7ACALL COMMAND ; Xut lnhMOV A, # 0EH ; Dch con tr sang phiACALL COMMAND ; Xut lnhMOV A, # 01H ; Xo lnh LCDACALL COMMAND ; Xut lnhMOV A, # 86H ; Dch con tr sang phiACALL COMMAND ; -a con tr v dng 1 lnh 6MOV A, # N ; Hin th ch NACALL DATA DISPLAYMOV A, # 0 ; Hin th ch 0ACALL DATA DISPLAY

HERE: SJMP HERE ; Ch yCOMMAND: ACALL READY ; LCD s n sng ch-a?

MOV P1, A ; Xut m lnh

CLR P2.0 ; t RS = 0 choxut lnhCLR P2.1 ; t R/W = 0 ghi d liu ti LCDSETB P2.2 ; t E = 1 i vixung caoxung thpCLR P2.2 ; t E = 0 cht d liuRET

DATA DISPLAY::ACALL READY ; LCD s n sng ch-a? MOV P1, A ; Xut d liuSETB P2.0 ; t RS = 1 choxut d liuCLR P2.1 ; t R/W = 0 ghi d liu ra LCDSETB P2.2 ; t E = 1 i vixung caoxung thpCLR P2.2 ; t E = 0 cht d liu

RETDELAY:SETB P1.7 ; Ly P1.7 lm cng voCLR P2.0 ; t RS = 0 truy cp thanh ghi lnhSETB P2.1 ; t R/W = 1 c thanh ghi lnh

; c thanh ghi lnh v kim tra c lnhBACK: CLR P2.2 ; E = 1 i vixung caoxung thp

SETB P2.2 ; E = 0 choxung caoxung thp? JB P1.7, BACK ; i y cho n khi c bn = 0RETEND

L-u rng trong ch-ng trnh c bn D7 ca thanh ghi lnh. c thanh

ghi lnh ta phi t RS= 0, R /W = 1 vxung cao xung thp cho bt E cpthanh ghi lnh cho chng ta. Sau khi c thanh ghi lnh, nu bt D7 (c bn) mccao th LCD bn v khng c thng tin (lnh) no -cxut n n ch khi no D7= 0 mi c th gi d liu hoc lnh n LCD. L-u trong ph-ng pht ny khngs dng tr thi gian no v ta ang kim tra c bn tr-c khixut lnh hoc d liu ln LCD.12.1.5 Bng d liu ca LCD.

Trong LCD ta c th t d liu vo bt c ch no. d-i y l cc v tr ach v cch chng -c truy cp.



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RS E /W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB00 0 1 A A A A A A A

Khi AAAAAAA = 0000000 n 0100111 cho dng lnh 1 v AAAAAAA= 1100111 cho dng lnh2.Xem bng 12.3.

Bng 12.3: nh a ch cho LCD.DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Dng 1 (min) 1 0 0 0 0 0 0 0Dng 1 (max) 1 0 1 0 0 1 1 1Dng 2 (min) 1 1 0 0 0 0 0 0Dng 2 (max) 1 1 1 0 0 1 1 1

Di a ch cao c th l 0100111 cho LCD. 40 k t trong khi i vi CLD20 k t ch n 010011 (19 thp phn= 10011 nh phn). rng di trn

0100111 (nh phn)= 39 thp phn ng vi v tr 0 n 39 cho LCD kch th-c 40 2.T nhng iu ni trn y ta c th nhn -c cc a ch ca v tr con tr

c cc kch th-c LCD khc nhau. Xem hnh 12.3 ch rng tt c mi a ch u dng s Hex. H nh 12.4 cho mt biu ca vic phn thi gian ca LCD.Bng12.4 l danh sch lit k chi tit cc lnh v ch lnh ca LCD.Bng 12.2 -c m rng t bng ny.

16 2 LCD 80C0

81C0

82C2

83C3

84C4

85C5

86C6

ThroughThrough

8F CF

20 1 LCD 80 81 82 83 Through 93

20 2 LCD 80C0 81C0 82C2 83C3 Through 93Through D320 4 LCD 80

C094D4

81C095D5

82C296D6

83C397D7

Through 93Through D3Through A7Through E7

20 2 LCD 80C0

81C0

82C2

83C3

Through A7Through E7

Note: All data is in hex.

Hnh 12.3:Cc a ch con tr i vi mt s LCD.



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Hnh 12.4:Phn khe thi gian ca LCD.Bng 12.4: Danh sch lit k cc lnh v a ch lnh ca LCD.

Lnh

R S

R / W

D B 7

D B 6

D B 5

D B 4

D B 3

D B 2

D B 1

D B 0

M t Thi gianthc hin

Xomnhnh

0 0 0 0 0 0 0 0 0 1 Xo tonb mn hnh v t ach 0 ca DD RAM vob ma ch

1.64ms

Tr vudng

0 0 0 0 0 0 0 0 1 t a ch 0 ca DD RAM nh- bm a ch . Tr hin th dch v vtr gc DD RAM khng thay i

1.64ms

t ch truynhp

0 0 0 0 0 0 0 1 1/D

S t h-ng chuyn dch con tr vx c nh dch hin th cc thao tcny -c th c hin khi c v ghid liu

40ms

iukhin

Bt/tthin th

0 0 0 0 0 0 1 D C B t Bt/ tt mn hnh(D) Bt/ ttcon tr(C) v nhp nhy kt v

tr con tr(B)

40ms

Dchhin thv contr

0 0 0 0 0 1 S/C

R/L

Dch con tr v dch hin th mkhng thay i DD RAM

40ms

tch cn ng

0 0 0 0 1 DL

N F Thit lp di d liu(DL) s dng hin th(L) v phng k t (F)

40ms

tPwh = Enable pulse width = 450 ns(minimum) tDSW= Data set up time = 195 ns(minimum) tH= Data hold time 10 ns(minimum) tAS= Set up time prior to E(going high) f or both RS and R/W = 140 ns(minimum) tAH= Hold time af terr E has come down f or both RS and R/W = 10 ns(minimum)

Data

tDSW tPWH

tHtAHW/R

E

RS

tAS



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t ach CGRAM

0 0 0 1 AGC Thit lp a ch C6 RAM d liuCG RAM -c gi i v nhn sauthit lp ny

40ms

Thitlp ach DDRAM

0 0 1 ADD Thit lp a ch DD RAM d liuDD RAM -c gi v nhn sauthit lp ny

40ms

C bnc va ch

0 1 BF ADD C bn c(BF) b o hot ngbn trong ang -c th c hin vc ni dungb m a ch

40ms

Ghi d liu CGhocDDRAM

1 0 Ghi d liu Ghi d liu vo DD RAM hoc CGRAM

40ms

c d liu CGhocDDRAM

1 1 c d liu c d liu t DD RAM hoc CGRAM

40ms

Ghi ch:

1. Thi gian thc l thi gian cc i khi tn s f CP hocf osc l 250KHz 2. Thi gian thc thay i khi tn s thay i. Khi tn s f EP hay f osc L 270kHz th

thi gian thc hin -c tnh 250 / 270 40 = 35ms v.v 3. Cc k hiu vit tt trong bng l:4.

DD RAM RAM d liu hin th(Display Data RAM) CG RAM RAM my pht kt (character Generator ) ACC a ch a ca RAM my pht kt ADD a ch ca RAM d liu hin th ph hp vi a ch con tr.AC B m a ch (Addr ess Counter ) -c d ng cho cc a ch DD RAM v CGRAM.1/D = 1 Tng 1/D = 0 GimS = 1 Km dch hin thS/C = 1 Dch hin th S/C = 0 Dch con trR/L = 1 Dch sang phi R/L = 0 Dch triDL = 1 8b t DL = 0 4b tN = 1 2 dng N = 1 1 dngF= 1 Ma trn im 5 10 F= 0 Ma trn im 5 7BF= 1 Bn BF= 0 C th nhn lnh

12.2 Phi ghp 8051 vi ADC v cc cm bin.Phn ny s khm ph ghp cc chp ADC (b chuyn i t-ng t s) v cc

cm bin nhit vi 8051.12.1.1 Cc thit b ADC.

Cc b chuyn i ADC thuc trong nhng thit b -c s dng rng rinht thu d liu. Cc my tnh s s dng cc gi tr nh phn, nh-ng trong th gii vt l th mi i l-ng dng t-ng t (lin tc). Nhit , p sut (kh hoc



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cht lng), m v vn tc v mt s t trng nhng i l-ng vt l ca th giithc m ta gp hng ngy.Mt i l-ng vt l -c chuyn v dng in hoc inp qua mt thit b -c gi l cc b bin i. Cc b bin i cng c th -c coinh- cc b cm bin. Mc d ch c cc b cm bin nhit, tc , p sut, nh sngv nhiu i l-ng t nhin khc nh-ng chng u cho ra cc tn hiu dng dngin hoc in p dng lin tc. Do vy, ta cn mt b chuyn i t-ng t s sao

cho b vi iu khin c th c -c chng.Mt chp ADC -c s dng rng ri lADC 804.12.2.2 Chp ADC 804.

Chp ADC 804 l b chuyn i t-ng t s trong h cc lot ADC 800 t hng National Semiconductor. N cng -c nhiu hng khc sn xut, n lm vicvi +5v v c phn gii l 8 bt. Ngoi phn gii th thi gian chuyn i cngl mt yu t quan trng khc khi nh gi mt b ADC. Thi gian chuyn i -cnh ngh a nh- l thi gian m b ADC cn chuyn mt u vo t-ng t thnhmt s nh phn. Trong ADC 804 thi gian chuyn i thay i ph thuc vo tn s ng h -c cp ti chn CLK v CLKIN nh-ng khng th nhanh hn 110ms. Ccchn ca ADC 804 -c m t nh- sau:1. ChnCS chn chp: L mt u vo tch cc mc thp -c s dng kch

hot chp ADC 804. truy cp ADC 804 th chn ny phi mc thp.2. Chn RD (c): y l mt tn hiu u vo -c tch cc mc thp. Cc b

ADC chuyn i u vo t-ng t thnh s nh phn t-ng -ng vi n v gi n trong mt thanh ghi trong. RD -c s dng nhn d liu -c chuyn i u ra ca ADC 804. Khi CS= 0 nu mtxung cao xung thp -c p nchnRD th u ra s 8 bt -c hin din cc chn d liu D0 D7. ChnRD cng -c coi nh- cho php u ra.

3. Chn ghiWR (thc ra tn chnhxc l Bt u chuyn i). y l chn u

vo tch cc mc thp -c dng bo cho ADC 804 bt u qu trnh chuyni. Nu CS= 0 khi WR to ra xung cao xung thp th b ADC 804 bt uchuyn i gi tr u vo t-ng t Vin v s nh phn 8 bt. L-ng thi gian cnthit chuyn i thay i ph thuc vo tn s -a n chn CLKIN v CLKR. Khi vic chuyn i d liu -c hon tt th chnINTR -c pxung thpb i ADC 804.

4. Chn CLKIN v CLK R.Chn CLKIN l mt chn u vo -c ni ti mt ngun ng h ngoi khi

ng h ngoi -c s dng to ra thi gian. Tuy nhin 804 cng c mt my toxung ng h. s dng my toxung ng h trong (cng cn -c gi l myto ng h ring) ca 804 th cc chn CLKIN v CLK R -c ni ti mt t inv mt in tr nh- ch ra trn hnh 12.5. Trong tr-ng hp ny tn s ng h -cxc nh bng biu thc:

RC1,11

f =

g i tr tiu biu ca cc i l-ng trn l R = 10kW v C= 150pF v tn s nhn -c lf = 606kHz v thi gian chuyn i s mt l 110ms.



10/17

Hnh 12.5:Kim tra ADC 804 ch chy t do.5. Chn ngt INTR (ngt hay gi chnhxc hn lkt thc chuyn i).

y l chn u ra tch cc mc thp.B nh th-ng n trng thi cao v khivic chuyn i hon tt th nxung thp bo cho CPU bit l d liu -cchuyn i s n sng ly i. Sau khiINTR xung thp, ta t CS= 0 v gi mtxung cao 0 xung thp ti chnRD ly d liu ra ca 804.6. Chn V in (+) v V in ( ).

y l cc u vo t-ng t vi sai m Vin = Vin (+) Vin ( ). Thng th-ng Vin ( ) -c ni xung t v Vin (+) -c dng nh- u vo t-ng t -c chuyn iv dng s.7. Chn V CC.

y l chn ngun nui+5v, n cng -c dng nhin p tham chiu khiu vo Vref/ 2 (chn9) h .8. Chn V ref/ 2.

Chn9 l mt in p u vo -c dng cho in p tham chiu. Nu chnny h (khng -c ni) th in p u vo t-ng t cho ADC 804 nm trong di 0

n+

5v (ging nh- chn VCC). Tuy nhin, c nhiu ng dng m u vo t-ng t p n Vin cn phi khc ngoi di 0 n 5v. Chn Vref/ 2 -cdng thc thi ccin p u vo khc ngoi di 0 5v. V d, nu di u vo t-ng t cn phi l 0n 4v th Vref/ 2 -c ni vi +2v.

Bng 12.5 biu din di in p Vin i vi cc u vo Vref/ 2 khc nhau.Bng 12.5: in p Vref/ 2 lin h vi di Vin.

ADC0804

+5V

1

11

4

12

10

9

19

10k150pF 11

12131415161718

35

toLEDs

NomallyOpen

START

D0D1D2D3D4D5D6D7

WRINTRD GND

RDCS

CLK in

CLK R

A GNDVr ef /2

Vin( ) Vin(+)

20

Vcc

10k

POT



11/17

Vref / 2(V) Vin(V) Step Size (mV)H * 0 n 5 5 / 256 = 19.532.0 0 n 4 4 / 255 = 15.621.5 0 n 3 3 / 256 = 11.711.28 0 n 2.56 2.56/ 256 = 101.0 0 n 2 2 / 256 = 7.810.5 0 n 1 1 / 256 = 3.90

Ghi ch: VCC = 5V* Khi Vref / 2 h th o -c khong 2,5V Kch th-c b-c ( phn di) l s thay i nh nht m ADC c th

phn bit -c.9. Cc chn d liu D0 D7.

Cc chn d liu D0 D7 (D7 l bt cao nhtMSB v D0 l bt thp nht LSB)l cc chn u ra d liu s. y l nhng chn -c m ba trng thi v d liu-c chuyn i ch -c truy cp khi chn CS= 0 v chnRD b -axung thp.

tnh in p u ra ta c th s dng cng thc sau:

buocthuockichV

D inout =

Vi D out l u ra d liu s (dng thp phn). Vin l in p u vo t-ng t v phn di l s thay i nh nht -c tnh nh- l (2 Vref / 2) chia cho 256 ivi ADC 8 bt.10. Chn t t-ng t v chn t s.

y l nhng chn u vo cp t chung cho c tn hiu s v t-ng t. tt-ng t -c ni ti t ca chn Vin t-ng t, cn t s -c ni ti t ca chnVcc. L do m ta phi c hai t l cch ly tn hiu t-ng t Vin t cc in p k

sinh to ra vic chuyn mch s -c chnhxc. Trong phn trnh by ca chng tath cc chn ny -c ni chung vi mt t. Tuy nhin, trong thc t thu o d liucc chn t ny -c ni tch bit.

T nhng iu trn ta kt lun rng cc b-c cn phi thc hin khi chuyni d liu b i ADC 804 l:a) Bt CS= 0 v gi mtxung thp ln cao ti chn WR bt u chuyn i.b) Duy tr hin th chnINTR . NuINTR xung thp th vic chuyn i -c hon

tt v ta c th sang b-c k tip. NuINTR cao tip tc thm d cho n khi nxung thp.

c) Sau khi chnINTR xung thp, ta bt CS= 0 v gi mtxung cao xung thp

n chnRD ly d liu ra khi chp ADC 804. Phn chia thi gian cho qutrnh ny -c trnh by trn hnh 12.6.



12/17

Hnh 12.6:Phn chia thi gian c v ghi ca ADC 804.12.2.3 Kim tra ADC 804.

Chng ta c th kim tra ADC 804 bng cch s dng s mch trn hnh12.7. thit lp ny -c gi l ch kim tra chy t do v -c nh snxutkhuyn cao nn s dng.H nh 12.5 trnh by mt bin tr -c dng cp mtin p t-ng t t 0 n 5V ti chn u vo.

Vin(+) ca ADC 804 cc u ra nh phn -c hin th trn cc n LED cabng hun luyn s. Cn phi l-u rng trong ch kim tra chy t do th u voCS -c ni ti t v u voWR -c ni ti u ra INTR . Tuy nhin, theo tiliu ca hng National Semiconductornt WR v INTR phi -c tm thi -axung thp k sau chu trnh cp ngun bo m hot ng.

Hnh 12.7:Ni ghp ADC 804 vi ngun ng h ring.

CS

D0 D7 Data out

Read it

End conversionStart conversion

WR

INTR

RD

8051 ADC804P2.5P2.6P1.0

P1.7P2.7

D0

D7INTR

GND

A GNDVr ef /2

CLK INCLK R

VCC

Vin(+) Vin( )

150pF

5V

10k

10kPOT

RD

WR

CS



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V d 12.7:Hy th ni ghp ADC 804 vi 8051 theo s 12.7. Vit mt ch-ng trnh

hin th chnINTR v ly u vo t-ng t vo thanh ghi A. Sau gi mtch-ng trnh chuyn i m Hex ra ASCII v mt ch-ng trnh hin th d liu.Thc hin iu ny lin tc.Li gii:

; t P2.6 = WR(bt u chuyn i cn 1xung thp ln cao) ; t chn P2.7 = 0 khi kt thc chuyn i; t P2.5 = RD(xung cao xung thp s c d liu t ADC) ; P1.0 P1.7 ca ADC 804

MOV P1, # 0FFH ; Chn P1 l cng u voBACK: CLR P2.6 ; t WR = 0

SETB P2.6 ; t WR = 1 bt u chuyn iHERE: JB P2.7, HERE ; Ch cho P2.7 to kt thc chuyn i

CLR P2.5 ; Kt thc chuyn i, cho php c RDMOV A, P1 ; c d liu vo thanh ghi AACALL CONVERSION ; Chuyn i s Hexra m ASCII

ACALL DATA DISPLAY ; Hin th d liuSETB P2.5 ; -a RD = 1 cho ln c sau.SJMP BACK

Hnh 12.8:Ni ghp ADC 804 vi ng h t XTAL2 ca 8051.Trn hnh 12.8 ta c th thy rng tn hiu ng h i vo ADC 804 l t tn

s thch anh ca 8051. V tn s ny qu cao nn ta s dng hai mch lt Rlip Flopkiu D (74LS74) chia tn s ny cho 4.Mt mch lt chia tn s cho 2 nu ta niuQ ti u vo D. i vi tn s cao hn th ta cn s dng nhiu mchFlip Plop hn.12.2.4 Phi ghp vi mt cm bin nhit ca 8051.

8051 ADC804P2.5P2.6P1.0

P1.7P2.7

D0

D0INTR

GND

A GNDVr ef /2

CLK INCLK R

VCC

Vin(+) Vin( )

5V

10kPOT

RD

WR

CSD Q

Q

D Q

Q

74LS74



14/17

Cc b bin i (Transducer) chuyn i cc i l-ng vt l v d nh- nhit, c-ng nh sng, l-u tc v tc thnh cc tn hiu in ph thuc vo bbin i m u ra c th l tn hiu dng in p, dng, tr khng hay dung khng.V d, nhit -c bin i thnh v cc tn hiu in s dng mt b bin i gil Rhermistor (b cm bin nhit), mt b cm bin nhit p ng s thay i nhit bng cch thay i tr khng nh-ng p ng ca n khng tuyn tnh (xem bng

12.6). Bng 12.6: Tr khng ca b cm bin nhit theo nhit .

Nhit (0C) Tr khng ca cm bin (k W )0 29.49025 10.00050 3.89375 1.700100 0.817

Bng 12.7: H-ng d n chn lot cc cm bin h LM34.M k hiu Di nhit chnh xc u raLM34A 55F to + 300 C + 2.0 F 10mV /F LM34 55F to + 300 C + 3.0 F 10mV /F LM34CA 40F to + 230 C + 2.0 F 10mV /F LM34C 40F to + 230 C + 3.0 F 10mV /F LM34D 32F to + 212 C + 4.0 F 10mV /F

Bng 12.8: H-ng d n chn lot cc cm bin nhit h LM35.

M sn phm Di nhit chnh xc u raLM35A 55 C to+ 150 C + 1.0 C 10 mV /F LM35 55 C to+ 150 C + 1.5 C 10 mV /F LM35CA 40 C to+ 110 C + 1.0 C 10 mV /F LM35C 40 C to+ 110 C + 1.5 C 10 mV /F LM35D 0 C to+ 100 C + 2.0 C 10 mV /F

Tnh cht gn lin vi vic vit phn mm cho cc thit b phi tuyn nh- vy -a nhiu nh snxut tung ra th tr-ng cc lot b cm bin nhit tuyn tnh.Cc b cm bin nhit n gin v -c s dng rng ri bao gm cc lot h LM34v LM35 ca hng National Semiconductor Corp.12.2.5 Cc b cm bin nhit h LM34 v LM35.

Lot cc b cm bin LM34 l cc b cm bin nhit mch tch hp chnhxc cao m in p u ra ca n t l tuyn tnh v nhit Fahrenheit (xem hnh12.7). lot LM34 khng yu cu cn chnh bn ngoi v vn n -c cn chnhri. N -a ra in p 10mV cho s thay i nhit 10F. bng 12.7 h-ng d n tachn cc cm bin lot LM34.



15/17

Lot cc b cm bin LM35 cng l cc b cm bin nhit mch tch hpchnhxc cao m in p u ra ca n t l tuyn tnh vi nhit theo thang Celsius. Chng cng khng yu cu cn chnh ngoi v vn chng -c cnchnh. Chng -a ra in p 10Mv cho mi s thay i 10C. Bng 12.8 h-ng d n tachn cc cm bin h LM35.12.2.6 Phi hp tn hiu v phi ghp LM35 vi 8051.

Phi hp tn hiu l mt thut ng -c s dng rng ri trong l nh vc thu od liu.Hu ht cc b bin i u -a ra cc tn hiu in dng in p, dngin, dung khng hoc tr khng. Tuy nhin, chng ta cn chuyn i cc tn hiuny v in p nhm gi u vo n b chuyn i ADC. S chuyn i (bin i)ny -c gi chung l phi hp tn hiu. Phi hp tn hiu c th l vic chuyn idng in thnh in p hoc s khuych i tn hiu. V d, b cm bin nhit thai tr khng vi nhit . S thay i tr khng phi -c chuyn thnh in p c th -c s dng cho cc ADC.Xt tr-ng hp ni mt LM35 ti mt ADC 804v ADC 804 c phn di 8 bt vi ti a 256 b-c (2 8) v LM35 (hocML34) toin p 10mV cho mi s thay i nhit 10C nn ta c th to iu kin Vin caADC 804 to ra mt Vout = 2560mV (2,56V) cho u ra u thang o. do vy, nhmto ra Vout y thang 2,56V cho ADC 804 ta cn t in p Vref / 2 = 1,28V. iu nylm cho Vout ca ADC 804 p ng trc tip vi nhit -c hin th trn LM35(xem bng 12.9). Cc gi tr ca Vref / 2 -c cho bng 12.5.

Bng 12.9: Nhit .

Nhit (0C) Vin (mV) Vout (D7 D0)0 0 0000 00001 10 0000 00012 20 0000 00103 30 0000 0011

10 100 0000 101030 300 0001 1110

Cc i l-ng vt l(nhit , p sut, l-u tc v.v)

B bin i

Phi hp tn hiu

ADC

B vi iu khin



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Hnh 12.9:Thu o cc i l-ng vt l.

H nh 12.10

Hnh 12.10:Ni ghp 8051 vi DAC 804 v cm bin nhit .H nh 12.10 biu din ni ghp ca b cm bin nhit n ADC 804. L-u

rng ta s dng i tzener LM336 2.5 c nh in p qua bin tr 10kW ti2,5V. Vic s dng LM336 2.5 c th v-t qua -c mi dao ng lnxung cangun nui.12.2.7 Chp ADC 808/809 vi 8 knh t-ng t.

Mt chp hu ch khc ca National Semiconductor l ADC 808 / 809 (xemhnh 12.11). Trong khi ADC 804 ch c mt u vo t-ng t th chp ny c 8 knhu vo. Nh- vy n cho php ta hin th ln 8 b bin i khc nhau ch qua mtchp duy nht. L-u rng, ADC 808 / 809 c u ra d liu 8 bt nh- ADC 804. 8knh u vo t-ng t -c dn knh v -c chn theo bng 12.10 s dng ba chna ch A,B v C.

(LSB)

GND Clock Vcc

ADC808/809Vr ef(+) Vr ef()

CCASC ALEOE

EOCD7

D0IN0

IN7

8051 ADC804P2.5P2.6

P1.0

P1.7P2.7

D0

D7INTR

GND

A GNDVr ef /2

CLK INCLK R

VCC

Vin(+) Vin( )

5V

RD

WR

CSD Q

Q

D Q

Q

Set to1.28V

GND

LM35 or LM34

L M

3 3 6

2.5k

10k



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Hnh 12.11: B bin i ADC 808 / 809.Bng 12.10: Chn knh t-ng t ca ADC 808.

Chn knh t-ng t C B AIN0 0 0 0IN1 0 0 1IN2 0 1 0IN3 0 1 1IN4 1 0 0IN5 1 0 1IN6 1 1 0IN7 1 1 1

Trong ADC 808 / 809 th Vrer(+) v Vref ( ) thit lp in p tham chiu. NuVref ( 1)= Gnd v Vref (+) = 5V th phn di l 5V / 256 = 19,53mV. Do vy, c phn di 10mV ta cn t Vref (+) = 2,56V v Vref ( )= Gnd. T hnh 12.11 ta thy

c chn ALE. Ta s dng cc a ch A,B v C chn knh u voIN0 IN7 vkch hot chn ALE cht a ch. Chn SetComplete bt u chuyn i (StartConversion). Chn EOC -c dng kt thc chuyn i (End Of Conversion)v chnOE l cho php c u ra (Out put Enable).12.2.7 Cc b-c lp trnh cho ADC 808/809.

Cc b-c chuyn d liu t u vo ca ADC 808 / 809 vo b vi iu khinnh- sau:1. Chn mt knh t-ng t bng cch to a ch A,B v C theo bng 12.10.2. Kch hot chn ALE (cho php cht a ch Address Latch Enable). N cnxung

thp ln cao cht a ch.3. Kch hot chn SCbngxung cao xung thp bt u chuyn i.4. Hin thOEC bo kt thc chuyn i. u ra cao xung thp bo rng d

liu -c chuyn i v cn phi -c ly i.5. Kch hotOE cho php c d liu ra ca ADC.Mt xung cao xung thp ti

chnOE s em d liu s ra khi chp ADC.L-u rng trong ADC 808 / 809 khng c ng h ring v do vy phi cp

xung ng b ngoi n chn CLK.Mc d tc chuyn i ph thuc vo tn s ng h -c ni n CLK nh-ng n khng nhanh hn 100ms.


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Chuong 12_LCD - ADC - Cam Bien - Smith.N Studio