CMOS_DataBook

8/2/2019 CMOS_DataBook

1/407


2/407

HighSpeed CM

Re


3/407

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves thewithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its ppurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclincluding without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, inclvalidated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rightSCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the bointended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation wdeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and exattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorize

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4/407

Table of Contents

Chapter 1. Function Selector Guide

Alphanumeric Index 6. . . . . . . . . . . . . . . . . . . . . . . . .

Buffers/Inverters 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Schmitt Triggers 12. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Transceivers 12. . . . . . . . . . . . . . . . . . . . . . . . . . .

Latches 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FlipFlops 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Data Selectors/Multiplexers 16. . . . . . . . . . . . .

Decoders/Demultiplexers/Display Drivers 17. . . . . . .

Analog Switches/Multiplexers/Demultiplexers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Shift Registers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counters 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Miscellaneous 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2. Design Considerations

Introduction 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Handling Precautions 24. . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sizing 28. . . . . . . . . . . . . . . . . . . . . . . . .

Battery Systems 28. . . . . . . . . . . . . . . . . . . . . . . . . .CPD Power Calculation 29. . . . . . . . . . . . . . . . . . .

Inputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Outputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3State Outputs 35. . . . . . . . . . . . . . . . . . . . . . . . . .

OpenDrain Outputs 35. . . . . . . . . . . . . . . . . . . . . .

Input/Output Pins 35. . . . . . . . . . . . . . . . . . . . . . . . .Bus Termination 36. . . . . . . . . . . . . . . . . . . . . . . . . .

Transmission Line Termination 37. . . . . . . . . . . . .

CMOS Latch Up 38. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Power Dissipation 40. . . . . . . . . . . . . . . . . .HC Quiescent Power Dissipation 40. . . . . . . . . . .HCT Quiescent Power Dissipation 40. . . . . . . . . .

HC and HCT Dynamic Power Dissipation 40. . . .

Thermal Management . . . . . . .

Capacitive Loading Effects onPropagation Delay . . . . . . . . . .Temperature Effects on DC andParameters . . . . . . . . . . . . . . . .Supply Voltage Effects on Driveand Propagation Delay . . . . . . .Decoupling Capacitors . . . . . . .Interfacing . . . . . . . . . . . . . . . . .Typical Parametric Values . . . .Reduction of Electromagnetic

Interference (EMI) . . . . . . . . . . .Hybrid Circuit Guidelines . . . . .SchmittTrigger Devices . . . . .Oscillator Design with HighSp

RC Oscillators . . . . . . . . . . .Crystal Oscillators . . . . . . . .

Printed Circuit Board Layout . .Definitions and Glossary of T

HC vs. HCT . . . . . . . . . . . . .Glossary of Terms . . . . . . . .

Applications Assistance Form

Chapter 3. Device Datashe. . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4. Application No. . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5. Ordering InformDevice Nomenclature . . . . . . . .

Case Outlines . . . . . . . . . . . . .ON Semiconductor Major WorldSales Offices . . . . . . . . . . . . . . .Document Definitions . . . . . . . .


5/407


6/407

CH

Function Selec

Alphanumeric Index . . . . . . . .

Buffers/Inverters . . . . . . . . . .Gates . . . . . . . . . . . . . . . . . . .Schmitt Triggers . . . . . . . . . .Bus Transceivers . . . . . . . . .

Latches . . . . . . . . . . . . . . . . .FlipFlops . . . . . . . . . . . . . . .Digital Data Selectors/MultipDecoders/Demultiplexers/DiAnalog Switches/MultiplexerDemultiplexers . . . . . . . . . . .Shift Registers . . . . . . . . . . .Counters . . . . . . . . . . . . . . . .Miscellaneous . . . . . . . . . . . .


7/407

ALPHANUMERIC INDEX

Device Number Function

MC74HC00A Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC02A Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC03A Quad 2Input NAND Gate With OpenDrain Outputs . . . . . . . . . . . . . . . . . . . . .

MC74HC04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCT04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCU04A Hex Unbuffered Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC08A Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCT14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC74HC32A Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC74A Dual D FlipFlop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCT74A Dual D FlipFlop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC86A Quad 2Input Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC125A Quad With 3State Outputs NonInverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC126A Quad With 3State Outputs NonInverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC132A Quad 2Input NAND Gate With Schmitt Trigger Inputs . . . . . . . . . . . . . . . . . . . .

MC74HC138A 1of8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCT138A 1of8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC74HC139A Dual 1of4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC157A Quad 2Input Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC161A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC163A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC164A 8Bit SerialInput/ParallelOutput Shift Register . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC165A 8Bit Serial or ParallelInput/SerialOutput Shift Register . . . . . . . . . . . . . . . . . .

MC74HC174A Hex D FlipFlop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC175A Quad D FlipFlop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC240A Octal With 3State Outputs Inverting Buffer/Line Driver/line Receiver . . . . . . . . MC74HC244A Octal With 3State Outputs NonInverting Buffer/Line Driver/Line Receiver . .

MC74HCT244A Octal With 3State Outputs NonInverting Buffer/Line Driver/Line Receiver . .

MC74HC245A Octal With 3State Outputs NonInverting Bus Transceiver . . . . . . . . . . . . . . . .

MC74HCT245A Octal With 3State Outputs NonInverting Bus Transceiver . . . . . . . . . . . . . . . .

MC74HC273A Octal D FlipFlop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HCT273A Octal D FlipFlop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC373A Octal With 3State Outputs NonInverting Transparent Latch . . . . . . . . . . . . . .

MC74HCT373A Octal With 3State Outputs NonInverting Transparent Latch . . . . . . . . . . . . . .

MC74HC374A Octal With 3State Outputs NonInverting D FlipFlop . . . . . . . . . . . . . . . . . . . . MC74HCT374A Octal With 3State Outputs NonInverting D FlipFlop . . . . . . . . . . . . . . . . . . . .

MC74HC390A Dual 4Stage Binary Ripple Counter W 2, 5 Sections . . . . . . . . . . . . . . . . . . .

MC74HC393A Dual 4Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC540A Octal With 3State Outputs Inverting Buffer/Line Driver/Line Receiver . . . . . . .

MC74HC541A Octal With 3State Outputs NonInverting Buffer/Line Driver/Line Receiver . .

MC74HCT541A Octal With 3 State Outputs Non Inverting Buffer/Line Driver/Line Receiver


8/407

ALPHANUMERIC INDEX

Device Number Function

MC74HC4051A 8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4052A Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4053A Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4060A 14Stage Binary Ripple Counter With Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4066A Quad Analog Switch/Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4316A Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/

Digital Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC74HC4538A Dual Precision Monostable Multivibrator Retriggerable, Resettable) . . . . . . . . .

MC74HC4851A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . . MC74HC4852A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . .


9/407

BUFFERS/INVERTERS

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC04A

HCT04A

HCU04A

HC14A

HCT14A

Hex Inverter

Hex Inverter with LSTTLCompatible Inputs

Hex Unbuffered Inverter

Hex SchmittTrigger Inverter

Hex SchmittTrigger Inverter with LSTTLCompatible

Inputs

LS04

LS04

LS04

LS14

LS14

*4069

*4069

4069

4584

4584

L

L

L

L

L

HC125A

HC126A

HC240A

Quad 3State Noninverting Buffer

Quad 3State Noninverting Buffer

Octal 3State Inverting Buffer/Line Driver/Line Receiver

LS125,LS125A

LS126,LS126A

LS240

HC244A

HCT244A

HC245A

HCT245A

Octal 3State Noninverting Buffer/Line Driver/Line

Receiver


Receiver with LSTTLCompatible Inputs

Octal 3State Noninverting Bus Transceiver

Octal 3State Noninverting Bus Transceiver with

LSTTLCompatible Inputs

LS244

LS244

LS245

LS245

HC540A

Octal 3State Inverting Buffer/Line Driver/Line Receiver

HC541A

HCT541A


Receiver


Receiver with LSTTLCompatible Inputs

LS541

LS541

HC Devices Have CMOSCompatible Inputs. HCT Devices Have LSTTLCompatible Inputs.

Device

HC

HCT

04A

HCU

04A

HC

14A

HC

125A

HC

126A

HC

240

# Pins

14

14

14

14

14

20

Quad Device

Hex Device

Octal Device

NineWide Device

D

D

D

D

D

D

Noninverting OutputsInverting Outputs

D

D

D

D

D

D

Single Stage (unbuffered)

D

Schmitt Trigger

D

3State Outputs

OpenDrain Outputs

D

D

D


10/407

BUFFERS/INVERTERS (Continued)


Device

# Pins

Quad Device

Hex Device

Octal Device

NineWide Device

Noninverting Outputs

Inverting Outputs

Single Stage (unbuffered)

Schmitt Trigger

3State Outputs

OpenDrain Outputs

Common Output Enables

ActiveLow Output Enables


11/407

GATES

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC00A

HC02A

HC03A

HC08A

HC32A

HC86AHC132A

Quad 2Input NAND Gate

Quad 2Input NOR Gate

Quad 2Input NAND Gate with OpenDrain Outputs

Quad 2Input AND Gate

Quad 2Input OR Gate

Quad 2Input Exclusive OR GateQuad 2Input NAND Gate with SchmittTrigger Inputs

LS00

LS08

LS32

LS86LS132

4011

4001

*4011

4081

4071

40704093

HC Devices Have CMOSCompatible Inputs.

Device

HC

00A

HC

02A

HC

03A

# Pins

14

14

14

Single Device

Dual Device

Triple Device

Quad Device

D

D

D

NAND

NOR

AND

OR

D

D

D

Exclusive OR

Exclusive NOR

ANDNOR

ANDOR

2Input

3Input

4Input

8Input

13Input

D

D

D

SchmittTrigger Inputs

OpenDrain Outputs

D


12/407

GATES (Continued)


Device

# Pins

Single Device

Dual Device

Triple Device

Quad Device

NAND

NOR

ANDOR

Exclusive OR

Exclusive NOR

ANDNOR

ANDOR

2Input

3Input

4Input

8Input13Input

SchmittTrigger Inputs

OpenDrain Outputs


13/407

SCHMITT TRIGGERS

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC14A

HCT14A

HC132A

Hex SchmittTrigger Inverter

Hex SchmittTrigger Inverter with LSTTLCompatible

Inputs

Quad 2Input NAND Gate with SchmittTrigger Inputs

LS14

LS14

LS132

4584

4584

4093

L

BUS TRANSCEIVERS

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC245A

HCT245A

Octal 3State Noninverting Bus Transceiver

Octal 3State Noninverting Bus Transceiver with


LS245

LS245


Device

# Pins

Quad Device

Octal Device

Buffer

Storage Capability

Inverting Outputs


Common Output EnableActiveLow Output Enable

ActiveHigh Output Enable

Direction Control


14/407

LATCHES

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC373A

HCT373A

Octal 3State Noninverting Transparent Latch

Octal 3State Noninverting Transparent Latch with


LS373

LS373

HC573A

HCT573A

Octal 3State Noninverting Transparent Latch

Octal 3State Noninverting Transparent Latch with


LS373

LS373


Device

# Pins

Single Device

Dual Device

Octal Device

Number of Bits Controlled by Latch Enable:

2

8

Transparent

Addressable

Readback Capability


Inverting Outputs

Common Latch Enable, ActiveLow

3State Outputs

Common Output Enable, ActiveLow

These devices are identical in function and are different in pinout only: HC/HCT373A and HC/HCT573A


15/407

FLIPFLOPS

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC74A

HCT74A

Dual D FlipFlop with Set and Reset

Dual D FlipFlop with Set and Reset with


LS74,LS74A

LS74,LS74A

*4013

4013

HC174A

HC175A

Hex D FlipFlop with Common Clock and Reset

Quad D FlipFlop with Common Clock and Reset

LS174

LS175

4174

4175

L

L

HC273A

HCT273A

HC374A

HCT374A

Octal D FlipFlop with Common Clock and Reset

Octal D FlipFlop with Common Clock and Reset with


Octal 3State Noninverting D FlipFlop

Octal 3State Noninverting D FlipFlop with


LS273

LS273

LS374

LS374

HC574A

HCT574A

Octal 3State Noninverting D FlipFlop

Octal 3State Noninverting D FlipFlop with


LS374

LS374

*Suggested alternative


Device

HC

HCT

74A

# Pins

14

Type

D

Dual DeviceQuad Device

Hex Device

Octal Device

D

Common Clock

NegativeTransition Clocking

PositiveTransition Clocking

D

Common, ActiveLow Data Enables


Inverting Outputs

D

D

3State Outputs

Common, ActiveLow Output Enables

Common Reset

ActiveLow Reset

ActiveHigh Reset

D


16/407

FLIPFLOPS (Continued)


Device

HCHCT

273A

# Pins

20

Type

D

Dual Device

Quad Device

Hex Device

Octal Device

D

Common ClockNegativeTransition Clocking


D

D

Common, ActiveLow Data Enables


Inverting Outputs

D

3State Outputs

Common, ActiveLow Output Enables

Common Reset

ActiveLow ResetActiveHigh Reset

D

D

ActiveLow Set

Transceiver

Direction Control

These devices are identical in function and are different in pinout only: HC374A and HC574A


17/407

DIGITAL DATA SELECTORS/MULTIPLEXE

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC157A

Quad 2Input Noninverting Data Selector/Multiplexer

LS157

HC251

HC253

HC257

8Input Data Selector/Multiplexer with 3State Outputs

Dual 4Input Data Selector/Multiplexer with 3State

Outputs

Quad 2Input Data Selector/Multiplexer with 3State

Outputs

LS251

LS253

LS257B

*4512



Device

# Pins

Description

Single Device

Dual Device

Quad Device

Data Latch with ActiveLowLatch Enable

Common Address

1Bit Binary Address

2Bit Binary Address

3Bit Binary Address

Address Latch (Transparent)

Address Latch(Nontransparent)ActiveLow Address LatchEnable

Noninverting Output

Inverting Output

3State Outputs

Common Output EnableActiveHigh Output Enable

ActiveLow Output Enable


18/407

DECODERS/DEMULTIPLEXERS/DISPLAY DR

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC138A

HCT138A

HC139A

1of8 Decoder/Demultiplexer

1of8 Decoder/Demultiplexer with LSTTLCompatible

Inputs

Dual 1of4 Decoder/Demultiplexer

LS138

LS138

LS139

*4028

*4028

4556

L



Device

HC

HC

138

# Pins

16

Input Description

3Bit B

Addr

Output Description

One

Single Device

Dual Device

D

Address Input Latch

ActiveHigh Latch Enable

ActiveLow Latch Enable

ActiveLow Inputs

ActiveLow Outputs

ActiveHigh Outputs

D

ActiveLow Output EnableActiveHigh Output Enable

D D

D

ActiveLow Reset

ActiveLow Blanking Input

ActiveHigh Blanking Input

ActiveLow LampTest Input

Phase Input (for LCDs)

D DImplies the device has two such enables


19/407

ANALOG SWITCHES/MULTIPLEXERS/DEMULTI

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC4051A

HC4052A

HC4053A

HC4066A

8Channel Analog Multiplexer/Demultiplexer

Dual 4Channel Analog Multiplexer/Demultiplexer

Triple 2Channel Analog Multiplexer/Demultiplexer

Quad Analog Switch/Multiplexer/Demultiplexer

4051

4052

4053

4066,4016

KHC4316/A

KHC4851A

K HC4852A

Quad Analog Switch/Multiplexer/Demultiplexer with

Separate Analog and Digital Power Supplies

Analog Multiplexer/Demultiplexer withInjection Current

Effect Control

Analog Multiplexer/Demultiplexer withInjection Current

Effect Control

*4016

*4051

*4052


KHighSpeed CMOS design only


Device

HC4051A

HC4052A

HC4053A

# Pins

16

16

16

Description

A 3Bit Address

Selects One of 8

Switches

A 2Bit Address

Selects One of 4

Switches

A 3Bit Add

Selects Vary

Combination

the 6 Switch

Single Device

Dual Device

Triple DeviceQuad Device

D

D

D

1to1 Multiplexing

2to1 Multiplexing

4to1 Multiplexing

8to1 Multiplexing

D

D

D

ActiveHigh ON/OFF Control

Common Address Inputs

2Bit Binary Address

3Bit Binary AddressAddress Latch with ActiveLow Latch

Enable

D

D

D

D

D

Common Switch Enable

ActiveLow Enable

ActiveHigh Enable

D

D

D

D

D

D

Separate Analog and Control Reference


20/407

ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS (C


Device

HC

4316A

HC

4851A

# Pins

16

20

Description

4 Independently

ControlledSwitches(Has a Separate

Analog Lower

Power Supply)

A 3Bit Address

Selects One of 8

Switches

(Has Injection Current

Protection)

Single Device

Dual DeviceTriple Device

Quad Device

D

D

1to1 Multiplexing

2to1 Multiplexing

4to1 Multiplexing

8to1 Multiplexing

D

D

ActiveHigh ON/OFF Control

D

Common Address Inputs

2Bit Binary Address3Bit Binary Address

D

Common Switch Enable

ActiveLow Enable

ActiveHigh Enable

D

D

D

D

Separate Analog and Control ReferencePower Supplies

D

D

Switched Tubs (for RON and Prop. DelayImprovement)

njection Current Protection

D


21/407

SHIFT REGISTERS

Device

Number

MC74

Function

Functional

Equivalent

LSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC164A

HC165A

8Bit SerialInput/ParallelOutput Shift Register

8Bit Serial or ParallelInput/SerialOutput Shift Register

LS164

LS165

*4021

HC589A

HC595A

8Bit Serial or ParallelInput/SerialOutput Shift Register

with 3State Output

8Bit SerialInput/Serial or ParallelOutput Shift Register

with Latched 3State Outputs



Device

HC

164A

HC

165A

# Pins

14

16

4Bit Register

8Bit Register

D

D

Serial Data Input

Parallel Data Inputs

D

D

D

Serial Output Only

Parallel Outputs

Inverting Output

Noninverting Output

D

D

D

D

D

Serial Shift/Parallel Load Control

Shifts One Direction Only

Shifts Both Directions

D

D

D


ActiveHigh Clock Enable

D

D

D

Input Data Enable

D

Data Latch with ActiveHigh Latch Clock

Output Latch with ActiveHigh Latch Clock

3State Outputs

ActiveLow Output Enable

ActiveLow Reset

D


22/407

COUNTERS

Device

Number

MC74

Function

Functional

EquivalentLSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

D

Co

HC161A

HC163A

HC390A

Presettable 4Bit Binary Counter with Asynchronous

Reset

Presettable 4Bit Binary Counter with Synchronous Reset

Dual 4Stage Binary Ripple Counter with 2 and 5Sections

LS161,LS161A

LS161,LS161A

HC393AHC4020A

HC4040A

HC4060A

Dual 4Stage Binary Ripple Counter14Stage Binary Ripple Counter

12Stage Binary Ripple Counter

14Stage Binary Ripple Counter with Oscillator

LS393

*45204020

4040

4060



Device

HC

161A

HC

163A

HC

390A

HC

393A

HC

4020

# Pins

16

16

16

14

16

Single Device

Dual Device

D

D

D

D

D

Ripple Counter

Number of Ripple Counter Internal Stages

Number of Stages with Available Outputs

D

4

4

D

4

4

D

14

12

Count Up

D

D

D

D

D

4Bit Binary Counter

BCD Counter

Decimal Counter

D

D

D

D

Separate 2 Section

Separate 5 Section

D

D

OnChip Oscillator Capability


NegativeTransition Clocking

ActiveHigh Clock EnableActiveLow Clock Enable

D

D

D

D

D

ActiveHigh Count Enable

D D

D D

ActiveHigh Reset

D

D

D

D

D

4Bit Binary Preset Data Inputs

BCD Preset Data Inputs

D

D


23/407

MISCELLANEOUS DEVICES

Device

Number

MC74

Function

Functional

EquivalentLSTTL

Device

74

Functional

Equivalent

CMOS

Device

MC1XXXX

or CDXXXX

C

HC4046A

HC4538A

PhaseLocked Loop

Dual Precision Monostable Multivibrator

(Retriggerable, Resettable)

4046

4538,4528


24/407

CH

Design Consi

Introduction . . . . . . . . . . . . . . . .

Handling Precautions . . . . . . . .

Power Supply Sizing . . . . . . . . .

Inputs . . . . . . . . . . . . . . . . . . . . .

Outputs . . . . . . . . . . . . . . . . . . . .CMOS Latch Up . . . . . . . . . . . .

Maximum Power Dissipation . .

Thermal Management . . . . . . .

Capacitive Loading Effects onPropagation Delay . . . . . . . . . .

Temperature Effects on DC andParameters . . . . . . . . . . . . . . . .

Supply Voltage Effects on Drive

and Propagation Delay . . . . . . .Decoupling Capacitors . . . . . . .

Interfacing . . . . . . . . . . . . . . . . .

Typical Parametric Values . . . .

Reduction of ElectromagneticInterference (EMI) . . . . . . . . . . .

Hybrid Circuit Guidelines . . . . .

SchmittTrigger Devices . . . . .

Oscillator Design with HighSp

Printed Circuit Board Layout . .Definitions and Glossary of Ter

Applications Assistance Form .


25/407

INTRODUCTION

CMOS devices have been used for many years in

applications where the primary concerns were low power

consumption, wide powersupply range, and high noise

immunity. However, metalgate CMOS (MC14000 series)

is too slow for many applications. Applications requiring

highspeed devices, such as microprocessor memory

decoding, had to go to the faster families such as LSTTL.

This meant sacrificing the best qualities of CMOS. The next

step in the logic evolution was to introduce a family of

devices that were fast enough for such applications, while

retaining the advantages of CMOS. The results of this

change can be seen in 1 where HSCMOS devices are

compared to standard (metalgate) CMOS, LSTTL, and

ALS.

The ON Semiconductor CMOS evolutionary process

shown in Figure 1 indicates that one advantage of the

silicongate process is device size. The HighSpeed CMOS

(HSCMOS) device is about half the size of the metalgate

predecessor, yielding significant chip area savings. The

silicongate process allows smaller gate or channel lengths

due to the selfaligning gate feature.

gate to define the channel during pr

registration errors and, therefore, the n

The elimination of the gate overlap si

gate capacitance, resulting in higher

smaller gate length also results in high

unit gate width, ensuring more effic

Immunity enhancements to electrost

damage and latch up are ongoing. Prec

taken, however, to guard against elect

latch up.

ON Semiconductorss HighSpeed

broad range of functions from basic

counters to buscompatible devices. T

of devices that are identical in pinou

equivalent to LSTTL devices, as wel

metalgate devices not available in TT

has an excellent alternative to exis

having to become familiar with a new

METAL GATE CMOSMETALOXIDEP+ N+ P+ P+ P+N+ N+

120 m

P N

65 m

POLMETAL

PSGOXIDE

HIGHSPEED

SILICONGATEHSCMOS

PN

N+ P P+ P+N+ N

Figure 1. CMOS Evolution

HANDLING PRECAUTIONS

HighSpeed CMOS devices, like all MOS devices, have

an insulated gate that is subject to voltage breakdown. The

gate oxide for HSCMOS devices breaks down at a

gatesource potential of about 100 volts. Some device inputs

are protected by a resistordiode network (Figure 2). New

input protection structure deletes the poly resistor (Figure 3)

Using the test setup shown in Figure 4, the inputs typically

withstand a > 2 kV discharge.

SILICONGATE

CMOSINPUT 150 POLY

VCC

D1

Figure 2. Input Protectio


26/407

Table 1. Logic Family Comparisons

General Characteristics (1) (All Maximum Ratings)

TTL

CMOS

Characteristic

Symbol

LS

ALS

MC14000

Operating Voltage Range

VCC/EE/DD

5 5%

5 5%

3.0 to 18

Operating Temperature Range

TA

0 to + 70

0 to + 70

40 to + 85

Input Voltage (limits)

VIH min

2.0

2.0

3.54

VIL max

0.8

0.8

1.54

Output Voltage (limits)

VOH min

2.7

2.7

VDD 0.05

VOL max

0.5

0.5

0.05

Input Current

IINH

20

20

IINL

400

200

.

Output Current @ VO (limit)

unless otherwise specified

IOH

0.4

0.4

2.1 @ 2.5 V

V

IOL

8.0

8.0

0.44 @ 0.4 V

DC Noise Margin Low/High

DCM

0.3/0.7

0.3/0.7

1.454

DC Fanout

20

20

50(1)2

Speed/Power Characteristics (1) (All Typical Ratings)

TTL

CMOS

Characteristic

Symbol

LS

ALS

MC14000

Quiescent Supply Current/Gate

IG

0.4

0.2

0.0001

Power/Gate (Quiescent)

PG

2.0

1.0

0.0006

Propagation Delay

tp

9.0

7.0

125

Speed Power Product

18

7.0

0.075

Clock Frequency (DF/F)

fmax

33

35

4.0

Clock Frequency (Counter)

fmax

40

45

5.0

Propagation Delay (1)

TTL

CMOS

Characteristic

LS

ALS

MC14000

Gate, NOR or NAND: Product No.

SN74LS00

SN74ALS00

MC14001B

tPLH/tPHL(5) Typical

(10)3

(5)3

25

Maximum

(15)3

10

250

FlipFlop, Dtype: Product No.

SN74LS74

SN74ALS74

MC14013B

tPLH/tPHL(5)

(Clock to Q) Typical

(25)3

(12)3

175

Maximum

(40)3

20

350

Counter: Product No.

SN74LS163

SN74ALS163

MC14163B

tPLH/tPHL(5) (Clock to Q) Typical

(18)3

(10)3

350

Maximum (27)3 24 700

NOTES:


27/407

The input protection network consists of large ESD

protection diodes, a diffused resistor, and two small

dummy transistors. Outputs have a similar ESD

protection network except for the series resistor. Although

the onchip protection circuitry guards against ESD

damage, additional protection may be necessary once the

chip is placed in circuit. Both an external series resistor and

ground and VCC diodes, similar to the input protection

structure, are recommended if there is a potential of ESD,

voltage transients, etc. Several monolithic diode arrays are

available from ON Semiconductor, such as the MAD130

(dual 10 diode array) or the MAD1104 (dual 8 diode array).

These diodes, in chip form, not only provide the necessary

protection, but also save board space as opposed to using

discrete diodes.

Static damaged devices behave in various ways,

depending on the severity of the damage. The most severely

damaged pins are the easiest to detect. An ESDdamaged

pin that has been completely destroyed may exhibit a

lowimpedance path to VCC or GND. Another common

failure mode is a fused or open circuit. The effect of both

failure modes is that the device no longer properly responds

to input signals. Less severe cases are more difficult to detect

because they show up as intermittent failures or as degraded

performance. Generally, another effect of static damage is

increased chip leakage currents (ICC).

Although the input network does offer significant

protection, these devices are not immune to large static

voltage discharges that can be generated while handling. For

example, static voltages generated by a person walking

across a waxed floor have been measured in the 4 to 15 kV

range (depending on humidity, surface conditions, etc.).

Therefore, the following precautions should be observed.

1. Wrist straps and equipment logs

and audited on a regular

malfunction and may go unnoti

gets moved from time to time an

reconnected properly.

2. Do not exceed the Maximum R

data sheet.

3. All unused device inputs should

or GND.

4. All low impedance equipment (

should be connected to CMOS

CMOS device is powered up. S

equipment should be disconne

turned off.

5. Circuit boards containing CMO

extensions of the devices, an

precautions apply. Contacting e

directly to device inputs can c

wrapping should be avoid

connectors to a PC board are co

output of a CMOS device, a resi

series with the input or output. T

accidental damage if the PC b

brought into contact with static

The limiting factor for the serie

delay. The delay is caused by the

by the series resistor and input c

the maximum input rise and fa

exceeded. In Figure 5, two p

shown using a series resistor to

For convenience, an equation

propagation delay and rise tim

resistance size.

Advantage: Requires minimal area

Disadvantage:R1 > R2 for the same level of

protection; therefore, rise and

fall times, propagation delays,

and output drives are severely

affected.

Advantage: R2 < R1 for the

protection. Imp

characteristics

Disadvantage:More board are

cost.

TO OFFBOARD

CONNECTION

R1CMOS

INPUT

OR

OUTPUT

TO OFFBOARD

CONNECTION

R2

VCC

GND

Propagation Delay and Rise Time vs. Series Resistance

NOTE: These networks are useful for protecting the following:

A digital inputs and outputs C 3state outputs

B analog inputs and outputs D bidirectional (I/O) ports


28/407

6. All CMOS devices should be stored or transported in

materials that are antistatic or conductive. CMOS

devices must not be inserted into conventional plastic

snow, Styrofoam, or plastic trays, but should be left

in their original container until ready for use.

7. All CMOS devices should be placed on a groundedbench surface and operators should ground

themselves prior to handling devices, because a

worker can be statically charged with respect to the

bench surface. Wrist straps in contact with skin are

essential and should be tested daily. See Figure 6 for

an example of a typical work station.

8. Nylon or other static generating materials should not

come in contact with CMOS devices.

9. If automatic handlers are being used, high levels of

static electricity may be generated by the movement

of the device, the belts, or the boards. Reduce static

buildup by using ionized air blowers, antistatic

sprays, and room humidifiers. All conductive parts of

machines which come into contact with the top,

bottom, or sides of IC packages must be grounded to

earth ground.

10. Cold chambers using CO2 for cooling should be

equipped with baffles, and the CMOS devices must be

contained on or in conductive material.

11. When lead straightening or hand soldering is

necessary, provide ground straps for the apparatus

used and be sure that soldering iron tips are grounded.

12. The following steps should be observed during wave

solder operations:

a. The solder pot and conductive conveyor system of

the wave soldering machine must be grounded to

earth ground.

b. The loading and unloading work benches should

have conductive tops grounded to earth ground.

c. Operators must comply with precautions

previously explained.

d. Completed assemblies should be placed in

antistatic or conductive containers prior to being

moved to subsequent stations.

13. The following steps should be observed during

boardcleaning operations:

a. Vapor degreasers and baskets must be grounded to

earth ground.

b. Brush or spray cleaning sho

c. Assemblies should be pla

degreaser immediately upo

antistatic or conductive cont

d. Cleaned assemblies should

or conductive containersremoval from the cleaning b

e. High velocity air moveme

solvents and coatings shou

when a static eliminator

directed at the printed circui

14. The use of static detection mete

surveillance is highly recomme

15. Equipment specifications shou

presence of CMOS dev

familiarization with this sp

performing any kind of mainte

of devices or modules.

16. Do not insert or remove CMO

sockets with power applied. Ch

to be used for testing devices to

voltage transients present.

17. Double check test equipment se

of VCC and GND before cond

functional testing.

18. Do not recycle shipping rails.

deterioration of their antistatic

carbon rails (black color) may

extent. This type of rail is cond

RECOMMENDED READING

Requirements for Handling ElectrSensitive (ESDS) Devices EIA St

Available by writing to:

Global Engineering Documen

15 Inverness Way East

Englewood, Colorado 80112

Or by calling:

18008547179 in the USA

(303) 3977956 International

S. Cherniak, A Review of TransientSuppression, Application Note843

Products Inc., 1982.


29/407

NOTES:

1. 1/16 inch conductive sheet stock

area.

2. Ground strap.3. Wrist strap In contact with skin.

4. Static neutralizer. (ionized air

Primarily for use in areas w

impractical.

5. Room humidifier. Primarily for

relative humidity is less than

heating and cooling systems u

the relative humidity inside a

outside humidity.

R = 1 MW

1

2

3

4

5

Figure 6. Typical Manufacturing Work Station

POWER SUPPLY SIZING

CMOS devices have low power requirements and the

ability to operate over a wide range of supply voltages.

These two characteristics allow CMOS designs to be

implemented using inexpensive power supplies withoutcooling fans. In addition, batteries may be used as either a

primary power source or as a backup.

The maximum recommended power supply voltage for

HC devices is 6.0 V and 5.5 V for HCT devices. Figure 7

offers some insight as to how this specification was derived.

In the figure, VS is the maximum power supply voltage and

IS is the sustaining current for the latchup mode. The value

of VS was chosen so that the secondary breakdown effect

may be avoided. The lowcurrent junction avalanche regionis between 10 and 14 volts at TA = 25 _ C.

ICC

IS

VS VCC

LATCH

UP MODESECONDARY

BREAKDOWN

LOW CURRENT

JUNCTION

AVALANCHE

operation of all devices. The obvious

design is cost savings.

BATTERY SYSTEMS

HSCMOS devices can be used w

backup systems. A few precautions s

designing batteryoperated systems.

1. The recommended power supp

observed. For battery backup sy

in Figure 8, the battery volta

2.7 volts (2 volts for the min

voltage and 0.7 volts to accoun

across the series diode).

2. Inputs that might go above the b

should use the HC4049 or HC40

If line power is interrupted, C

Buffer A lose power. However,

Buffer B remain active due to

Buffer A protects System A

blocking active inputs while the

up. Also, if the power supply vo

battery voltage, Buffer A acts a

the outputs from System B. Bu

System B from any overvoltag

Both buffers may be replaced

resistors, however power cons

and propagation delays are leng

3 Outputs that are subject to volt


30/407

POWER SUPPLY

BATTERY TRICKLE

RECHARGE

CMOS

SYSTEM

Figure 8. Battery Backup SystemPOWER SUPPLY

LINE POWER ONLY

SYSTEM

CMOSSYSTEM

HC4049

HC4050

BATTERY BACKUP

SYSTEM

HC4049

HC4050

BATTE

REC

CMOSSYSTEM

A B

Figure 9. Battery Backup Interface

CPD POWER CALCULATIONPower consumption for HSCMOS is dependent on the

powersupply voltage, frequency of operation, internal

capacitance, and load. The power consumption may be

calculated for each package by summing the quiescent

power consumption, ICC VCC, and the switching powerrequired by each device within the package. For large

systems, the most timely method is to breadboard the

circuit and measure the current required under a variety of

conditions.The device dynamic power requirements can be

calculated by the equation:

PD = (CL + CPD) VCC2f

where: PD = power dissipated in W

CL total load capacitance present at the output

1 MHz and the following formula is devices CPD value:

ICC (dynamic)CPD =

VCC f

The resulting power dissipation is cal

follows under noload conditions.

(HC) PD = CPDVCC2f + VCCICC

(HCT) PD

= CPD

VCC

2f + VCC

ICC

(1 + 2 + + n)

where the previously undefined variab

of each input applied at TTL/NMOS

The power dissipation for analog

digital signals is the following:


31/407

Gates: Switch one input while the remaining

input(s) are biased so that the output(s)

switch.

Latches: Switch the enable and data inputs such that

the latch toggles.

FlipFlops: Switch the clock pin while changing the

data pin(s) such that the output(s) change

with each clock cycle.

Decoders/ Switch one address pin which changes two

Demultiplexers: outputs.

Data Selectors/ Switch one address input with the corre-

Multiplexers: sponding data inputs at opposite logic

levels so that the output switches.

Analog Switch one address/select pin which

Switches: changes two switches. The switch

inputs/outputs should be left open. For

digital applications where the switch

inputs/outputs change between VCC and

GND, the respective switch capacitance

should be added to the load capacitance.

Counters: Switch the clock pin with the other inputs

biased so that the device counts.

Shift Switch the clock while alternating the

input

Registers: so that the device shifts alternating 1s and

0s through the register.

Transceivers: Switch only one data input. Place

transceivers in a single direction.

Monostables: The pulse obtained with a resistor and no

external capacitor is repeatedly switched.Parity Switch one input.

Generators:

Encoders: Switch the lowest priority output.

Display Switch one input so that approximately

one

Drivers: half of the outputs change state.

ALUs/Adders: Switch the least significant bit. The

remaining inputs are biased so that thedevice is alternately adding 0000 (binary)

or 0001 (binary) to 1111 (binary).

On HSCMOS data sheets, CPD is a typical value and is

given either for the package or for the individual device (i.e.,

gates flipflops etc ) within the package An example of

PD = (CPD + CL)VCC2f + V

PD1 = (22 pF + 50 pF)(5 V)2

PD2 = (22 pF + 50 pF)(5 V)2

PD3 = (22 pF) (5 V)2(0 Hz) =

PD4 = (22 pF)(5 V)2(0 Hz) =

PD(total) = VCCICC + PD1 + PD2

= 10 W + 1.8 W + 1

= 1812 W

VCC = 5 V

f = 1 kHz

f = 1 MHz

50 pF

1

2

50 pF

Figure 10. Power Consumption C

As seen by this example, the power

devices is dependent on frequency. W

high frequencies, HSCMOS devices

power as LSTTL devices, as shown in

savings of HSCMOS is realized wh

where only a few of the devices are ac

system frequency. The power consum

from the fact that for CMOS, only

switching consume significant power

100 m

5

2

10 m

5

2

1 m

5

2

100

5

2

POWER(W

ATTS)

MC7400

SN74LS00

SN74ALS00

MC74HC00


32/407

INPUTS

A basic knowledge of input and output structures is

essential to the HSCMOS designer. This section deals with

the various input characteristics and application rules

regarding their use. Output characteristics are discussed inthe section titled Outputs.

All standard HC, HCU and HCT inputs, while in the

recommended operating range (GNDv Vinv VCC), can bemodeled as shown in Figure 12. For input voltages in this

range, diodes D1 and D2 are modeled as resistors

representing the highimpedance of reverse biased diodes.

The maximum input current is 1 A, worst case overtemperature, when the inputs are at VCC or GND, and VCC

= 6 V.

VCC

R1

10 pF

R1 = R2 = HIGH Z

R2

Figure 12. Input Model for GNDv

Vinv VCC

When CMOS inputs are left opencircuited, the inputs

may be biased at or near the typical CMOS switchpoint of

0.45 VCC for HC devices or 1.3 V for HCT devices. At this

switchpoint, both the Pchannel and the Nchannel

transistors are conducting, causing excess current drain. Due

to the high gain of the buffered devices (see Figure 13), the

device can go into oscillation from any noise in the system,

resulting in even higher current drain.

V

,OUTPUTVOLTAGE(V)

out

5

4

3

2

1

HCT HC

this chapter, for series resistor consid

should be configured as in Figure 14.

RS

100 kW

FROM

EDGE

CONNECTOR

Figure 14. External Pro

For inputs outside of the recomme

the CMOS input is modeled as in Fig

Current flows through diode D1 or D

voltage exceeds VCC or drops bel

forward bias either D1 or D2. Th

guaranteed to withstand from GND

and a maximum current of 20 mA. If

is exceeded, the device could go into

(See CMOS Latch Up, this chapter.)

be applied to any input or output pin b

applied to the devices power pins. B

pins should be removed before r

However, if the input current is limite

and this current only lasts for a brief

ms), no damage to the device occurs.

Another specification that shou

maximum input rise (tr) and fall (tf) ti

the results of exceeding the maximu

recommended by ON Semiconduc

JEDEC Standard No. 7A. The reason

the output is that as the voltage passes

threshold region with a slow rise tim

the input line is amplified, and is p

output. This oscillation may have a l

to cause succeeding stages to switc

results. If input rise or fall times are e

maximum specified rise or fall tim

devices such as ON Semiconductors

are recommended.

OUTPUTS

All HSCMOS outputs, with thHCU04A, are buffered to ensure con

and current specifications across the

outputs have guaranteed output voltag

VOH = VCC 0.1 V for Ioutv 20loads).


33/407

latch up condition could be triggered. (See CMOS Latch

Up, this chapter.)

The maximum rated output current given on the

individual data sheets is 25 mA for standard outputs and 35

mA for bus drivers. The output short circuit currents of these

devices typically exceed these limits. The outputs can,however, be shorted for short periods of time for logic

testing, if the maximum package power dissipation is not

violated. (See individual data sheets for maximum power

dissipation ratings.)

For applications that require driving high capacitive loads

where fast propagation delays are needed (e.g., driving

power MOSFETS), devices within the same package may be

paralleled. Paralleling devices in dif

result in devices switching at differe

voltage waveform, creating outpu

yielding undesirable output voltage w

As a design aid, output characteri

for both Pchannel source and NcThe curves given include expected

TA = 25 _ C, 85_ C, and 125 _ C, as wel

TA = 25 _ C. For temperatures < 25 _ C

These curves, Figure 18 through Figu

design aids, not as guarantees. Unused

opencircuited (floating).

Figure 15. Input Model for Vin > VCC or Vin < GND

150 W

Vin

Vout

D1

D23 pF 2 pF

Figure 16. Input Model for New ESD Enhanced Circuits

D1

D23 pF 2 pF

Figure 17. Maximum Rise


34/407

STANDARD OUTPUT CHARACTERISTICS

NCHANNEL SINK CURRENT PCHANNEL SOURCE

Figure 18. VGS = 2.0 V Figure 19. VGS =

I

,OUTPUTSINKCURRENT(mA)

o

ut

Vout, OUTPUT VOLTAGE (V)

I

,OUTPUTSOURCECURRENT(mA

)

out

TYPICAL

TA = 25 _ C

EXPECTED MINIMUM*, TA = 25125 _ C

TYPICAL

TA = 25 _ C

EXPECTED MINI

25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.0 1.5 1.0

25

20

15

10

5

0

Vout, OUTPUT VOLTA


TYPICAL

TA = 25 _ C TA = 25 _ C

TA = 85 _ C

TA = 125 _ C

EXPECTED MINIMUM CURVES*I


out


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.0 3.5 3.0

25

20

15

10

5

0

Vout, OUTPUT VOLTA

2.5 2.0

TYPICAL

TA = 25 _ C

EXPECTED MI

I

,OUTPUTSOURCECURRENT(m

A)

o

ut

PUTSINKCURRENT(m

A)

25

20

15

10

25

20

15

10

TYPICAL

TA

= 25_

C

TA = 25 _ C TA = 85 _ C

TA = 125_

C

EXPECTED MINIMUM CURVES*

TYPICAL

TA = 25 _ C

TA = 25 _ CTA = 85 _

TA = 125

EXPECTED MINIMUMT

SOURCECURRENT

(mA)


35/407

BUSDRIVER OUTPUT CHARACTERISTICS

NCHANNEL SINK CURRENT PCHANNEL SOURCE


I,

OUTPUTSOURCECURRENT(mA)

out


I


out

TYPICAL

TA = 25 _ C

EXPECTED MINIMUM*, TA = 25125 _ C

TYPICAL

TA = 25 _ C

EXPECTED MIN

25

20

15

10

5

00.5 1.0 1.5 2.0 2.0 1.5 1.0

25

20

15

10

5

0

Vout, OUTPUT VOLTA

30

35

0

30

35


TYPICAL

TA = 25 _ C TA = 25 _ C

TA = 85 _ C

TA = 125 _ C

EXPECTED MINIMUMS*


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

I

,OUTPUTSINKCURRENT(mA

)

out

4.5 4.0 3.5 3.0

25

20

15

10

5

0

Vout, OUTPUT VOLTA

2.5 2.0

TYPICALTA = 25 _ C

TA = 25

EXPECTED M

I

,OUTPUTSOURCECURRENT(m

A)

out

30

35

30

35

25

20

15

PUTSINKCURRENT(mA)

25

20

15

TYPICAL

TA = 25_

CTA = 25 _ C

TA = 85 _ C

TA = 125 _ C

EXPECTED MINIMUMS*

TYPICAL

TA = 25 _ C

TA = 25 _ C

TA = 85 _ C

TA = 125 _ C

TSOURCECURRENT

(mA)

30

35

30

35


36/407

3STATE OUTPUTS

Some HC/HCT devices have outputs that can be placed

into a highimpedance state. These 3state output devices

are very useful for gang connecting to a common line or bus.

When enabled, these output pins can be considered as

ordinary output pins; as such, all specifications andprecautions of standard output pins should be followed.

When disabled (highimpedance state), these outputs can be

modeled as in Figure 30. Output leakage current (10 Aworst case over temperature) as well as 3state output

capacitance must be considered in any bus design.

When power is interrupted to a 3state device, the bus

voltage is forced to between GND and VCC + 0.7 V

regardless of the previous output state.

R1

VCC

R1 = R2 = HIGH Z

OUTPUT

15 pFR2

INTERNAL

CIRCUITRY

Figure 30. Model for Disabled Outputs

OPENDRAIN OUTPUTS

ON Semiconductor provides several devices that are

designed only to sink current to GND. These opendrain

output devices are fabricated using only an Nchannel

transistor and a diode to VCC (Figure 31). The purpose of thediode is to provide ESD protection. Opendrain outputs can

be modeled as shown in Figure 32.VCC

INTERNAL

CIRCUITRY

OUTPUT

VCC

LOW Z

HIGH Z

HIGH Z

Figure 32. Model of OpenD

INPUT/OUTPUT PINS

Some HC/HCT devices contain pi

inputs and outputs of digital logic. The

as digital I/O pins. The logic level ap

determines whether these I/O pins ar

outputs.

When I/O pins are selected as outp

considered as standard CMOS outpuinputs, except for an increase in inpu

input capacitance, these pins shou

standard CMOS inputs. These increas

that a digital I/O pin is actually a comb

a 3state output tied together (see Fig

As stated earlier, all HC/HCT input

an appropriate logic level. This could

I/O pin is selected as an input wh

improperly terminated bus.ON Semiconductor recomm

HC/HCTtype buses with resistors

between 1 k to 1 M in value. The cis a tradeoff between speed and pow

Bus Termination, this chapter).

Some ON Semiconductor devices

These analog I/O pins should not be

I/O pins. Analog I/O pins may be mo

These devices can be used to pass anadigital signals, in the same manner as

b bl d i h l l f


37/407

I/O

INTERNAL

CIRCUITRY

Figure 33. Typical Digital I/O Pin

GND OR VEEGND OR VEE

Ron

VCC VCC

HIGH Z

HIGH Z

ANALOG

I/O

ANALOG

O/I

Figure 34. Analog I/O Pin

BUS TERMINATION

Because buses tend to operate in harsh, noisy

environments, most bus lines are terminated via a resistor to

VCC or ground. This low impedance to VCC or ground

(depending on preference of a pullup or pulldown logic

level) reduces bus noise pickup. In certain cases a bus line

may be released (put in a highimpedance state) by disabling

all the 3state bus drivers (see Figure 35). In this condition

all HC/HCT inputs on the bus would be allowed to float. A

CMOS input or 1/0 pin (when selected as an input) should

never be allowed to float. (This is one reason why an HCT

device may not be a dropin replacement of an LSTTL

device.) A floating CMOS input can put the device into the

linear region of operation. In this region excessive current

can flow and the possibility of logic errors due to oscillation

may occur (see Inputs, this chapter). Note that when a bus

is properly terminated with pullup resistors, HC devices,

instead of HCT devices, can be driven by an NMOS or

LSTTL bus driver. HC devices are preferred over HCT

devices in bus applications because of their higher low level

input noise margin. (With a 5 V supply the typical HC switch

point is 2.3 V while the switch point of HCT is only 1.3 V.)

Some popular LSTTL bus termination designs may not

work for HSCMOS devices The outputs of HSCMOS may

not be able to drive the low value of

some buses. (This is another reason wh

not be a drop in replacement for

However, because low power operati

reasons for using CMOS, an op

termination is usually advantageous.B

ENABLE INPUT(HIGH = 3STATE)

ENABLE INPUT

(LOW = 3STATE)

Figure 35. Typical Bus Line with 3

The choice of termination resist

between speed and power consumpt

bus is a function of the RC time const

resistor and the parasitic capacitanc

bus. Power consumption is a function

or pulldown resistor is used and th

device that has control of the bus (see the termination resistor the faster the b

power is consumed. A large value resi

but slows the bus down. ON Semicon

termination resistor value between

alternative to a passive resistor term

activetype termination (see Figu

termination holds the last logic level o

can once again take control of the bus.

has the advantage of consuming a minMost HC/HCT bus drivers do not ha

Therefore, heavily loaded buses can s

signals and exceed the input rise/fall ti

Standard No. 7A. In this ev

Schmitttriggered inputs should be u

l i l

VCC


38/407

(a) USING A PULL-UP RESISTOR (b) USING A PULL-DOWN

VCC

VCC

VCC

(L)

I R

BUS

(H)

I

Figure 36.

BUS LINES ENABLE

Figure 37. Using Active Termination (HC125)

TRANSMISSION LINE TERMINATION

When data is transmitted over long distances, the line on

which the data travels can be considered a transmission line.

(Long distance is relative to the data rate being transmitted.)

Examples of transmission lines include highspeed buses,

long PCB lines, coaxial and ribbon cables. All transmission

lines should be properly terminated into a lowimpedance

termination. A lowimpedance termination helps eliminatenoise, ringing, overshoot, and crosstalk problems. Also a

lowimpedance termination reduces signal degradation

because the small values of parasitic line capacitance and

inductance have lesser effect on a lowimpedance line.

The value of the termination resistor becomes a tradeoff

Transmission line distance become

rates increase. As data rates inc

reflective) waves begin to resemble th

line theory. However, due to the no

digital logic, conventional RF trans

applicable.

HC devices are preferred over HCT

that HC devices have higher swit

devices. This higher switch point aachieve better incident wave switchin

lines.

HC/HCT may not have enough

interface with some of the mo

transmission lines. (Possible reason

may not be a dropin replacement o

device.) This does not pose a major

larger value termination resistors is

type transmission lines.By increasing the termination resist

advantage of low power consumptio

Semiconductor recommends a m

resistor value as shown in Figure

resistor should be as close to the rece

Another method of terminating the lin

receiving unit, is shown in Figure 39.

values in Figure 39 are twice the resist

this gives a net equivalent terminatioEven higher values of resistors ma

termination method. This reduces po

at the expense of speed and possible

VCC V and have sufficient current to t


39/407

VCC

R1 = 1.5 kW

R1 = 1.0 k W

HSCMOS

(LINE DRIVER)

HSCMOS

(RECEIVER)

R1

R2

Figure 38. Termination Resistors at the Receiver

VCCVCC

R1 = R3 = 3.0 kW

R2 = R4 = 2 k W

HSCMOS HSCMOS

R1 R3

R2 R4

Figure 39. Termination Resistors at

Both the Line Driver and Receiver

CMOS LATCH UP

Typically, HSCMOS devices do not latch up with currents

of 75 mA forced into or out of the inputs or 300 mA for the

outputs under worst case conditions (TA = 125 _ C and VCC= 6 V). Under dc conditions for the inputs, the input

protection network typically fails, due to grossly exceeding

the maximum input voltage rating of 0.5 to VCC + 0.5 V

before latchup currents are reached. For most designs, latchup will not be a problem, but the designer should be aware

of it, what causes it, and how it can be prevented.

Figure 40 shows the layout of a typical CMOS inverter

and Figure 41 shows the parasitic bipolar devices that are

formed. The circuit formed by the parasitic transistors and

resistors is the basic configuration of a silicon controlled

rectifier, or SCR. In the latchup condition, transistors Q1

and Q2 are turned on, each providing the base current

necessary for the other to remain in saturation, therebylatching the device on. Unlike a conventional SCR, where

the device is turned on by applying a voltage to the base of

the NPN transistor, the parasitic SCR is turned on by

applying a voltage to the emitter of either transistor. The two

emitters that trigger the SCR are the same point, the CMOS

V and have sufficient current to t

latchup mechanism is similar for the

Once a CMOS device is latched up

is not limited, the device can be destr

can be degraded. Ways to prevent su

listed below.1. Industrial controllers driving r

environment in which latch up i

Also, the ringing due to

transmission lines in an ind

provide enough energy to latc

Optoisolators, such as O

MOC3011, are recommended

latch up. See the ON Semicondu

Guide for a complete listing ooptoisolators.

2. Ensure that inputs and outpu

maximum rated values.

1.5v

Vin v VCC +1.5 V

0.5v

Vin v VCC +0.5 V

0.5v

Vout v VCC +0.5 V

|Iin| v 20 mA

|Iout|v

25 mA for standard |Iout| v 35 mA for busdrive

3. If voltage transients of sufficien

device are expected on the inpu

protection diodes can be used

Another method of protection is

to limit the expected worst

maximum ratings value. See H

for other possible protection cir

of ESD prevention.

4. Sequence power supplies so tha

of HSCMOS devices are not ac

pins are powered up (e.g., rece

and/or series resistors may be u

applications).

5. Voltage regulating and filterin

board design and layout to ensu

lines are free of excessive noise

6. Limit the available power su

devices that are subject to latch

can be accomplished with the p

network or with a currentlimi

RECOMMENDED READING


40/407

VCC VCC

PCHANNEL NCHANNEL

INPUT

OUTPUTPCHANNEL

OUTPUT

NCHANNEL

OUTPUT

GND

FIELD OXIDE FIELD OXIDE FIEN+ P+ P+ N+ N+ P+

P WELLN SUBSTRATE

Figure 40. CMOS Wafer Cross Section

VCC

VCC

PCHANNEL OUTPUT P WELL RESISTANQ1

P+

P+

N

P

NCHANNEL OUTPN SUBSTRATE RESISTANCE

P

N+N+N

Q2

Figure 41. LatchUp Circuit Schematic

MAXIMUM POWER DISSIPATION Worstcase ICC occurs at VCC = 6


41/407

MAXIMUM POWER DISSIPATION

The maximum power dissipation for ON Semiconductor

HSCMOS packages is 750 mW for both ceramic and plastic

DIPs and 500 mW for SOIC packages. The deratings are

10 mW/_

C from 65_

C for plastic DIPs, and 7 mW/_

C from65 _ C for SOIC packages. This is illustrated in Figure 42.

40 0 40 80 120

100

200

300

400

500

600

800

PD,

MAXIMUMPACKAGEPOWERDISSIPATION(mW)

TA, AMBIENT TEMPERATURE (C)

700

PLASTIC

DIP

TSSOP

PACKAGE

SOIC

PACKAGE

Figure 42. Maximum Package PowerDissipation versus Temperature

Internal heat generation in HSCMOS devices comes from

two sources, namely, the quiescent power and dynamic

power consumption.

In the quiescent state, either the Pchannel or Nchannel

transistor in each complementary pair is off except for small

sourcetodrain leakage due to the inputs being either at

VCC or ground. Also, there are the small leakage currentsflowing in the reversebiased input protection diodes and

the parasitic diodes on the chip. The specification which

takes all leakage into account is called Maximum Quiescent

Supply Current (per package), or ICC, and is shown on all

data sheets.

The three factors which directly affect the value of

quiescent power dissipation are supply voltage, device

complexity, and temperature. On the data sheets, ICC is

specified only at VCC = 6.0 V because this is the worstcasesupply voltage condition. Also, larger or more complex

devices consume more quiescent power because these

devices contain a proportionally greater reversebiased

diode junction area and more off (leaky) FETs.

Finally, as can be seen from the data sheets, temperature

Worst case ICC occurs at VCC 6

at VCC = 6.0 V, as specified in the dat

power supply voltages from 2 to 6 V.

HCT QUIESCENT POWER DISSIPA

Although HCT devices belong to thinput voltage specifications are identi

HCT parts can therefore be either judi

or mixed with LS devices in a system

TTL output voltages are VOLVOH = 2.4 to 2.7 V (min).

Slightly higher ICC current exists w

driven with VOL = 0.4 V (max) becau

enough to partially turn on the N

However, when being driven with a TTexhibit large additional current flow (

HCT device data sheets. ICC curroffrail input voltage turning on both

of the input buffer. This condition o

impedance path from VCC to GND

quiescent power dissipation is depen

inputs applied at the TTL VIH logic v

The equation for HCT quiescent

given by:PD = ICCVCC + IC

where = the number of inputs at the

HC AND HCT DYNAMIC POWER D

Dynamic power dissipation is calcu

for both HC and HCT devices. The

which directly affect the magnitud

dissipation are load capacitance, inte

switching transient currents.The dynamic power dissipation due

given by the following equation:

PD = CLVCC2f

where PD = power in W, CL = cVCC = supply voltage in volts, and

driving the load capacitor in MHz.

All CMOS devices have internal p

that have the same effect as externalmagnitude of this internal noloa

capacitance, CPD, is specified as a ty

Finally, switching transient curren

power dissipation. As each gate swi

period of time in which both N and

PD = (CL + CPD)VCC2f TJ = TA + PD(JA)


42/407

D L PD CC

Total power dissipation for HC and HCT devices is merely

a summation of the dynamic and quiescent power

dissipation elements. When being driven by CMOS logic

voltage levels (rail to rail), the total power dissipation for

both HC and HCT devices is given by the equation:

PD = VCCICC + (CL + CPD)VCC2f

When being driven by LSTTL logic voltage levels, the

total power dissipation for HCT devices is given by the

equation:

PD =VCCICC + VCCICC(, + 2 + + n)

+ (CL + CPD)VCC2f

wheren = duty cycle of LSTTL output applied to each inputof an HCT device.

THERMAL MANAGEMENTCircuit performance and long-term circuit reliability are

affected by die temperature. Normally, both are improved by

keeping the IC junction temperatures low.

Electrical power dissipated in any integrated circuit is a

source of heat. This heat source increases the temperature of

the die relative to some reference point, normally theambient temperature of 25C in still air. The temperatureincrease, then, depends on the amount of power dissipated

in the circuit and on the net thermal resistance between the

heat source and the reference point. See page 29 for the

calculation of CMOS power consumption.

The temperature at the junction is a function of the

packaging and mounting systems ability to remove heat

generated in the circuit from the junction region to the

ambient environment. The basic formula for convertingpower dissipation to estimated junction temperature is:

TJ = TA + PD(JC + CA) ( 1 )

or

J A D JA

where

TJ = maximum junction tempe

TA = maximum ambient tempe

PD = calculated maximum powincluding effects of extern

Dissipation on page 40).

JC = average thermal resistan

CA = average thermal resistan

JA = average thermal resistanc

This ON Semiconductor recommen

approved by RADC and DESC for ca

maximum operating junction MIL-M-38510 (JAN) devices.

Only two terms on the right side of

varied by the user the ambient

device case-to-ambient thermal resist

extent the device power dissipation c

but under recommended use the VCdictate a fixed power dissipation.) Bo

the package mounting technique aff

resistance term. JC is essentially inand external mounting method, but imaterial, die bonding method, and di

For applications where the case is

fixed temperature by mounting on a

controlled heat sink, the estimated ju

calculated by:

TJ = TC + PD(JC)

where TC = maximum case tempe

parameters are as previously definedThe maximum and average JC

standard IC packages are given in 2.

Table 2. Thermal Resistance Values for Standard I/C Packages

Thermal Resistance In Still Air

Package Description

No. Bod Bod Bod Die Die Area Fla Area.

Leads Style Material W L Bonds

(Sq. Mils)

(Sg. Mils)

14 DIL Epoxy 1/4 3/4 Epoxy 4096 6,400

AIR FLOW device in the system should be eva


43/407

The effect of air flow over the packages on JA (due to adecrease in CA) reduces the temperature rise of thepackage, therefore permitting a corresponding increase in

power dissipation without exceeding the maximum

permissible operating junction temperature.Even though different device types mounted on a printed

circuit board may each have different power dissipations, all

will have the same input and output levels provided that each

is subject to identical air flow and the same ambient air

temperature. This eases design, since the only change in

levels between devices is due to the increase in ambient

temperatures as the air passes over the devices, or

differences in ambient temperature between two devices.

The majority of users employ some form of air-flowcooling. As air passes over each device on a printed circuit

board, it absorbs heat from each package. This heat gradient

from the first package to the last package is a function of the

air flow rate and individual package dissipations. 3 provides

gradient data at power levels of 200 mW, 250 mW, 300 mW,

and 400 mW with an air flow rate of 500 Ifpm. These figures

show the proportionate increase in the junction temperature

of each dual in-line package as the air passes over each

device. For higher rates of air flow the change in junctiontemperature from package to package down the airstream

will be lower due to greater cooling.

3. Thermal Gradient of Junction Temperature

(16-Pin Dual-In-Line Package)

Power Dissipation

(mW)

Junction Temperature Gradient

(C/Package)

200 0.4

250 0.5

300 0.63

400 0.88

Devices mounted on 0.062 PC board with Z axis spacing of 0.5.

Air flow is 500 lfpm along the Z axis.

4 is graphically illustrated in Figure 43 which shows that

the reliability for plastic and ceramic devices is the same

until elevated junction temperatures induce intermetallicfailures in plastic devices. Early and mid-life failure rates of

plastic devices are not effected by this intermetallic

mechanism.

PROCEDURE

junction temperature. Knowing the

temperature, refer to 4 or Equation

determine the continuous operating t

bond failures due to intermetallic fo

system reliability departs from the desin Figure 43.

Air flow is one method of therma

should be considered for system longe

used methods include heat sinks for hi

refrigerated air flow and lower density

CA is entirely dependent on the responsibility of the designer to determ

be achieved by various techniques

modeling, actual measurement, etc.The material presented here emp

consider thermal management as an i

design and also the tools to determin

methods being considered are adeq

desired system reliability.

4. Device Junction Temper

Time to 0.1% Bond F

Junction

Temperature C Time, Hours

80 1,032,200

90 419,300

100 178,700

110 79,600

120 37,000

130 17,800

140 8,900

1

1 10

TIME, YEARS

NORMALIZEDFAILURERATE

T J=90 C

TJ=100

C

TJ=110

C

TJ=130

C

TJ=120C

FAILURE RATE OF PLASTIC = C

UNTIL INTERMETALLICS OCCU

Figure 43 Failure Rate ve

CAPACITIVE LOADING EFFECTS tPT = tP + 0.5 VCC (CL 5


44/407

ON PROPAGATION DELAY

In addition to temperature and powersupply effects,

capacitive loading effects should be taken into account. The

additional propagation delay may be calculated if the shortcircuit current for the device is known. Expected minimum

numbers may be determined from 5.

From the equation

Cdvci =

dt

this approximation follows:

I =

CV

t

so

t =CV

I

or

t =I

C(0.5 VCC)

because the propagation delay is measured to the 50% point

of the output waveform (typically 0.5 VCC).

This equation gives the general form of the additional

propagation delay. To calculate the propagation delay of a

device for a particular load capacitance, CL, the following

equation may be used.

where tPT = total propagation delay

tp = specified propagation d

CL = actual load capacitance

IOS

= short circuit current (5)

An example is given here for tPHL of

150 pF load.

VCC = 4.5 V

tPHL (50 pF) = 18

CL = 150 pF

IOS = 17.3 mA

tPHL (150 pF) = 18 ns + (0.5)(4.5

= 18 ns + 13 ns

= 31 ns

Another example for CL = 0 pF and al

same.

tPHL (0 pF) = 18 ns +(0.5)(4.5 V

1= 18 ns + ( 6.5 ns)

tPHL = 11.5 ns

This method gives the expected pro

intended as a design aid, not as a gua

Table 5. Expected Minimum Short Circuit Currents*

Standard Drivers

Bus Dr

Parameter

VCC

25_C

85_C

125_C

25_C

85_

Output Short Circuit Source Current

2.0

4.5

6.0

1.89

18.5

35.2

1.83

15.0

28.0

1.80

13.4

24.6

3.75

37.0

70.6

3.6

30

56

Output Short Circuit Sink Current

2.0

4.5

6.0

1.55

17.3

33.4

1.55

14.0

26.5

1.55

12.5

23.2

2.45

27.2

52.6

2.4

22

41

*These values are intended as design aids, not as guarantees.

TEMPERATURE EFFECTS ONDC AND AC PARAMETERS

SUPPLY VOLTAGE EFFECCURRENT AND PROPAGA


45/407

DC AND AC PARAMETERS

One of the inherent advantages of CMOS devices is that

characteristics of the N and Pchannel transistors, such as

drive current, channel resistance, propagation delay, andoutput transition time, track each other over a wide

temperature range. Figure 44 shows the temperature

relationships for these parameters. To illustrate the effects of

temperature on noise margin, Figure 45 shows the typical

transfer characteristics for devices with buffered inputs and

outputs. Note that the typical switch point is at 45% of the

supply voltage and is minimally affected by temperature.

The graphs in this section are intended to be design aids,

not guarantees.

50 0 50 100 1500.5

1.0

1.5

TYPICALIOH,tPLH,tPHL,tTLH

THL

C

,t

,R

,

NORMALIZ

EDTO25CVALUE

TA, AMBIENT TEMPERATURE (C)

IOH, IOLRC, tPLH, tPHL, tTLH, tTHL

Figure 44. Characteristics of Drive Current,

Channel Resistance, and AC ParametersOver Temperature

1.0

2.0

3.0

4.0

5.0

Vout,OUTPUT

VOLTAGE(V)

VCC = 5 Vdc

TA = 55C

VIL

TA = 125C

TA = 25C

VIH

CURRENT AND PROPAGA

The transconductive gain, lout/V

proportional to the gate voltage minus

VG VT. The gate voltage at the inpbuffered devices is approximately the

VCC or GND. Because VG = VCC or

current is proportional to the supply

delays for CMOS devices are also a

supply voltage, because most of the de

and discharging internal capacitan

Figure 47 show the typical variation

propagation delay, normalized to VC

VCCv

6.0 V. These curves may be ueach data sheet to arrive at paramvoltage range.

2.0 3.0 4.00.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

(NORMALIZEDTO4.5

VNUMBER)

IOH,

IOL,

TYPICALOUTP

UTDRIVECURRENT

VCC, POWER SUPPLY V

Figure 46. Drive Current v

1.0

2.0

3.0

ORMALIZEDTO4.5

V

NUMBER)

HL,

TYPICALPROPAG

ATIONDELAY

DECOUPLING CAPACITORSu

t


46/407

The switching waveforms shown in Figure 48 and

Figure 49 show the current spikes introduced to the power

supply and ground lines. This effect is shown for a load

capacitance of less than 5 pF and for 50 pF. For ideal powersupply lines with no series impedance, the spikes would

pose no problem. However, actual power supply and ground

lines do possess series impedance, giving rise to noise

problems. For this reason, care should be taken in board

layouts, ensuring low impedance paths to and from logic

devices.

To absorb switching spikes, the following HSCMOS

devices should be bypassed with good quality 0.022 F to

0.1 F decoupling capacitors:1. Bypass every device driving a bus with all outputs

switching simultaneously.

2. Bypass all synchronous counters.

3. Bypass devices used as oscillator elements.

4. Bypass Schmitttrigger devices with slow input rise

and fall times. The slower the rise and fall time, the

larger the bypass capacitor. Lab experimentation is

suggested.

Bypass capacitors should be distributed over the circuitboard. In addition, boards could be decoupled with a 1 Fcapacitor.

BUFFERED DEVICE: INPUT tr, tf

IGND

ICC

Vou

Figure 48. Switching Current

BUFFERED DEVICE: INPUT tr, tf

IGND

ICC

Vout

Figure

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