Emerging Research Devices...5ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 2005 ITRS ERD Chapter Emerging Research Memory Devices Bi-stable switch M-I-M (nc)-I-M

1 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007

ITRS Public Conference

Emerging Research DevicesMakuhari, Japan

December 5, 2007

Jim Hutchby – SRC


Hiroyuki Akinaga AISTTetsuya Asai Hokkaido U.Yuji Awano FujitsuGeorge Bourianoff Intel/SRCMichel Brillouet CEA/LETIJoe Brewer U. FloridaJohn Carruthers PSURalph Cavin SRCU-In Chung SamsungPhilippe Coronel ST MeErik DeBenedictis SNLSimon Deleonibus LETIKristin De Meyer IMECMike Forshaw UC LondonMichael Frank AMDChristian Gamrat CEAMike Garner IntelDan Hammerstrom PSUShigenori Hayashi MatsushitaToshiro Hiramoto U. TokyoDan Herr SRCMutsuo Hidaka ISTEKJim Hutchby SRCYasuo Inoue Renesas TechAdrian Ionescu ETHKohei Itoh Keio U.Seiichiro Kawamura SeleteRick Kiehl U. MinnTsu-Jae King Liu U. C. BerkeleyHiroshi Kotaki SharpNety Krishna AMATZoran Krivokapic AMD

Phil Kuekes HPLou Lome IDAHiroshi Mizuta U. SouthamptonMurali Ramachandran FreescaleFumiyuki Nihey NEC Dmitri Nikonov Intel Wei-Xin Ni NDLTak Ning IBMKwok Ng SRCLothar Risch InfineonDave Roberts Air ProductsKaushal Singh AMATKentaro Shibahara Hiroshima U.Sadas Shankar IntelThomas Skotnicki ST MeSatoshi Sugahara Tokyo TechShin-ichi Takagi U. TokyoLuan Tran MicronKen Uchida ToshibaYasuo Wada Waseda U.Rainer Waser RWTH AFrans Widdershoven NXPJeff Welser NRI/IBMPhilip Wong Stanford U.Kojiro Yagami SonyDavid Yeh SRC/TIIn-Seok Yeo SamsungMakoto Yoshimi SOITECIn-K Yoo SAITPeter Zeitzoff FreescaleYuegang Zhang IntelVictor Zhirnov SRC

Emerging Research Devices Working Group


Highlights of Changes Scope of ERD Chapter

Invent the new “switch” – Emerging information processing* devices to eventually replace CMOS Boolean logicSupplement Si CMOS – Use the physics of emerging research devices to realize complex typically nonlinear functions in an accelerator-like fashion

Perform certain functions more efficiently than digital CMOSEventually extend CMOS and nanoelectronics to address new applications

Spin off a new chapter on Emerging Research MaterialsExpand the Emerging Architecture SectionExpand scope of the Emerging Logic Section – supplement CMOS

Example: Image Processing using emerging research devices integrated on a CMOS Platform.

Update the Emerging Memory Section

*ERD Chapter includes the following elements of Information Processing: Data processing, storage and communication.

4 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007year

Beyond CMOS

Elements

ERD-WG in Japan

Existing technologies

New technologies

Evolution of Extended CMOS


2005 ITRS ERD ChapterEmerging Research Memory Devices

Bi-stable switch

M-I-M (nc)-I-M

1 M-I-M 2 Solid Electrolyte3 FE tunneling 4 FE Schottky diode5 FE-I-FE

FET with FE gate insulator

Graded insulator

1Nanocrystal2 Direct tunneling

Device Types

1T1R or 1R1T1R or 1R1T1R or 1R1T1T1TCell Elements

Not knownNot knownMultiple mechanisms

Remanentpolarization

on a ferroelectric

gate dielectric

Charge on floating

gateCharge on floating gate

Storage Mechanism

Molecular Memories

PolymerMemory

Insulator Resistance

Change Memory

Ferroelectric FET

Memory

Engineered tunnel barrier

Memory

Nano-floating Gate

Memory

Bi-stable switch

M-I-M (nc)-I-M

1 M-I-M 2 Solid Electrolyte3 FE tunneling 4 FE Schottky diode5 FE-I-FE


Graded insulator

1Nanocrystal2 Direct tunneling

Device Types

1T1R or 1R1T1R or 1R1T1R or 1R1T1T1TCell Elements

Not knownNot knownMultiple mechanisms

Remanentpolarization

on a ferroelectric

gate dielectric

Charge on floating

gateCharge on floating gate

Storage Mechanism

Molecular Memories

PolymerMemory

Insulator Resistance

Change Memory

Ferroelectric FET

Memory


Memory

Nano-floating Gate

Memory

Expand

OUT

Capacitance-based Resistance-based


New device concept, promising characteristics, several

recent publicationsINNano-mechanical

memory

Replacement for the Insulator resistance change memoryINElectronic Effects

Memory

Replacement for the Insulator resistance change memoryINIonic Memory

Replacement for the Insulator resistance change memoryINFuse/Antifuse

Memory

This memory category included several different memory types

based on different mechanisms of operation

Replaced by three new memory categories (see below)OUT

Insulator Resistance Change Memory

ERD recommends to include NFLG memory in PIDS

(Not included in 2007PIDS chapter)

Natural evolution of FG FLASH. No outstanding research issues -became a prototypical technology

OUTNanofloating gate memory

CommentReason for IN/OUTIN/OUT

New device concept, promising characteristics, several

recent publicationsINNano-mechanical

memory

Replacement for the Insulator resistance change memoryINElectronic Effects

Memory

Replacement for the Insulator resistance change memoryINIonic Memory

Replacement for the Insulator resistance change memoryINFuse/Antifuse

Memory

This memory category included several different memory types

based on different mechanisms of operation

Replaced by three new memory categories (see below)OUT

Insulator Resistance Change Memory

ERD recommends to include NFLG memory in PIDS

(Not included in 2007PIDS chapter)

Natural evolution of FG FLASH. No outstanding research issues -became a prototypical technology

OUTNanofloating gate memory

CommentReason for IN/OUTIN/OUT

2007 ITRS ERD ChapterTransition Table for Emerging Memory Devices


2007 ITRS ERD ChapterCapacitance-based memory technologies


Graded insulatorDevice Types

1T1TCell Elements

Remnant polarization on a ferroelectric gate

dielectric

Charge on floating gate

Storage Mechanism

Ferroelectric FET Memory


Memory


2007 ITRS ERD ChapterResistance-based memory technologies

Bi-stable switch

M-I-M (nc)-I-M

1) Charge trapping2) Mott transition3) FE Barrier effects

1) Solid Electrolyte 2) RedOxreaction

M -I-M e.g.

Pt/NiO/PtCNT bridgeCNT cantileverSi cantilever Nanoparticle

Device Types

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R1T1R or 1D1RCell Elements

Not knownNot known

Multiple mechanisms

Ion transport in solids

Multiple mechanisms

Electrostatically-controlled bi-

stable mechanical

switch

Storage Mechanism

Molecular Memories

PolymerMemory

Electronic effects

Memory

Ionic Memory

Fuse/Antifuse

Memory

Nanomechanical memory

Bi-stable switch

M-I-M (nc)-I-M

1) Charge trapping2) Mott transition3) FE Barrier effects

1) Solid Electrolyte 2) RedOxreaction

M -I-M e.g.

Pt/NiO/PtCNT bridgeCNT cantileverSi cantilever Nanoparticle

Device Types

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R

1T1R or 1D1R1T1R or 1D1RCell Elements

Not knownNot known

Multiple mechanisms

Ion transport in solids

Multiple mechanisms

Electrostatically-controlled bi-

stable mechanical

switch

Storage Mechanism

Molecular Memories

PolymerMemory

Electronic effects

Memory

Ionic Memory

Fuse/Antifuse

Memory

Nanomechanical memory


2.52.72.72.22.02.22.32.4

2.42.32.42.02.12.32.22.3Electron Injection Memory

2.22.22.91.92.52.41.91.7Nano Mechanical Memory

2.52.72.81.82.22.01.92.6Fuse/Anti-fuse Memory

Engineered Tunnel Barrier Memory

CMOS Architectural Compatibility

CMOS Technological Compatibility

Operate Temperature

Operational Reliability

Off/On ratio

Energy EfficiencyPerformanceScalability

3

2

1

3

2

1

3

2

1

3

2

1

Critical EvaluationMemory

For each Technology Entry (e.g. 1D Structures), sum horizontally over the 8 CriteriaMax Sum = 24Min Sum = 8

> 20

>18 - 20 < 16

>16 - 18


2.52.12.51.72.12.42.02.6

1.91.82.21.31.42.41.72.4Molecular Memory

2.31.92.21.41.82.11.82.1Macromolecular Memory

2.32.32.61.72.11.92.01.8Ferroelectric FET Memory

Ionic Memory



Operate Temperature

Operational Reliability

Off/On ratio

Energy EfficiencyPerformanceScalability

3

2

1

3

2

1

3

2

1

3

2

1

Critical EvaluationMemory


> 20

>18 - 20 < 16

>16 - 18


2005 ITRS ERDEmerging Research Logic Devices

Device

FET [B] 1D structures Resonant Tunneling Devices SET Molecular Ferromagnetic

logic Spin transistor

Types Si CMOS

CNT FETNW FET

NW hetero-structuresCrossbar

nanostructure

RTD-FETRTT

SET

Crossbar latchMolecular transistor

Molecular QCA

Moving domain wall

M: QCASpin transistor

Supported Architectures Conventional Conventionaland Cross-bar

Conventionaland CNN CNN Cross- bar and

QCA

CNNReconfigure

logic andQCA

Conventional

Expand

Transition


Transition Table for Emerging Logic Devices IN/OUT Reason for IN/OUT Comment

Rapid Single Flux Quanta OUT

RSFQ devices, systems and circuits have been developed,

prototyped, and fabricated. They could become an

important technology if the correct market driver emerges

Design and fabrication lines for RSFQ systems exist.

Cryogenic operation, cost and material integration

issues limit application space

CMOS extension- IN Low bandgap, compound III-V

materials can potentially improve transistor

performance

Research on compound III –V materials on SI substrates has increased significantly

over the last 2 years

Impact Ionization MOS IN (pending)

Simulation results showing very low sub threshold slopes

indicate potential for low power operation

May be included in future editions

Lateral interband tunneling transistor

IN (pending) Potential to utilize gate

modulated interband tunneling to reduce subthreshold slope


Floating gate MOS devices IN (pending)

Devices with nanocrystals embedded in gate allow circuits with tuneable

thresholds. Potential for low power circuits


Nano Electro Mechanical Systems

IN (pending) Potential for ultra low leakage device based on nano relay

operation



2007 ITRS ERDCMOS Scaling & Replacement Devices (1st)

conventionalLithographically defined

Memory-basedQCA

Threshold logic

ConventionalConventionalConventionalSupported Architectures

•Spin Gain transistor•HMF Spin MOSFET•Spin Torque Transistor

•Moving domain wall•Hybrid Hall effect•Magnetic Resistive Element •M: QCA

•2-terminal•3-terminal FET•3-terminal bipolar transistor•NEMS •Molecular QCA

SET•III-V compound semiconductor channel replacement

•CNT FET•NW FET•NW hetero-structures•Nanoribbon transistors

Si CMOSTypes

Spin transistor

Ferromagnetic logic

MolecularSETCMOS Extension

III-V channel

replacement

CMOS Extension

Low dimensional structures

FET

Device


2.31.82.52.02.32.52.22.4

1.71.61.81.31.52.21.52.5Molecular Devices

1.51.61.41.31.22.31.12.4Single Electron Transistors

2.51.82.31.92.42.32.92.0Channel Replacement Materials

1D Structure


CMOS TechnologicalCompatibility

Operate Temperature

Operational ReliabilityGainEnergy

EfficiencyPerformanceScalability

3

2

1

3

2

1

3

2

1

3

2

1

Critical EvaluationLogic


> 20

>18 - 20 < 16

>16 - 18


1.31.22.12.01.51.71.31.2

1.31.31.31.41.72.31.41.7Spin Transistor

Ferromagnetic Devices



Operate Temperature

Operational ReliabilityGainEnergy

EfficiencyPerformanceScalability

3

2

1

3

2

1

Critical EvaluationLogic


> 20

>18 - 20 < 16

>16 - 18


Logic Device Conclusions

Continued analysis of alternative technology entries likely will continue to yield the same result:

Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels

Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates


Supplementing CMOS

General Purpose Processor

Basis of Existing Assessments of Logic Devices

A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization

SOC-PE Architecture

PEMainProc.

MainMemory

Peripherals

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE PE

Function A Function B Function C

Function D Function E

Multi-Core/Accelerator Engine Platform (SOC-MC/AE Architecture)

Multi-Cores

Accelerator Engine

Accelerator Engine

Accelerator Engine

Accelerator Engine

On-Demand Acceleration

Hi Speed Hi Speed Hi Speed

Connectivity

L3 Cache

Non-Blocking Switch Fabric

Memory Control

System Functions

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

SOC-PE Architecture

PEMainProc.

MainMemory

Peripherals

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE PE



SOC-PE Architecture

PEMainProc.

MainMemory

Peripherals

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

PE PE




Multi-Cores

Accelerator Engine

Accelerator Engine

Accelerator Engine

Accelerator Engine



Connectivity

L3 Cache


Memory Control

System Functions

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache


Multi-Cores

Accelerator Engine

Accelerator Engine

Accelerator Engine

Accelerator Engine



Connectivity

L3 Cache


Memory Control

System Functions

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Multi-Core

L2 Cache

Courtesy Fawzi Behmann - Freescale


2007 ITRS ERDCMOS Supplement Devices (2nd)

Device Resonant tunneling diodes

Muti ferroic tunnel junctions

Single Electron Transistors

Molecular devices

Ferro-magnetic devices

Frequency coherent

spin devices

State variable

Charge Dielectric and magnetic domain polarization

Charge Molecular Conformation

Ferromagnetic polarization

Precession frequency

Response function

Negative differential resistance

Four resistive states

Coulomb blockade

Hysteritic Non-linear Nonlinear

Emerging Research Architectures

CMOL – ‘Molecule on CMOS’ architectureCNN – Cellular Nonlinear NetworkAMP – Associative Memory Processor

GPP – General Purpose ProcessorFG-MOS – Floating Gate MOS devicesSET – single electron transistor

RecognitionMiningSynthesis

MixedMFDT,Spin-gain transistorBio-inspired

Recognition/VisionIrregular/FixedFG-FET, SETAMP

Recognition/VisionRegular/FlexibleCMOS+SensorsCNN

Morphic

Synthesis/GPPIrregular/Fixed

CMOS+Ferromagnetic logicCheck-point

Synthesis/GPPRegular/FlexibleMolecular SwitchesMolecular

Cross-bar

Synthesis/GPPIrregular/Fixed

CMOS+MolecularSwitchesCMOL

Synthesis/GPPIrregular/FixedCMOSAsymmetric

cores

Heterogeneous

Synthesis/GPPIrregular/FixedCMOSSymmetric coresHomogeneous

Many-Core

Research ActivityApplicationNetworkComputational

ElementsImplementationArchitecture

MFTD – multiferroic tunnel diode


Image recognitionSpeech recognition DSP (cross correlation)Data Mining OptimizationPhysical simulationSensory data processing (biological, physical)Image creationCryptographic analysis

Potential Supplemental Applications

Illustrative Example


Top down information processing Image Recognition

Tadashi Shibata, University of Tokyo


Specialized devices for image recognition

Heterogate ferroelectric FGMOS FETTadashi Shibata, University of Tokyo


Image recognition

Tadashi Shibata, University of Tokyo


SummaryScope: Broaden scope to encourage emerging technologies both to supplement CMOS as well as eventually to invent the new “switch”.Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials.Memory Section: Added NEMS mechanical memory to section. – Divide Emerging Memory Tables into Resistive and Capacitive

subcategories– Updated section in 2007.

Logic Section: Reformulated Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function.

– Re-considered status of candidate Technology Entries.– Re-structured Logic Section.

Architecture Section: Revised section to focus on encouraging research to explore optimal organization of emerging non-linear devices to efficiently realize accelerator-like functions to supplement the CMOS platform technology.

Documents

Emerging Research Devices...5ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 2005 ITRS ERD Chapter Emerging Research Memory Devices Bi-stable switch M-I-M (nc)-I-M