ES ZC261-L5

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BITS PilaniPilani Campus

DIGITAL ELECTRONICS

AND MICROPROCESSORRekha.A

Faculty

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BITS Pilani, Pilani Campus

Full Subtractor

Block diagram of full subtractor Truth table of full subtractor

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K-Map for Full Subtractor

1 1

1 1

x

yz

00 01 11 10

0

1

D= xyz + xyz + xyz+ xyz

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K-Map for Borrow of full subtractor

1 1 1

1

x

yz00 01 11 10

0

1

B = xz+xy+yz

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Implementation of full subtractor

B

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Four bit binary Adder-Subtractor

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Comparators

Comparators are designed to compare the magnitude of two binary

numbers and indicate whether one is greater than, less than or

equal to the other.

One bit comparator

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Implementation of one bit comparator

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Two bit comparator

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Truth table of 2 bit comparator

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Decoders

Discrete quantities of information are represented in digital systemsby binary codes

A decoder is a combinational circuit that converts the binaryinformation from n input lines to a maximum of 2n output lines.

A decoder is a device which when activated , selects one of itspossible 2n outputs based on its n bit digit.

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General representation of a decoder

12ESZC261:Digital Electronics and Microprocessor

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2 to 4 Decoder


Y0

Y1

Y2

Y3

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Dual 2 to 4 line Decoder


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Implement with a suitable decoder with active low enable input for the

function f(w,x,y,z) = (3,7,9)


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Implement the function with a suitable decoder

F = (0,1,3,5,6 )

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4 to 16 decoder constructed as 3 to 8 decoder

W X Y Z

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 00 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 01 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


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Implementation of a Full adder with a decoder

S= (1,2,4,7)

C=(3,5,6,7)


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ENCODERS

Decoders accept an input code and produce a HIGH(or LOW) at

one output line.Decoder identifies, recognise or detects a particular

code

An encoder has a number of input lines , only one of which is

activated at a given time and produces an n-bit output code,

depending on which input is activated.

An Encoder has 2n(or fewer) input lines and n output lines.

The output lines as an aggregate, generate the binary code

corresponding to the input value.


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A General Block Diagram of an Encoder


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Truth Table of a 8 to 3 line Encoder( Decimal to BCD)


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Priority Encoder

A priority encoder is an encoder circuit that includes the priority

function.

When more than one inputs are equal to 1 at the same time, the

input having the highest priority will take precedence.

In addition to the outputs, the circuit has the output designated as V

which is the valid bit.

Valid bit indicator is set to 1 when one or more inputs are equal to 1.


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Truth Table of 8 to 3 line priority Encoder


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K Map for the outputs

X2X3 X2X3

1 1 1

1 1 1

1 1 1

1 1 1

1 1

1 1 1

1 1 1

1 1

X0 X1

00

01

11

10

00 01 11 10 00 01 11 10

00

01

11

10

y1 = x2 + x3 y0 = x3+ x1x2

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A multiplexer is a combinational circuit that selects binary information

from one of the many input lines and directs it to a single output line.

The selection of a particular input line is controlled by a set of selectionlines.

2n input lines , n select lines whose bit combinations determine which

input is selected.


MULTIPLEXER

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Block Diagram of a two to one line multiplexer

When S=0, Io is selected

When S=1, I1 is selected


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Logic Diagram of a Two-to-One line multiplexer


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Four to one line multiplexer

Function Table

Implementation of 4 to 1 Mux


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16 to 1 MUX configured using 4 to 1 MUX


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Implement the following function using a 8 to 1 MUX

f(a,b,c) = (0,4,5,6)


Boolean Function Implementation

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Implement the following Boolean function using 4 to 1 MUX

F(x,y,z) = (1,2,6,7)


Documents

ES ZC261-L5