Giao Trinh Ghep Noi May Tinh

7/31/2019 Giao Trinh Ghep Noi May Tinh

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Bi ging mn hc: K thut ghp ni my tnh

Bi m u 3Chng 1i cng v k thut ghp ni my tnh...........................................................4

1.1Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi.....................................................4

1.1.1.Yu cu trao i tin vi ngi iu hnh......................................................................................41.1.2.Yu cu trao i tin vi thit b ngoi thng dng........................................................................41.1.3.Yu cu trao i tin trong mng my tnh.....................................................................................4

1.2Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN)...............................................41.2.1.Dng tin (s)...................................................................................................................................41.2.2.Cc loi tin.....................................................................................................................................5

1.3Vai tr nhim v v chc nng ca khi ghp ni (KGN)...................................................................51.3.1.Vai tr.............................................................................................................................................51.3.2.Nhim v........................................................................................................................................61.3.3.Chc nng......................................................................................................................................7

1.4Cu trc chung ca mt khi ghp ni..................................................................................................7

1.5Chng trnh phc v trao i tin cho khi ghp ni...........................................................................8Chng 2Giao tip vi tn hiu tng t.........................................................................102.1Khi nim tn hiu analog v h o lng iu khin s....................................................................102.2Chuyn i tn hiu s sang tng t DACs.......................................................................................10

2.2.1.Cc tham s chnh ca mt DAC ..........................................................................112.2.2.DAC chia in tr (Resistive Divider DACs).............................................................................112.2.3.DAC trng s nh phn (Binary Weighted DACs).....................................................................122.2.4.DAC iu bin rng xung (PWM DACs).............................................................................13

2.3Chuyn i tn hiu tng t - s ADCs: ...........................................................................................132.3.1.Cc tham s chnh ca mt ADC................................................................................................14

Chng 3Th tc trao i tin ca my vi tnh.................................................................15

3.1Cc ch trao i tin ca my vi tnh...............................................................................................153.2Trao i tin ngt vi x l.....................................................................................................................163.2.1.Cc loi ngt ca my vi tnh PC................................................................................................163.2.2.X l ngt cng trong IBM - PC:................................................................................................193.2.3.Lp trnh x l ngt cng:...........................................................................................................22

3.3Trao i tin trc tip khi nh.............................................................................................................253.3.1.C ch hot ng:........................................................................................................................253.3.2.Hot ng ca DMAC:................................................................................................................253.3.3.Chip iu khin truy nhp b nh trc tip DMAC 8237 (Direct Memory Access Controller)

26Chng 4Rnh cm m rng...........................................................................................32

4.1t vn .............................................................................................................................................324.2Bus PC..................................................................................................................................................324.3Bus ISA (16 bit)...................................................................................................................................334.4Bus PCI.................................................................................................................................................334.5Ghp ni qua khe cm m rng...........................................................................................................34

4.5.1.Mt s c im ca Card ISA....................................................................................................344.5.2.Gii m a ch v kt ni Bus d liu........................................................................................34

5.1Khi ghp ni song song n gin......................................................................................................365.2Cc vi mch m, cht (74LS245, 74LS373).....................................................................................37

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5.2.1.Vi mch m 74LS245:...............................................................................................................375.2.2.Vi mch cht 74LS373:...............................................................................................................37

5.3Vi mch PPI 8255A.............................................................................................................................385.3.1.Gii thiu chung...........................................................................................................................385.3.2.Cc lnh ghi v c cc cng v cc thanh ghi iu khin.........................................................405.3.3.Cc t iu khin.........................................................................................................................405.3.4.Ghp ni 8255A vi MVT v TBN.............................................................................................43

5.4Ghp ni song song qua cng my in..................................................................................................485.4.1.Ghi thiu chung..........................................................................................................................485.4.2.Cu trc cng my in...................................................................................................................495.4.3.Cc thanh ghi ca cng my in:...................................................................................................515.4.4.EPP - Enhanced Parallel Port.......................................................................................................53

6.1t vn .............................................................................................................................................596.2Yu cu v th tc trao i tin ni tip:..............................................................................................59

6.2.1.Yu cu: .......................................................................................................................................596.2.2.Trao i tin ng b: Synchronous.............................................................................................606.2.3.Trao i tin khng ng b - Asynchronous:.............................................................................60

6.3Truyn thng ni tip s dng giao din RS-232:...............................................................................61

6.3.1.Qu trnh truyn mt byte d liu:..............................................................................................616.3.2.Cng ni tip RS 232...................................................................................................................62

Ti liu tham kho:...........................................................................................................79

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Bi m u

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Chng 1: i cng v k thut ghp ni my tnh

Chng 1 i cng v k thut ghp ni my tnh

1.1 Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi

1.1.1. Yu cu trao i tin vi ngi iu hnh

Ngi iu hnh (ngi s dng) my vi tnh (MVT) cn a lnh (di dng ch) v s liuthng qua bn phm. Khi ngi iu hnh bm vo cc phm ca bn phm nhng m c to rav c truyn vo b nh ca MVT v ng thi hin th ln mn hnh cc ch v con s bm.

1.1.2. Yu cu trao i tin vi thit b ngoi thng dng

Cc thit b a tin vo

Cc thit b a tin ra

Cc b nh ngoi

Yu cu trao i tin vi thit b ngoi khc

Trong h o vt l, MVT cn nhn cc tin vt l( nhit , p xut, lc, dng in, vv ) didng tn hiu in thng qua du d b pht hin (detector ), cm bin (sensor ), b chuyn i(tranducer ). Hn na MVT cn nhn cc tin v trng thi sn sng hay bn ca cc thit b o.Trong h o - iu khin, MVT cn:

Nhn tin v s liu o, v trng thi thit b o

a tin v s chp nhn trao i tin vi thit b ngoi, v lnh iu khin cc c cu chp

hnh (Cc ng c servo, cc van ng m, cc thit b ng ngt mch in, vv ) v ccthng s k thut cho thit b.

Trong cc h lu tr v biu din tin, MVT cn a tin ra :

Lu tr trn bng t, a t, bng giy v a compac

Biu din kt qu o di dng bng s liu, dng th trn giy ca my v hay trnmn hnh ca thit b u cui.

1.1.3. Yu cu trao i tin trong mng my tnh

Mt my tnh trong mng cn trao i tin vi nhiu ngi s dng mng, vi nhiu my vitnh khc, vi nhiu thit b ngoi nh: cc thit b u cui, cc thit b nh ngoi, cc thit blu tr v biu din tin.

1.2 Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN)

1.2.1. Dng tin (s)MVT ch trao i tin di dng s vi cc mc logic 0 v 1

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Chng 1: i cng v k thut ghp ni my tnhThit b ngoi li trao i tin vi nhiu dng khc nhau nh dng s, dng k t, dng tng t, dng mtn hnh sin tun hon

1.2.2. Cc loi tin

MVT a ra thit b ngoi mt trong 3 loi tin:

Tin v a ch: l cc tin ca a ch TBN hay chnh xc hn, l a ch thanh ghi m

ca khi ghp ni i din cho TBN Tin v lnh iu khin: l cc tn hiu iu khin khi ghp ni hay TBN nh ng

m thit b, c hoc ghi mt thanh ghi, cho php hay tr li yu cu hnh ng, vv

Tin v s liu: l cc s liu cn a ra cho thit b ngoi

My tnh nhn tin vo t TBN v mt trong hai loi tin:

Tin v trng thi ca TBN: l tin v s sn sng hay yu cu trao i tin, v trng thisai li ca TBN

Tin v s liu: l cc s liu cn a vo MVT

1.3 Vai tr nhim v v chc nng ca khi ghp ni (KGN)

1.3.1. Vai tr

Khi ghp ni nm gia MVT v TBN ng vai tr bin i v trung chuyn tin gia chng

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1.3.2. Nhim v

Phi hp v mc v cng sut tn hiu

- Mc tn hiu ca MVT thng l mc TTL (0V 5V) trong khi TBN c nhiu mc khc nhau,thng thng cao hn ( 15V, 48V)- Cng sut ng dy MVT nh, TBN ln- Thng dng cc vi mch 3 trng thi

Phi hp v dng tin:

Trao i tin ca MVT thng l song song, cua TBN i khi l ni tip

Phi hp v tc trao i tin

Phi hp v phng thc trao i tin

m bo trao i tin mt cch tin cy gia MVT v TBN, cn c KGN v cch trao itin din ra theo trnh t nht nh.

Vic trao i tin do my tnh khi xng(1) MVT a lnh d khi ng TBN hay khi ng KGN(2) MVT c tr li sn sng trao i hay trng thi sn sng ca TBN. Nu c trng thi

sn sng mi trao i tin, nu khng, ch v c li trng thi(3) MVT trao i khi c thy trng thi sn sng

Ngunpht

MVT

Ngunnhn

Ngunnhn

TBN

Ngunpht

Ngunpht

Ngunnhn

Ngunnhn

Ngunpht

Ghp ni ngdy MVT

Ghp ni ngdy TBN

V tr v vai tr ca khi ghp ni

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Vic trao i tin do TBN khi xng:(1) gim thi gian ch i trng thi sn sng ca TBN, MVT c th khi ng

TBN ri thc hin nhim v khc. Vic trao i tin din ra khi:(2) TBN a yu cu trao i tin vo b phn x l ngt ca KGN, a yu cu ngt

chng trnh cho MVT(3) Nu c nhiu TBN a yu cu ng thi, KGN sp xp theo u tin nh sn, ri

a yu cu trao i tin cho MVT(4) MVT nhn yu cu , sa son trao i v a tn hiu xc nhn sn sng trao i(5) KGN nhn v truyn tn hiu xc nhn cho TBN(6) TBN trao i tin vi KGN v KGN trao i tin vi MVT (nu a tin vo)(7) MVT trao i tin vi TBN qua KGN (nu a tin ra)

1.3.3. Chc nng Chc nng nhn tn hiu ( listener)

- Nhn thng bo a ch t MVT

- Nhn thng bo trng thi t TBN- Nhn lnh iu khin t MVT- Nhn s liu t MVT Chc nng ngun tn hiu (talker)

- Pht a ch cho khi chc nng ca TBn- Pht lnh cho TBN- Pht yu cu hay trng thi ca TBN cho MVT- Pht s liu cho TBN hay cho MVT Chc nng iu khin (Controler)

Ni chung KGN thng c ng thi hai chc nng trn, c bit khi ghp ni vi nhiu TBN

Cu trc chung ca mt h ghp ni my tnhCu trc ng dy ca KGN vi MVTBt c KGN no cng ni vi MVT v TBN theo cc nhm sau Nhm ng dy a ch A0 - An- Cc tn hiu ny c gii m trong cc KGN chn cc TBN cn lin lc vi MVT- Tp hp cc tn hiu ny to thnh bus a ch (address bus) Nhm ng dy lnh- ng dy c, ng dy vit truyn lnh c (RD) hay vit cho KGN.- ng dy hi thoi t chc phi h hnh ng gia MVT v KGN, m bo s hot ng nhp

nhng, tin cy gia chng nh:Hi - tr liYu cu (t KGN vo MVT) v chp nhn (t MVT ra KGN) : yu cu ngt INTR v chp

nhn ngt INTA- ng dy lnh iu khin KGN hay TBN Nhm ng dy nhp thi gian Nhm ng dy in p ngun

1.4 Cu trc chung ca mt khi ghp ni

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Khi phi hp ng dy MVT- Phi hp mc v cng sut tn hiu vi bus MVT. Thng dng vi mch chuyn mc, vi mch

cng sut- C lp ng dy khi khng c trao i tin Khi gii m a ch - lnh: Nhn cc tn hiu t bus a ch, cc tn hiu c, ghi, cht a ch

(ALE), t hp thnh cc tn hiu c, ghi v chn chp cho tng thit b ca KGN v TBN. Cc thanh ghi m- Thanh ghi iu khin ch - Thanh ghi trng thi hay yu cu trao i cuatr TBN- Thanh ghi m s liu ghi- Thanh ghi m s liu c Khi x l ngt- Ghi nhn, che chn yu cu trao i tin ca TBN. X l u tin v a yu cu vo MVT

Khi pht nhp thi gian- Pht nhp thi gian cho hnh ng bn trong KGN hay cho TBN. i khi ng b, khi cn

nhn tn hiu nhp ng h (clock) t bus my tnh Khi m thit b ngoi- Bin i mc tn hiu, cng sut v bin i dng tin Khi iu khin : iu khin hot ng ca khi nh pht nhp thi gian, ch hot ng

1.5 Chng trnh phc v trao i tin cho khi ghp ni

X l ngt

Thanh ghitrng thi

Thanh ghiiu khin

Thanh ghim c

Thanh ghi

m vit

Gii ma ch -

lnh

LnhcLnhvit

A0

- Ann

WR

DO0

- DOn

DI0

- DIn

Phihpngdym

ytnh

Phihp

ngdythitbngo

i

Lnh c

Lnh vit

Lnh vit

Lnh c

DI0

- DIn

DO0

- DOn

iu khin A

iu khin B

Yu cu A

Yu cu B

cmngtn

WR

Yu cu (INTR)

Xc nhn (INTA)

ngdym

ytnh(Syst e

m

bu

s)

ngdythitbngo

i

S khi khi ghp ni

Cc lnhchn chp

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Mi khi ghp ni cn c mt chng trnh phc v trao i tin ( thng thng vit bngAssembly) v khi s dng, ngi dng cn vit chng trnh ng dng.

Vi chng trnh phc v trao i tin, cn c cc thao tc sau:

Khi ng KGN

Ghi che chn v cho php ngt

c trng thi TBN

Ghi s liu ra

c tin s liu

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Chng 2 Giao tip vi tn hiu tng t

2.1 Khi nim tn hiu analog v h o lng iu khin s

Vic s dng phng php s trong x l thng tin v iu khin ang ngy cng hiu qu vthun li. Tuy nhin hu ht cc tn hiu trong th gii thc li l tn hiu dng tng t

(analog). Do bt k h thng no mun x l cc tn hiu thc t bng phng php s th nphi c kh nng chuyn i cc thng tin tng t thnh dng s v ngc li. Thao tc thng c thc hin bng cc thit b ADC (Analog to Digital Converter) v DAC (Digital toAnalog Converter).

Hnh 2.1: M hnh h thng x l tn hiu tng t bng phng php s

H thng x l tn hiu tng t bng phng php s ni chung l mt h lai, trong sliu tng t s c truyn, lu tr , hay x l bng phng php s nh cc b vi x l s.TRc khi s l, tn hiu tng t phi c chuyn thnh tn hiu s nh b chuyn i tn hiu

tng t sang s (ADC). Kt qu ca php x l s c chuyn ngc li thnh dng tng tnh b chuyn i tn hiu s thnh tng t (DAC).

2.2 Chuyn i tn hiu s sang tng t DACs

Mt b chuyn i tn hiu s thnh tng t DAC lmt dng c bit ca mt b gii m. N gii m tn hius u vo v chuyn thnh tn hiu tng t u ra.Bng chn l ca n c th c dng nh sau:

Hnh 2.2: Bng gi tr chn l ca mt DAC

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Chng 2: Giao tip tn hiu tng t

2.2.1. Cc tham s chnh ca mt DACTham s n v Gii thch

phn gii(revolution)

Bit

y l s bit m DAC x l. Nu DAC c n bit th gi tr in p ura c th phn thnh n trng thi c gi tr cch u nhau. Mi gi trtng ng vi mt m s u vo. S bit n cng cao th DAC c

phn gii cng lnGii in p tham chiu(Vref) FSR

VCh ra mc in p ln nht v nh nht c th c s dng nhin p tham chiu t bn ngoi

Sai s phn cc imkhng

mVL lch gia in p tng t u ra thc t vi u ra l tng0V khi u m b hai vo l 0 c a vo thanh ghi u vo

phi tuyn vi phn(Non-Linearity,Differential - DNL)

LSB hay%Vref

L chnh lch gia thay i gi tr ip p ra thc t vi thay i in p ra l tng trong trng hp u vo s thay imt bit LSB , hay d thay i gia hai gi tr s k nhauVD: +/- 1 LSB; +/- 0.001% FSR

phi tuyn tch phn(Non-Linearity, Integral- INL) hay chnh xctng i (RelativeAccuracy)

LSBL sai s ln nht gia u ra vi ng thng ni gia im 0 vim ton thang (gi tr ln nht ca thang o) ngoi tr sai s imkhng v sai s ton thangVD: +/-1 LSB typ.; +/- 4 LSB's max.

Gii u ra tng thay gii ton thangAnalog Output Rangeor Full-Scale Range

VL chnh lch gia gi tr tng t ln nht v nh nht m DACc th cung cpVD: -3V to +3V, Bipolar Mode

Mc in p logic caou voLogic Input Voltage,Vih (Logic "1")

VL in p nh nht ca tn hiu s u vo DAC m bo c nhnl mc logic 1

VD: 2.4 V min.

Logic Input Voltage,Vil (Logic "0")

VL in p ln nht ca tn hiu s u vo DAC m c nhn lmc logic 0"VD: : 0.8 V max

in p ngun dngAnalog Positive PowerSupply (+Vs)

VL di in p c th dng lm ngun cung cp dng cho DACVD: +4.75V min.; +5.0V typ.; +13.2V max.

in p ngun mAnalog Negative PowerSupply (-Vs)

VL di in p c th s dng lm ngun cung cp m cho DACVD: -13.2V min.; -5V typ.; -4.75V max.

in p mc logicdngLogic Positive PowerSupply (+VL)

VL di in p c th s dng cho mc logic dng ca DAC:VD: +4.75V min.; +5.0V typ.; +13.2V max.

in p mc logic mLogic Negative PowerSupply (-VL)

VL di in p c th s dng cho mc logic dng ca DACVD: -13.2V min.; -5V typ.; -4.75V max.

2.2.2. DAC chia in tr (Resistive Divider DACs)

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DAC theo phng php chia in tr c l l kiu DAC n gin nht. DAC kiu ny sdng mt chui in tr mc ni tip vi nhau to ra mt tp cc gi tr in p cch u nhaugia +Vref v Vref. Tn hiu s u vo xc nh tn hiu in p no c ni vi b khuchi thng qua cc cc b chuyn mch.

Mc d phng php chia in tr c th d hiu, nhng n tr nn km hiu qu vi cc bDAC c phn gii cao. Mi bit thm vo cho phn gii ca DAC i hi tng gp i sin tr v cng tc. V d nh vi DAC 12 bit th phi cn ti 4095 in tr v 4096 cng tc.

Hnh 2.3: DAC chia in tr

2.2.3. DAC trng s nh phn (Binary Weighted DACs)

Khi phn gii ca DAC t ti 6 hay 7 bit, kin trc thang in tr thng cho mtphng php hiu qu hn

Phng php ny cho ta li ch chnh l chng tit kim din tch vi mch. Chng hn nhmt DAC 9 bit ch cn 1 in tr v 1 cng tc thm vo so vi DAC 8 bit

Hnh 2.4: DAC trng s nh phn

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Chng 2: Giao tip tn hiu tng t

2.2.4. DAC iu bin rng xung (PWM DACs)

Phng php DAC iu bin rng xung (Pulse width modulation PWM) l phng phprt n gin v hu nh hon ton s dng phng php s, s dng rt t mch tng t

PWM iu chnh in p u ra s dng chui xung tn s cao vi rng xung c th thayi c thay i cng sut u ra

di xung cng ln th in p u ra cng gn vi in p ti a (VOH) ca DAC, vngc li di xung ngn nht tng ng vi in p ti thiu (VOL)

Tn hiu u ra s c a qua mt b loc thng thp to tn hiu analog

Hnh 2.5: DAC iu bin rng xung

DAC dng PWM cng kh thu c DAC vi phn gii cao, bi v c phn giicao, DAC phi iu chnh chui xung theo cc khong thi gian rt nh. iu yu cu phi cmt xung clock (master clock) vi tn s rt cao iu khin rng xung

V d vi DAC 16 bit, cn c phn gii theo thi gian bng 1/65536 ln chu k chuixung. V xung tn hiu cn phi a qua b lc thng thp to ra tn hiu tng t, tn sxung i hi phi gp nhiu ln ( thng thng l gp 100 ln) tn s cao nht ca tn hiu tngt u ra. Do mt b DAC 16 bit cho cc ng dng x l m thanh c bng thng 20kHz cn

c mt b to xung clock c tn s l 65536 x 100 x 20000 = 131 GHz. R rng rng tn s nyl khng th t c vi cng ngh hin nay

2.3 Chuyn i tn hiu tng t - s ADCs:

Gii php thng dng a tn hiu tng t vo x l bng cc b x l s l dng bchuyn i tn hiu tng t sang s (analog-to-digital converter - ADC). Hnh di l mt v dcho mt b ADC n gin. u vo cho b ny l hai tn hiu: mt tn hiu tham chiu

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(reference) v tn hiu cn chuyn i. N c mt u ra biu din mt t m dng s 8 bit. Tm ny vi x l c th c v hiu c

2.3.1. Cc tham s chnh ca mt ADC

Tham s n v Gii thch

phn giiResolution

Bits

Nu mt ADC c n bit, th phn gii ca n l 2n , cngha l s trng thi hay s m c th s dng chiau vo analog. S bit cng cao th phn gii cng lnv cng phn bit c nhiu trng thi

Sai s tuyn tnh viphnNon-Linearity,Differential (DNL)

Bits(with nomissingcodes)

Vi mi ADC, tn hiu s bin i theo tng bit LSB. chnh lch gia cc gi tr l tng c gi l phi tuyn vi phn.Example of an Actual Spec: 10 Bits min

Sai s tuyn tnh tchphnNon-Linearity,Integral (INL)

LSB

Hm truyn ca mt ADC l mt ng thng ni tim 0 ti im ton thang. Sai s ln nht ca mtm s vi ng thng ny c gi l sai s tchphn ca ADCExample of an Actual Spec: +/- 2 LSB's max

Di in p tng tu vo hay di tonthang(Analog Input Rangeor Full-Scale Range)

V

L chnh lch gia gi tr tng t ln nht v nhnht ng vi ADC c thVD:0V to +10 V, Unipolar Mode;-5V to +5V, Bipolar Mode

Thi gian chuyn i(Conversion Time)

secThi gian cn thit ADC hon thnh mt ln chuyniVD: 15 sec min.; 25 sec typ.; 40 sec max.

Ngun nui dng (+

Power Supply - V+) V

Di in p c th s dng lm ngun nui dng cho

ADCVD: +4.5V min.; +5.0V typ.; +7.0V max.

Ngun nui m- Power Supply (V-)

VDi in p c th s dng lm ngun nui m cho ADCVD: -12.0V min.; -15V typ.; -16.5V max.

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Chng 3: Th tc trao i tin ca my vi tnh

Chng 3 Th tc trao i tin ca my vi tnh

3.1 Cc ch trao i tin ca my vi tnh

Ch trao i tin ca MVT vi thit b ngoi Trao i tin theo ch chng trnh

S trao i tin c VXL iu khin theo mt trong hai loi lnh sau

Cc lnh vo (IN) hay ra (OUT).

Cc lnh chuyn(MOV) gia thanh ghi A v thanh ghi m s liu ca KGN c a chnh xc nh.

Trao i tin trc tip khi nh

Sau khi VXL c khi ng, s trao i tin hon ton do KGN iu khin thay cho VXL vcc ca vo ra ca VXL trng thi in tr cao (VXL b c lp). Lc ny, KGN iu khin mihot ng ca khi nh M v KGN, c th l:

Pht a ch cho khi nh hoc TBN. Pht lnh c (RD) hay ghi (WR) s liu.

Cc s liu c, ghi c trao i gia khi nh M va TBN thng qua cc thanh ghi mca KGN.

Th tc trao i tin trong ch chng trnh ch trao i tin theo chng trnh, c th trao i tin theo mt trong ba phng php sau:

- Trao i ng b- Trao i khng ng b hay hi trng thi (Polling)- Trao i theo ngt chng trnh

1.Trao i ng bSau khi khi ng TBN, MVT khng cn quan tm ti TBN c sn sng traoi tin hay khng m a lun cc lnh trao i tin ( c vo, ghi ra haytruyn s liu ). Phng php trao i tin ny ch c thc hin khi:

- TBN lun sn sng trao i tin.- Tc trao i tin ca MVT v TBN lun ph hp nhau hoc TBN trao i

tin nhanh.nh gi:- u im: Nhanh, khng tn thi gian ch i- Nhc im: Thiu tin cy, b mt tin v c th c s c

lm TBN cha sn sng trao i.2.Trao i khng ng b hay hi trng thi (Polling)

Trnh t trao i din ra nh sau:- MVT a tin iu khin TBN.- MVT ch v kim tra trng thi sn sng trao i tin

ca TBN bng cch:o c tin v trng thi sn sng ca TBN.o Kim tra trng thi sn sng. Nu cha, MVT

li c v kim tra trng thi sn sng.- MVT trao i tin vi TBN.

Trao i tin

Chng trnh

Chng trnh

TBN sn sng ?

Trao i tin

S

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Phng php trao i ny thc hin khi tc trao i tin ca TBN chm so vi MVT

nh gi:- u im: Tin cy, ch trao i khi bit chc TBN sn sng.- Nhc im: Tn thi gian s dng MVT.

V d: Gi s c mt thit b o lng c ghp ni vi my tnh. N c nhim v thu nhit t mtim o v chuyn thnh tn hiu s a vo my tnh. Thit b ny c mt thanh ghi trng thiStatusReg 8 bit cho bit trng thi hot ng ca n, khi no d liu sn sng my tnh c th c voth bit S5 ca thanh ghi ny s c t ln 1. Chng trnh iu khin s c nhim v lin tc c dliu nhit t thit b ny. Ta c on chng trnh nh sau:Begin

While ((StatusReg and 20H) = 20H) doBegin

c d liu v thc hin cc tc v lin quanEnd;

End.

3.2 Trao i tin ngt vi x lPhng php trao i tin ny khc phc nhc im ca cc

phng php trn. Trnh t nh sau:(1) MVT ang thc hin chui lnh ca mt chng trnh

no .(2) TBN c yu cu trao i tin, s gi tn hiu yu cu trao

i tin ( yu cu ngt INTR)(3) MVT (c th l VXL ) a tn hiu chp nhn (xc nhn

ngt INTA)

(4) Chng trnh chnh b ngt, MVT chuyn sang chngtrnh con phc v ngt tc l chng trnh con trao itin cho TBN yu cu.

(5) Chng trnh chnh lai tip tc thc hin ch b ngt.

3.2.1. Cc loi ngt ca my vi tnh PC

Cc loi ngtNgi ta chia ngt thnh hai loi: ngt cng v ngt mm

Ngt cng: cn gi l ngt ngoi v do nguyn nhn bn ngoi. VXL c cc li

vo dnh cho ngt ngoi. Khi c tn hiu vo li vo ny, chng trnh VXL ang thc hins b dng.

Ngt NMI( Non maskable Interrupt) - Ngt khng che c : Khi c ngt ny, VXL dngchng trnh sau lnh ang thc hin, thanh ghi a ch lnh (IP) v thanh ghi ch th flagc lu gi, 2 bit IF (Interrupt Flag) va TF (Trap Flag) b xo v 0 cm ngt ngoitip theo v khng c by. Mun cho php hay khng cho php ngt ny sy ra, chng tadng mt triger (flip flop) mc li vo ngt trc khi a vo li vo ngt NMI.

Chng trnh

Ngt

Chngtrn

hcon

phcvng

t

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Ngt INTR:o Ngt ny c cho php hay cm ngt bng cch lp hay xo bit IF ca thanh ghi flag.

Lp bi lnh STI (Set Interrupt), xo bi lnh CLI (Clear Interup)o Thng c ni vi li ra yu cu ngt ca vi mch x l u tin ngt (8214, 8259).

Ngt reset :

Ngt mm: (hay ngt bn trong do lnh ca chng trnh) do VXL gp cc lnhgy ra ngt hoc tnh hung c bit khi thc hin lnh (ngt logic) v ngt ca h iu hnh.- Ngt do lnh: l ngt khi thc hin cc lnh CALL, HLT, INT- Ngt logic hay cc ngoi tr: xy ra khi gp cc tnh hung c bit sau:

o Chia mt s cho 0o Trn ni dung thanh ghi hay b nho Thc hin tng bc (vector 1)o im dng ( Break point) chng trnh do ngi dung chng trnh s dng nh trc

(Vect 3)

- Ngt ca h iu hnh: l cc ngt do h iu hnh quy nh phc v trao i tin ca ccTBN (bn phm, my in, vv) nh INT 10, INT 16, INT 21, .v.v..)

Ngt ca MVT PC (8086, 80286 )

Cc ngt khng hon ton c lin kt vi cc thit b ngoi. H VXL 8086 cung cp 256ngt, a phn trong s chng l ch phc v nh ngt phn mm. H 8086 c mt bng vecterngt gi a ch ca cc chng trnh phc v ngt. Mi a ch l 4 byte.

Trong cc my PC, ch c 15 ngt dnh cho phn cng v 1 ngt khng che c. Phn cnli c s dng cho cc ngt phn mm v cc b x l ngoi l. B x l ngoi l l ccchng trnh tng t nh ISR nhng x l cc ngt khi xut hin li. V d nh vector ngt utin gi a ch ca ngoi l Divide by Zero (li chia cho 0). Khi xut hin li ny VXL nhysang a ch 0000:0000 v thc hin chng trnh c a ch lu y.

INT (Hex) IRQ Common Uses

00 - 01 Exception Handlers -

02 Non-Maskable IRQ Non-Maskable IRQ (Parity Errors)

03 - 07 Exception Handlers -

08 Hardware IRQ0 System Timer

09 Hardware IRQ1 Keyboard

0A Hardware IRQ2 Redirected

0B Hardware IRQ3 Serial Comms. COM2/COM4

0C Hardware IRQ4 Serial Comms. COM1/COM3

0D Hardware IRQ5 Reserved/Sound Card

0E Hardware IRQ6 Floppy Disk Controller

0F Hardware IRQ7 Parallel Comms.

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10 - 6F Software Interrupts -

70 Hardware IRQ8 Real Time Clock

71 Hardware IRQ9 Redirected IRQ2

72 Hardware IRQ10 Reserved


74 Hardware IRQ12 PS/2 Mouse75 Hardware IRQ13 Math's Co-Processor

76 Hardware IRQ14 Hard Disk Drive


78 - FF Software Interrupts -

Th tc x l (p ng) ngt chng trnh

Khi c mt tin hiu yu cu ngt chng chnh a vo chn yu cu ngt (INTR), qu trnh

ngt chng trnh c din ra theo cc bc sau: Lu gi tin v trng thi ca VXL lc c tn hiu yu cu ngt v ni chng trnh b gin

on.

VXL gi tn hiu xc nhn hay cho php ngt INTA v c vector ngt.

Chuyn sang chng trnh phc v ngt.

Tr v ch chng trnh chnh b ngt v tip tc thc hin chng trnh .

Lu gi tin v ch b ngt chng trnh:

cui mi chu trnh lnh, VXL 8086 ( cng nh 80286) kim tra xem c yu cu ngt nogi ti khng. Nu c yu cu, VXL tin hnh lu tr tin v ni b ngt chng trnh ( dng lnhPUSH vo vng nh ngn xp m a ch ch th bi thanh ghi SP).Cc tin l:

- Thanh ghi c Flag FR (Flag Register)- Con tr lnh IP(Instruction Pointer)- Thanh ghi on lnh CS (Code Segment register)

Gi tn hiu cho php (xc nhn ) ngt v c vector ngt:

Sau khi lu tr tin v v tr b ngt ca chng trnh chnh, VXL gi tn hiu xc nhn ngtINTA (Interrupt Acknowledge) cho KGN ca TBN. Tu cch t chc ngt v to vector ngt,

VXL s dng tn hiu ny c vector ngt tng ng ca KGN vo thanh ghi cha A. VXLc ni dung ca nh c a ch l vector ngt bit c a ch u tin ca chng trnhcon phc v ngt ( chng trnh trao i tin).

Thc hin chng trnh con phc v ngt

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l chng trnh m a ch lnh u tin nm trong nh c a ch l vector ngt. Ktthc chng trnh con ny, c lnh tr v (RET - return) VXL tip tc thc hin chng trnhchnh.

Tip tc thc hin chng trnh chnh:

Sau khi gp lnh tr v (RET), VXL tin hnh c v hi phc cc tin ca VXL lc b ngt

chng trnh ghi nh ch ngt chng trnh (bng lnh POP cc nh ngn xp). Qua trnhc ra ny xy ra ngc li vi qu trnh ghi vo (theo quy lut LIFO Last In First Out) v nidung ca:

Thanh ghi con tr lnh (IP) tr v lch (offset) ca a ch lnh tip theo ca chngtrnh chnh b ngt trong mng nh lnh (CS).

Thanh ghi mng lnh (CS) v a ch on u tin ca vng nh dnh cho chng trnhchnh b ngt.

Thanh ghi flag lc b ngt chng trnh.

3.2.2. X l ngt cng trong IBM - PC:

VXL 80x86 c 3 chn dng cho ngt cng l:INTR: Interrupt RequestNMI: NonMaskable Interrupt/INTA: Interupt Acknowledge

INTR l tn hiu u vo yu cu ngt ca VXL v n c th che hay cho php thng qualnh CLI (Clear Interrupt) v STI (Set Interrupt)NMI tng t INTR nhng khng che c bng lnh

INTR v NMI c th c kch hot t bn ngoi bng cch ni vo in p 5V vo chntng ng ca VXL.

Nh vy VXL ch c kh nng phc v mt yu cu ngt cng t TBN. m rng khnng phc v ngt ngoi IBM - PC s dng thm vi mch x l ngt cng lp trnh c PIC(Programmable Interrupt Controller) 8259. S dng PIC 8259 ni vo chn INTR c th m rngs lng ngt cng ln n 64s

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RAM

KGN1VXL

InterruptController KGN8

. . .IR0IR7

ROM

INTR

INT

/INTA

NMIResetC ch thc hin ngt cng

System bus

. . ..

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Vi mch x l ngt 8259S khi:

Cc chn:IR0 IR7 (Chn 18 25) : Cc li vo yu cu ngtD0 D7 (Chn 11 4) : Cc bit s liu (2 chiu)A0 (chn 27) : a ch chn thanh ghi lnhCS (Chn 11) : Chn vi mch (chip select)WR (chn 2) : Li vo lnh ghiRD ( chn 3) : Li vo lnh cCAS0 2 (Chn 12,13,15) : Li vo mc ni tngSP (chn 16) : Trong ch khng m, nu SP = 1 th 8259 l ch (Master).

SP = 0 th l t (Slave)INTA (chn 26) : Li vo xc nhn ngtINT (chn 17) : Li ra yu cu ngt chng trnh

Cu trc PIC 8259

Thanh ghi yu cu ngt IRR (Interrupt Request Register): ghi tm mc ngt(IR0 IR7)t TBN.

Thanh ghi Ngt ang phc v ISR (In Service Register): ghi mc ngt ang s dng.

Thanh ghi mt n ngt IMR (Interrupt Mask Register).

Mch logic gii quyt u tin PR (Priority Resolver)

CAS0

CAS1

CAS2

B md liu

Logicc/ghi

B so snhv ni tng

Logic iu khin

Thanhghi phcv (ISR)

Giiquyt u

tin(PR)

Thanhghi yucu ngt

Thanh ghi che ngt (IMR)

D0

D7

A00

A00

A00

A00

A00

A0 INT

IR0

.

.

.

.IR

n

ngdyni

S khi 8259

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Khi logic iu khin: x l ngt, a yu cu (INT) v xc nhn ngt (INTA)

B m ng dy s liu: m ghi vo cc thanh ghi v m c cc s liu t ccthanh ghi.

Logic iu khin c/ghi: to cc tn hiu ghi v c cc thanh ghi m.

B m ni tng/so snh: chn cc vi mch 8259 t trong mt vi mch 8259 ch.

i vi IBM - PC, 2 PIC c s dng m rng ra 15 ngt cng. PIC1 qun l u vongt IRQ0 - 7, PIC2 dnh cho IRQ8 - 15. PIC2 c ni tng ?ln PIC1 qua ng IRQ2 (Do nu ta chn ngt IRQ2 th ton b IRQ 8 - 15 cng b che.

3.2.3. Lp trnh x l ngt cng:Trong my IBM - PC c 2 PIC c nh v ti cc a ch l PIC1 - 20H, PIC2 - A0H. Cc PIC ckhi to bi BIOS, do ta ch cn quan tm ti 2 lnh khi lm vic vi chng.

Lnh th nht tc ng vo t iu khin OCW1 thit lp vic che ngt Nu munche ngt no th ta xo bit tng ng vi ngt v 0. T iu khin OCW1 c gi ti

a ch base + 1. Lnh th 2 l lnh End of Interrupt (EOI). Lnh ny c gi ti PIC khi kt thc chng

trnh con x l ngt reset PIC. Lnh EOI c gi ti PIC bng cch ghi gi tr 20Hvo thanh ghi c a ch base.

Thc hin chng trnh x l ngt;

Trong ngn ng C ta c th thc hin mt chng trnh x l ngt bng khai bo

MPU

IR0IR1

IR2

IR3

IR7

INT

/INTA

IR0

IR1

IR2

IR7

INT

/INTA

CAS0-2

INTR

/

INTA

CAS0-2

Pri PIC

Sec PIC

IRQ0

IRQ1

IRQ3

IRQ7

IRQ8

IRQ9

IRQ10

IRQ15

: : :

: :

Port 20H

Port A0H

S ghp ni ni tng PIC trong IBM - PC

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void interrupt myISR()

trong yourisr l con tr tr n a ch m chng trnh ISR ca ta nm trong b nh. ach ny sau s c t vo bng vector ngt, v c gi khi c ngt.Khung ca mt chng trnh ISR vit bng C nh sau:

void interrupt myISR() /* Interrupt Service Routine (ISR) */

{ disable();

/* Body of ISR goes here */

oldhandler();

outportb(0x20,0x20); /* Send EOI to PIC1 */

enable();

}

void interrupt yourisr() nh ngha mt hm l mt chng trnh con x l ngt.

disable(); xo c ngt lm cho cc ngt cng khc (ngoi tr ngt NMI) khng thc hin

c. V trnh trng hp cc ngt khc c u tin cao hn s ngt chng trnh x lngt ca chng ta. Tuy vy vic ny c th khng cn thc hin.Phn thn ca chng trnh ISR gm cc lnh m ta mun thc hin khi yu cu ngt c kch hot.

Cc cng hoc cc thit b ngoi c th ngt VXL bi rt nhiu l do, vd nh nhn c mtbyte, time-out, trn b m, vv. Khi chng trnh ISR phi c thanh ghi trng thi ca KGN bit nguyn nhn gy ra ngt ca thit b, v c nhng thao tc tng ng.

i khi ngoi chng trnh x l ngt ca ta, h thng cn mt s chng trnh thng trkhc cng c kch hot khi c ngt . V vy sau khi thc hin xong cc thao tc ca mnh,chng trnh ISR ca chng ta phi c li gi ti chng trnh ISR c (nu c). Thc hin bng

lnh gi con tr tr ti a ch ca chng trnh ISR c. Trong trng hp ny l oldhandle()Trc khi thoat khi chng trnh con ISR, ta phi bo cho PIC bit l ta kt thc chng trnh ISR bngcch gi lnh EOI ti PIC tng ng.

Chng trnh con ISR mun c thc thi phi c mt chng trnh khi to v qun ln. on chng trnh sau s khi to v qun l chng trnh con myISR m ta va to. Githit chng ta s dng ngt IRQ3

#include

#define INTNO 0x0B /* Interupt Number - See Table 1 */

void main(void){

oldhandler = getvect(INTNO); /* Save Old Interrupt Vector */

setvect(INTNO, myISR); /* Set New Interrupt Vector Entry */

outportb(0x21,(inportb(0x21) & 0xF7)); /* Un-Mask (Enable) IRQ3 */

/* Set Card - Port to Generate Interrupts */

/* Body of Program Goes Here */

/* Reset Card - Port as to Stop Generating Interrupts */

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24/79

outportb(0x21,(inportb(0x21) | 0x08)); /* Mask (Disable) IRQ3 */

setvect(INTNO, oldhandler); /* Restore old Interrupt Vector Before Exit */

}

Trc khi thay th a ch ca chng trnh ISR mi vo bng vector ngt , ta phi lu vectorngt c, ta c th phc hi li sau khi thot khi chng trnh. Thc hin bng lnh

oldhandler = getvect(INTNO); /* Save Old Interrupt Vector */

trong INTNO l s hiu ca vector ngt ta mun lu.Sau ta ci chng trnh ISR mi ca ta vo bng lnh

setvect(INTNO, myISR); /* Set New Interrupt Vector Entry */

Ngt cng ta mun s dng phi c cho php bng lnh

outportb(0x21,(inportb(0x21) & 0xF7)); /* Un-Mask (Enable) IRQ3 */

Phn thn chng trnh chnh tip tc thc hin bnh thng tu theo tng ng dng, vd nhx l ho, giao tip vi ngi s dng, v.v. Khi c bt k s kin lin quan n thit b uc x l t ng bi chng trnh con ISR.

Trc khi thot khi chng trnh chnh ta lun phi khi phc li vector ngt c.setvect(INTNO, oldhandler); /* Restore old Interrupt Vector Before Exit */

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3.3 Trao i tin trc tip khi nh

3.3.1. C ch hot ng:

VXL khi to TBN

TBN khi xng vic truyn s liu bng cch s dng cc thng tin cung cp bi VXLthng qua qu trnh khi to

TBN thc hin vic truyn s liu bng cch truyn trc tip gia TBN v b nh thngqua s iu khin ca b iu khin DMA (DMAC)

3.3.2. Hot ng ca DMAC:

Khi to: Trc khi a DMAC vo hot ng, Phi c chng trnh khi to cho n. Qutrnh khi to s cung cp cho DMAC thng tin cn thit hot ng. l cc thng tin nh:a ch bt u ca khi d liu, kch thc khi d liu, chiu c/ghi d liu, s hiu cng caTBN.

Hot ng:

Xt trng hp truyn mt khi d liu t b nh ra TBN.(1) Bc 1: TBN yu cu DMA bng cch t tn hiu DREQ ln mc cao(2) Bc 2: DMAC t tn hiu mc cao vo chn HRQ (Hold Request) gi tn hiu

yu cu treo bus cho VXL, bo cho VXL bit DMAC cn s dng bus.(3) Bc 3: VXL kt thc chu k bus hin ti, chuyn cc cng ghp ni vi bus sang

mc tr khng cao v tr li yu cu DMA bng tn hiu mc cao chn HDLA( Hold Acknoledge) bo cho DMAC c quyn s dng bus

VXLDMAC MEMORY Disk

Controller

HOLD

HLDA DACK

DREQ

Data Bus

Address Bus

Control Bus (IOR, IOW, MEMR, MEMW)

Hot ng ca DMAC

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(4) Bc 4: DMAC kch hot tn hiu DACK bo cho TBN bit n s bt u iukhin vic truyn d liu.

(5) Bc 5: DMAC bt u truyn d liu t b nh ti TBN nh sau:o DMAC t a ch ca byte u tin ca khi d liu ln bus a cho Kch hot tn hiu /MEMR c byte d liu t b nh ln bus d liuo t a ch ca cng TBN ln bus a ch

o Kch hot tn hiu IOW ghi byte d liu ang c trn bus d liu ra TBNo Gim gi tr m v tng gi tr i cho Lp li qu trnh trn cho ti khi gi tr m bng 0.(6) Sau khi qu trnh DMA kt thc, DMAC xo gi tr HRQ xung mc thp, tr

quyn iu khin bus cho VXL.

3.3.3. Chip iu khin truy nhp b nh trc tip DMAC 8237 (Direct Memory AccessController)

DMAC 8237 c th thc hin truyn d liu theo 3 kiu: kiu dc (t b nh ra thit b ngoi

vi), kiu ghi (t thit b ngoi vi n b nh) v kiu kim tra. Khi Timing and Control (nh thi v iukhin):

To cc tn hiu nh thi v iu khin cho bus ngoi(external bus). Cc tn hiu ny c ng b vi xungclock a vo DMAC (tn s xung clock ti a l 5 MHz).

Khi Priority encoder and rotating prioritylogic (m ho u tin v quay mc u tin):

DMAC 8237A c 2 m hnh u tin: m hnh u tin cnh (fixed priority) v m hnh u tin quay (rotatingpriority). Trong m hnh u tin c nh, knh 0 s c mcu tin cao nht cn knh 3 c mc u tin thp nht. Cni vi m hnh uu tin quay th mc uu tin khi khi dngging nh m hnh u tin c nh nhng khi yu cuDMA ti mt knh no d c phc v th s c txung mc u tin thp nht.

Khi Command Control (iu khin lnh):Gii m cc thanh ghi lnh (xc nh thanh ghi s c truy xut vloi hot ng cn thc hin).

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Cc thanh ghi:DMAC 8237A c tt c 12 loi thanh ghi ni khc nhau:

27


28/79

Chc nng cc chn ca 8237A:

CLK (Input): tn hiu xung clock ca mch. Tn hiu ny thng c ly t 8284 sau khiqua cng o.

CS (Input): thng c ni vi b gii m a ch.

RESET (Input): khi dng 8237A, c ni vi ng RESET ca 8284. Khi Reset th thanhghi mt n c lp cn cc phn sau b xo:

Thanh ghi lnh

Thanh ghi trng thi

Thanh ghi yu cu

Thanh ghi tm

Flip-flop du/cui (First/Last flip-flop)

READY (Input): ni vi READY ca CPU to chu k i khi truy xut cc thit b ngoi

vi hay b nh chm.HLDA (Hold Acknowledge)(Input): tn hiu chp nhn yu cu treo t CPU

DRQ0 DRQ3 (DMA Request)(Input): cc tn hiu yu cu treo t thit b ngoi vi

DB0 DB7 (Input, Output): ni n bus a ch v d liu ca CPU

IOR , IOW (Input, Output): s dng trong cc chu k dc v ghi

EOP (End Of Process)(Input,Output): bt buc DMAC kt thc qu trnh DMA nu l ngvo hay dng bo cho mt knh bit l d liu chuyn xong

(Terminal count TC), thng dng nh yu cu ngt CPU kt thc qu trnh DMA.A0 A3 (Input, Output): chn cc thanh ghi trong 8237A khi lp trnh hay dng cha 4 bit

a ch thp.

A4 A7 (Output): cha 4 bit a ch

HRQ (Hold Request)(Output): tn hiu yu cu treo n CPU

DACK0 DACK3 (DMA Acknowledge)(Output): tn hiu tr li yu cu DMA cho ccknh.

AEN (Output): cho php ly a ch vng nh cn trao i

ADSTB (Address Strobe)(Output): cht cc bit a ch cao A8 A15 cha trong cc chnDB0 DB7

MEMR , MEMW (Output): dng dc / ghi b nh.

Cc thanh ghi ni:

Cc thanh ghi ni trong DMAC 8237A c truy xut nh cc bit a ch thp A0 A3

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Bit a ch ach Chn chc nng R/W?

A3 A2 A1 A0

0 0 0 0 X0 Thanh ghi a ch b nh knh 0 R/W

0 0 0 1 X1 Thanh ghi m t knh 0 R/W







1 0 0 0 X8 Thanh ghi trng thi / lnh R/W

1 0 0 1 X9 Thanh ghi yu cu W

1 0 1 0 XA Thanh ghi mt n cho mt knh W

1 0 1 1 XB Thanh ghi ch W

1 1 0 0 XC Xo flip-flop u/cui W

1 1 0 1 XD Xo ton b cc thanh ghi / cthanh ghi tm

W/R

1 1 1 0 XE Xo thanh ghi mt n W

1 1 1 1 XF Thanh ghi mt n W

a ch cc thanh ghi ni dng ghi / c a ch:

Knh/

IOR/

IOW A3 A2 A1 A0 Thanh ghi R/W?

0 1010

0101

0000

0000

0000

0011

a ch c s v a ch hin hnha ch hin hnhB m c s v b m hin hnhB m hin hnh

WRWR

1 1010

0101

0000

0000

1111

0011


WRWR

2 1010

0101

0000

1111

0000

0011


WRWR

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3 1010

0101

0000

1111

1111

0011


W RW R

a ch cc thanh ghi tr ng thi v i u khi n:

/IOR/

IOW A3 A2 A1 A0 Thanh ghi

1 0 1 0 0 0 Ghi thanh ghi lnh0 1 1 0 0 0 c thanh ghi trng thi

1 0 1 0 0 1 Ghi thanh ghi yu cu

1 0 1 0 1 0 Ghi thanh ghi mt n

1 0 1 0 1 1 Ghi thanh ghi ch

1 0 1 1 0 0 Xo flip-flop u/cui

1 0 1 1 0 1 Xo tt c cc thanh ghi ni

0 1 1 1 0 1

1 0 1 1 1 0 a ch c s v a ch hin hnh

0 1 1 1 1 0 a ch hin hnh

1 0 1 1 1 1B m c s v b m hinhnh

0 1 1 1 1 1 B m hin hnh

Mch 8237A-5 cha 4 knh trao i d liu DMA vi mc u tin lp trnh c. 8237A-5c tc truyn 1 MBps cho mi knh v 1 knh c th truyn 1 mng c di 64 KB. cth s dng mch DMAC 8237A, ta cn to tn hiu iu khin nh sau:

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Tn hiu iu khin cho h thng lm vic vi DMAC 8237A

Tn hiu AEN t 8237A dng cm cc tn hiu iu khin t CPU khi DMAC nmquyn iu khin bus.

TK:[1] DIRECT MEMORY ACCESS (69)

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Chng 4 Rnh cm m rng

4.1 t vn

Khi bn lun v cu trc my tnh ta thng cp n cc cu trc bus, cc ng dn busnh bus d liu, bus iu khin , v.v. Cc rnh cm m rng l mt dng th hin bng phn

cng ca bus trn bn mch chnh, trn c th cm thm cc card m rng thay i hocnng cp cu hnh ca my tnh.

S ra i ca cc loi rnh cm m rng gn lin vi s pht trin ca k thut my tnh. Ttrc n nay c n 8 kiu bus m rng c s dng cho my tnh c nhn. Vic phn loicc bus m rng da trn s cc bit d liu m chng x l ng thi. l cc bus:

- Bus PC (Cn gi l ISA 8 bit)- Bus ISA (16 bit)- Bus PC/MCIA (16 bit)- Bus VESA local (32bit)

- Bus SCSI (16/ 32 bit)- Bus EISA (32 bit)- Bus MCA (32 bit)- Bus PCI (32/ 64 bit)- Bus AGP (32/ 64 bit)

4.2 Bus PC

Bus PC l loi bus xut hin trn my tnh PC/XTu tin nn c gi lun l bus PC. Loi bus nytn dng kin trc ca b VXL Intel 8088, nn c

mt bus d liu 8 bit v ngoi v bus a ch 20 bit.Rnh cm ni vi bus PC c 62 chn cho php cmvo mt card m rng lm t mch in 2 mt. V trnbus ny c 8 bit d liu c truyn ng thi nnbus PC cn c gi l bus PCI 8 bit

Tc truyn ca bus PC c c nh 4.77MHz

i vi bus ISA 8 bit ta cn quan tm n mt sng tn hiu chnh sau:Tn hiu Hng M t

A0 - A19 I/O 20 ng tn hiu a ch dng nh a ch cho bnh v cc thit b ngoi vi

D0 - D7 I/O 8 ng tn hiu to thnh BUS d liu cho vi x l, b nh v cc thit b ngoi vi

Reset Out Sau khi bt my tnh hoc sau khi khi ng li, ngdn Reset s kch hot trong thi gian ngn a card c cm vo n mt trng thi ban u xc nh.

Article I. S chn khe cm ISA 8bit

Article II. Pha mch in

Article III.Pha linh kin

GND B01 A01 /IOCHCK Reset B02 A02 D7+ 5V B03 A03 D6IRQ2 B04 A04 D5- 5V B05 A05 D4

DREQ2 B06 A06 D3- 12V B07 A07 D2

D tr B08 A08 D1+ 12V B09 A09 D0

GND B10 A10 /IOCHRDY/MEMW B11 A11 AEN/MEMR B12 A12 A19

/IOW B13 A13 A18/IOR B14 A14 A17

/DACK3 B15 A15 A16DERQ3 B16 A16 A15

/DACK1 B17 A17 A14DREQ1 B18 A18 A13/DACK0 B19 A19 A12

CLK B20 A20 A11IRQ7 B21 A21 A10IRQ6 B22 A22 A9IRQ5 B23 A23 A8IRQ4 B24 A24 A7IRQ3 B25 A25 A6

/DACK2 B26 A26 A5TC B27 A27 A4ALE B28 A28 A3

+ 5V B29 A29 A2OSC B30 A30 A1GND B31 A31 A0

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Chng 4: Rnh cm m rng/IOW Out Input/Output/Write:

Tn hiu ny s kch hot khi truy nhp ghi ln mt card mrng. Mc thp ch ra rng cc d liu c gi tr ang ch a ra bus d liu. Cc d liu c n nhn bng s-n trc

/IOR Out Input/Output/Read:Mc thp ca ng dn a ch ny bo hiu s truynhp c trn mt card m rng. Trong thi gian ny ccd liu c gi tr cn phi sp xp sau c nnhn bng sn trc

AEN Out Address Enableng dn iu khin AEN dng phn bit chu trnhtruy nhp DMA v chu trnh truy nhp b vi x l. mccao DMA gim st qua bus a ch v bus d liu. ngdn c hiu lc mc thp. ng dn ny cn phi c sdng cho qu trnh gii m a ch bi card m rng.

4.3 Bus ISA (16 bit)

Cng ty my tnh IBM pht trin bus ISA dng trong my tnh AT da trn b VXL80286. im mnh ca bus ny l c th cho php cng mt lc x l hoc trao i vi 16 bit dliu. m bo tnh tng thch vi bus PC, cc nh thit k b xung rnh cm th 2 thnghng vi rnh cm PC 8 bit, trn c cha 8 bit d liu v 4 bit a ch. Nh vy bus ISA cmt bus d liu 16 bit v mt b a ch 24 bit. Ging nh bus PC, n s dng tc ng h cnh 8.33 MHz

Do cch t chc rnh cm nh vy nn mt card PC vn c th cm vo mt khe cm ca bus

ISA. Card ISA rt ph bin bi v chng th hin tnh nng u vit i vi hu ht cc ng dngghp ni. Cc linh kin c s dng trn card u rt r, cho nn trn thc t vic ghp nibng cc card m rng ISA t ra l cng ngh qua th thchs v ng tin cy.

4.4 Bus PCICng ty Intel xy dng nn mt tiu chun ghp ni mi c tn l bus cc b PCI

(Peripheral Componel Interconnection - Kt ni cc thnh phn ngoi vi) hay thng gi tt l

bus PCI, dng cho b x l Pentium. Bus ny cho php truy nhp rt nhanh ti b nh, b

iu khin a, card m thanh, card ho. Vi mch ghp ni dng cho bus ny l chip PCI82430 cho php ghp ni trc tip vi bus.

Mt s c im chnh:

- Bus PCI truyn d liu bng tc ca ng h h thng cho php truyn d liu vi tc

cao hn nhiu so vi bus ISA.

- C th hot ng vi 64 bit - Tc ti a t c l 264 Mbyte/s

- Rnh cm PCI c mt chn cao hn do vy khong tng thch vi cc card ISA.

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4.5 Ghp ni qua khe cm m rng

4.5.1. Mt s c im ca Card ISA

Kch thc ln nht ca cc card ISA 8 bit l:

Chiu cao: 106,7 mm (hay 4.2 inch)

Chiu di 333.5 mm ( hay 13.13 inch) Chiu dy - k c linh kin - 12.7 mm (hay 0.5 inch)

Cc ng tn hiu ca khe cm b tr c 2 pha, v vy card m rng bao gi cng phi lbn mch in 2 mt.

4.5.2. Gii m a ch v kt ni Bus d liu

i vi my PC vng a ch 300 - 31FH c d tnh dnh ring cho card m rng cmthm vo. Cc ng a ch s dng i vi vng ny l A0 - A9.

Trn mt card m rng thng c nhiu khi chc nng nh b bin i tng t /s ADC,

b bin i s - tng t DAC, khi xut nhp d liu s, iu khin hin th, .v.v. . Cc khiny c trao i di nhng a ch khc nhau t my tnh. Do , trn card m rng phi cthm mt b gii m a ch. B gii m a ch c nhim v so snh i ch trn bus a ch camy tnh vi cc a ch c thit lp trc cho cc khi chc nng ca card m rng. Khia ch c s thng nht vi khi no th khi tng ng s c kch hot thng qua mtng tn hiu logic t u ra ca b gii m. Khi c kch hot, khi mi c th tin hnhs trao i thng tin vi my tnh.

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Chng 4: Rnh cm m rng

G19

DIR1

A12

B118

A23

B217

A34

B316

A45

B415

A56

B514

A67

B613

A78

B712

A89

B811

74245

Q?

MC74F245A

1

B2

C3

G16

G2A4

G2B5

Y015

Y114

Y213

Y312

Y411

Y510

Y69

Y77

Q?

SN74LS138

1

2345678

16

1514131211109

Q?

SW DIP-8

/(P=Q)19

Q03

Q1 5Q2

7

Q39

Q412

Q514

Q616

Q718

P02

P14P2

6

P38

P411

P513

P615

P717

/G1

Q?

74HC688

U?NAND

U?NAND

U?

NAND

A09

A07A06A05A04A03A02

A08

B14

B13

B02

A31A30

A29

A28

A26A27

A25A24A23A22

A11

VCC

R?RES2

VCC

/IOR

/IOW

RESET

AEN

A2

A3A4A5A6A7A8A9

D0D1D2D3D4D5D6D7

A0A1

D0D1D2D3D4D5D6D7

B gii m a ch 74HC688 so snh cc ng dn a ch A2 - A9 xem c thng nht via ch thit lp trc ca card m rng bng chuyn mch DIP. 74HC688 so snh cc cp bitxem c ging nhau khng. Khi cc cp ng nht thi s to ra mt tn hiu mc thp u ra.

Ngoi ra khi gii m cn phi quan tm n ng tn hiu AEN (Address ENable). ng nycho bit CPU hay DMAC ang chim quyn s dng bus. Khi tn hiu ny mc thp th cardm rng mi c s dng cc bus. Tn hiu AEN c a ti u vo /G ca 74HC688 chophp b gii m hot ng.

Cc ng tn hiu A0, A1, IOR, IOW cng c s dng trong b gii m bng cch kthp vi cc IC cng logic AND, OR v vi mch gii m 74HC138 to thnh cc ng iukhin c ghi cho tng khi chc nng trn card

B gii m logic ng thi m nhn vai tr iu khin b m bus 2 chiu 74HC245. Bny ni cc ng dn d liu ca rnh cm PC vi cc ng dn ca card m rng. Cch ghp

ni ny rtquan trng, nh vy m cc mc tn hiu trn ng dn d liu khng b nh hng.N c cha 8 vi mch m vi cc li ra 3 trng thi trao i thng tin gia cc ng dnbus d liu theo 2 hng. Hng truyn d liu c xc nh bng chn DIR: DIR = 0, d liuc chuyn t B sang A. Vic chuyn hng d liu cho php qun l n gin bng tn hiu/IOR. Ta c th ni trc tip ra chn DIR. Qua m bo b m ch cho php d liu a vot bn ngoi a ln bus d liu ca my tnh khi PC thc hin mt qu trnh truy nhp c(/IOR = 0)

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Chng 5 Ghp ni trao i tin song song

5.1 Khi ghp ni song song n gin

Ca vo n gin: Gm mt b gii m a ch - lnh v cc ca vo 3 trng thi a trctip s liu song song t thanh ghi m s liu t TBN vo ng dy s liu (D 0 - Dn) ca MVT

Ca ra n gin: Cng c b gii m a ch - lnh, nhng c thm cc thanh ghi cht sliu ra ghi s liu a ra t MVT. Li ra c th c thm s 3 trng thi c lp TBN vibus ca MVT

DI0

DI1

DI2

DI3

Gii m ach

A0

- An

RD

D0

D1

D2

D3

S ca vo n gin

Gii m i ch

WR

A0

- An

D Q

C

D Q

C

D Q

C

D Q

C

D0

D1

D2

D3

DO0

DO1

DO2

DO3

Ca ra n gin khng c i thoi

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Chng 5: Ghp ni trao i tin song song

5.2 Cc vi mch m, cht (74LS245, 74LS373)

5.2.1. Vi mch m 74LS245:

Vi mch 74LS245 cho tn hiu vo ra 2 chiu dng m s liu trong my tnh PC/XT(VXL 8086). Vi mch ny c 2 ng iu khin chnh, tn hiu /G l tn hiu cho php vi mchhot ng, khi /G mc cao, cc chn d liu ca vi mch trng thai tr khng cao.

Tn hiu DIR xc nh chiu truyn d iu. DIR = 1 d liu c truyn t A sang B, ngcli, khi DIR = 0 d liu c truyn t B sang A

5.2.2. Vi mch cht 74LS373:

Vi mch bao gm cc vi mch cht v cc vi mch cng 3 trng thi. Vi mch ny thngc dng cht a ch trong my PC/XT v cht d liu trong cc ng dng ghp ni mytnh. C 2 ng tn hiu iu khin l /OE v LE. Tn hiu /OE l tn hiu cho php hot ngca vi mch. Khi /OE mc cao, cc cng ca vi mch trng thi tr khng cao. Tn hiu LEl tn hiu cho php cht, tn hiu ny tch cc mc dng. i vi 74LS373, khi LE mccao, tn hiu a vo t cng D c a ra cng Q. Khi LE chuyn sang mc thp, tn hiu cng Q c cht li.

Inputs FunctionOutputs

G DIR A bus B bus

L L Output Input A = B

L H Input Output B = AH X High Impedance Z

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5.3 Vi mch PPI 8255A

5.3.1. Gii thiu chung

Vi mch vo ra song song lp trnh c PPI (Programable Parallel Interface) 8255 do hngIntel ch to. Ngoi kh nng cho php to mt giao din song song lp trnh c ghp nivi my tnh, n cn c th hot ng vi cc ch khc nhau v kh nng lp xo bit ca C

cho i thoi. Vi mch 8255 ny rt thng dng, thng c trong cc my tnh PC/XT, PC/AT vcc thit b trao i tin khc.

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Vi mch gm:- B m s liu trao i tin v s liu hai chiu gia PPI v bus ca my tnh.- B logic iu khin c vit: tc l b gii m a ch lnh cho cc thanh ghi m v thanh ghi

iu khin.Phn ghp ni vi TBN c:Ca A: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi phtCa B: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi phtCa C: Chia lm 2 na, cao v thp

Cng A8

Cng Cnathp

4

Cng B8

IO

PA0- PA

7

Cng Cna cao

4

IO

PA7- PA

4

IO

PA3- PA

0

IO

PA0- PA

7

8

4

4

8

iukhinnhm

AA

iukhinnhmB

msliu

D0- D

7

iukhinlgicc

ghi

RD

CS

WR

A1

A0

S khi ca PPI 8255A

Reset

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Tu theo ch s dng cho bi t iu khin ca C c th c dng- Trao i s liu vo hoc ra- iu khin hoc i thoi vi TBN v VXL khi ca A v B ch xc lp v xo tng bit PCi- iu khin hoc i thoi vi TBN v VXL khi ca A v B ch 1 v 2

Cc mch iu khin ni b: C cc khi iu khin (nhm A, nhm B) cc ca A, B v C.

5.3.2. Cc lnh ghi v c cc cng v cc thanh ghi iu khin

Vi t hp cc tn hiu a ch (A0, A1), chon vi mch (CS), v cc lnh c ghi (RD, WR)ca VXL, ta c cc lnh ghi c khc nhau cho cc ca (A, B, C ) v thanh ghi iu khin nhbng 3.2, to ra s di chuyn s liu gia ng dy s liu, cc ca v thanh ghi iu khin.Nh vy, vi mch 8255 c c im l khng c lnh c thanh ghi trng thi m dng lnh c ca Ckhi vi mch ch 1 v 2, cn ch 0, khng c trng thi.

A1 A0 CS RD WR Lnh (ca VXL)Chiu di chuyn s liu

(vi VXL)0 0 0 0 1 c cng A Cng A -> D0 - D70 1 0 1 1 c cng B Cng B -> D0- D7

1 0 0 1 1 c cng C Cng C -> D0- D71 1 0 0 1 Khng c gi tr0 0 0 1 0 Ghi cng A D0 - D7 -> Cng A0 1 0 1 0 Ghi cng B D0 - D7 -> Cng B1 0 0 1 0 Ghi cng C D0 - D7 -> Cng C

1 1 0 1 0Thanh ghi iukhin

D0 - D7 -> Thanh ghi iukhin

X X 1 X XTrng thi in trcao

Khng c trao i d liu

Cc lnh ca 8255A

5.3.3. Cc t iu khinT iu khin thit lp ch :

T iu khin lp xo bit:

Ch 0

D0

- D7

A0, A

1, CSWR, RD

Port C Port APort B

PB0

- PB7

PA0

- PA7

PC0

- PC3

PC4

- PC7

I/O I/O I/O I/O

8255A

D7 X X X D3 D2 D1 D0

0: Lp xa bit

BitD3D

2D

111PC00000 PC10010 P

C20100 PC

30110 PC

41001 PC

51

010 PC61101 PC

71111

0: xo1: lp

C lp/xo

T IU KHIN LP XO BIT CA VI MCH 8255

D7 D6 D5 D4 D3 D2 D1 D0

NhmB

Cng C thp1 = Li vo

0 = Li raCng B

1 = Li vo0 = Li ra

Mode1 = Mode 10 = Mode 0

NhmACng C cao1 = Li vo0 = Li ra

Cng A1 = Li vo0 = Li ra

Mode00 = Mode 001 = Mode 10X = Mode 2

Mode Flag1 = Active

Control Word (T iukhin)

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Chng 5: Ghp ni trao i tin song songCh ny cn c gi l ch vo hoc ra c s v:

- Cc ca A, B, v 2 na ca ca C c s dng c lp vi nhau- Cc ca c th l ca vo hoc ra tu t iu khin ch ghi vo thanh ghi iu khin- S liu ra c cht- S liu vo khng c cht- Khng c tn hiu i thoi vi VXL cng nh TBN. Nu mun c tn hiu i thoi, phi dng

cc bit ca ca no ( thng l ca C) cc lp ln 1 v sau l xo v 0 bng cch ghi s

liu hoc bng cch xc lp/ xo mt bit PC i ca ca C bi t iu khin vi D7 = 0. Khi cngC phi thit lp ch ra.

- Lp xo tng bit ca cng PC- ch 0, ngi ta c th dng cc bit PCi ca ca C lp (t ln 1) v xo (xo v 0)

iu khin hoc i thoi vi TBN. Mun vy phi ghi li lnh vi D7 = 0 vo thanh ghi iukhin ca 8255A sau khi ghi li iu khin ch .

Ch 1:

Ch ny cn gi l ch vo ra c i thoi vi cc bit ca C. Chia thnh 2 nhm. Nhm A gm ca A trao i s liu v na C cao (PC3 PC7) i thoi vi VXL v

TBN.

Nhm B gm ca B trao i s liu v na C thp (PC0 PC2) i thoi vi VXLv TBN.

Chiu v ch 1 ca ca A v B do t iu khin quyt nh, cn cc tn hiu i thoi PC icn ph thuc chiu ca vo hay ra ca ca A, B

PC0 lun l tn hiu ra INTRB: tn hiu yu cu ngt chng trnh cho B

PC3 lun l tn hiu ra INTAA: tn hiu yu cu ngt chng trnh cho A

PC2 lun l tn hiu vo, nhn cc tn hiu yu cu STBBv xc nhn /ACKB ca thit bngoi cho ca B chung cho c 2 chiu vo hay ra. Cn na A, nu l ca vo, PC4 nhn/STBA ca thit b ngoi v PC6 nhn /ACK ca thit b ngoi nu ca A l ca ra.

Cc bit cn li ca ca C l vo hay ra tu t iu khin ch Ch ra:

Port APort B

PB0

- PB7 PA0 - PA7

I/O I/O

IBFB

STBB

IBFA

STBA I/O I/O

INTR

B

INTR

A

OBFB

OBFAACKB ACKAI/OI/O

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Ca vo

Ca ra

i thoi ca Ai thoi ca B

Cng A: Ch 1, chiu ra

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Mi khi d liu c ghi ra cng, tn hiu /OBF chuyn sang mc tch cc 0 thng bocho TBN bit d liu c cht cng ra v sn sng cho TBN c. Khi c c d liu,TBN kch hot tn hiu /ACK cho bit c d liu, khi tn hiu /OBF c t ng chuynv mc cao.

/OBF(Output Buffer Full): L tn hiu ra thng bo cho TBN bit d liu c cht cng ra A hoc B.

/ACK(Acknowledge): Tn hiu xc nhn bo v t TBN lm cho chn OBF chuyn lnmc cao. Tn hiu ny thng bo cho 8255 bit TBN nhn d liu.

INTR: Tn hiu ny thng thng dng ngt VXL mi khi TBN gi li tn hiu /ACK

INTE(Interrupt Enable): Bit ni, dng cho php hay cm tn hiu INTR.

- INTEA c lin kt vi PC6 nu cng A hot ng ch ra. PC4 nu ch vo

- INTEB lin kt vi PC2 vi c chiu ra v vo ca cng B

Ch vo: /STB: Chn nhn tn hiu xung cht. Khi c mt xung mc thp tc ng vo chn ny, d

liu a t TBN vo 8255 s c cht cng vo.

IBF: Khi tn hiu /STB tch cc tn hiu IBF s c chuyn sang mc cao, bo cho TBNbit 8255 cht d liu cng vo. Tn hiu ny s tr v mc thp khi VXL c tnhiu ang cht cng (khi tn hiu /RD tch cc)

INTR: Tn hiu ngt VXL, tch cc khi /STB chuyn sang mc cao. Khi c tn hiu /RDtn hii\ ny s thi tch cc.

Ch 2:

Ch ny ch dng cho ca A vi vo ra hai chiu v cc bit PC3 PC7 dng lm tn hiuhi thoi. Ca B lc ny c th hot ng ch 0 hoc 1, chiu vo hay ra c th t bng tiu khin.

Port APort B

PB0

- PB7

PA0

- PA7

I/O I/O

IBFA

STBA

INTR

A

OBFA

I/O (Ch 0)i thoi (Ch 1)

ACKA

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Ca B c th ch 0 hoc 1

Ca A ch ithoi 2 chiu

(2 chiu)

Cng A: Ch 1, chiu vo

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V d:Gi thit ta cn thit lp:PPI hot ng ch 0. Cng A vo, B ra, C cao vo, C thp ra.-> Ta c gi tr ca t iu khin l 98HCng B hot ng ch 1, vo. Cng A hot ng ch 0, ra. Cng C cao ra, cng C thp khngquan tm- > Gi tr t iu khin: 87H hoc 86H

T trng thi

Thng thng khi s dng 8255 ch 1 v 2, ta thng dng phng php iu khinbng ngt chng trnh. Tuy nhin ta c th s dung phng php hi vng trng thi bng cchc cng C bit c trng thi hot ng ca 8255. Do ta c th coi a ch cng C trongch 1 v 2 l a ch ca thanh ghi trng thi ca 8255. c thanh ghi trng thi ny, ta c thbit c cc thng tin sau:

C yu cu ngt chng trnh trao i tin ca cc ca A (INTRA) hay B (INTRB)

Cc thanh ghi m s liu vo c s liu (IBFA=1, IBFB=1)

Cc thanh ghi m ra c s liu (/OBFA = 0, /OBFB = 0)

Hoc ring vi ch 2, khi c ngt xy ra, ta cn phi c t trng thi bit c nguynnhn gy ra ngt l do 8255 nhn c d liu hay gi c d liu c cc hot ngtng ng.

5.3.4. Ghp ni 8255A vi MVT v TBN

S ghp ni ca vo ra theo chng trnh vi VXL v TBN nh hnh di. PPI 8255A t

gia VXL v TBN, ng vai tr trung chuyn tin gia VXL v TBN qua cc ng dy caMVT v TBN.

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Phn ghp ni vi MVT Cc tn hiu v s liu (data bus) D0 D7, a ch thp (A0,A1), lnh c (RD), lnh ghi

(WR) c ni thng vi cc li vo tng ng ca PPI 8255A

Tn hiu /CS (Chip Select) ca PPI c ni vi b gii m cc a ch cao (A2 An) caVXL

Cc tn hiu ra yu cu ngt chng trnh (INTRA , INTRB) ca 8255 c ni vo li voINTR ca VXL qua mt vi mch logic OR

Phn ghp ni vi thit b ngoi:

Tu thuc loi TBN, s bit ca ng dy s liu v phng thc trao i tin m ta c cchmc ng dy khc nhau.

Ch 0: Ba ng dy PA, PB, PC u c dng trao i s liu hoc tin v iukhin v trng thi mt cch bnh ng vi nhau v tu la chn. ch ny c th:

- Khng cn i thoi gia 8255 v TBN, ch c trao i s liu trn 1 trong 3cng

D0

D7

RD

WR

A0

A1

8

CS

RST

RD

WR

D0

D7

Gii ma ch

INTR

AINTR

B

PA0 PA7

8

PA0

PA7

8

PCTBN

A2

- An

INTR

VXL8255A

Ghp ni 8255A vi MVT v TBN

Reset

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- Nu cn tin v iu khin hay c trng thi ca TBN ta s dng thm cc cakhc cho mc ch ny ngoi ca trao i s liu

Ch 1: Ch c hai ca A,B trao i s liu c lp nhau, cn cc ng PCi ca caPC dng hi thoi cho cc ca A,B trn. Cc ng ny c chiu v vai tr xcnh do khng th thay i.

Ch 2: Ch cho ca PA vi s liu vo/ra hai chiu. Cc bit ca PC cng c vai tr vchiu xc nh

cc ch bt tay (i thoi), gia 8255 v TBN ch trao i hai tn hiu hi p m thiMt s ng dng ghp ni 8255 vi thit b ngoi:

Mch ghp ni 8255 ch 0:

hnh 4.x gii thiu cch ghp ni 8255 vi my in qua cng PA c chiu ra, v ghp nivi mt b bin i tng t - s qua cng PB c chiu vo. Cng C c dnh cho cc tn hiui thoi. Trong :

Na C thp l ca vo, c trng thi ca my in v ADC

- PC0 cho trng thi my in bn (busy)

- PC1 cho tn hiu ACK ca my in

- PC2 Cho tn hiu EOC (End of Convertion) ca ADC

Na C cao a ra cc tin v iu khin

- PC4 a ra tn hiu cht d liu cho my in

- PC5 a ra tn hiu Start cho ADC.

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Ghp ni 8255 ch 1:

8 PA0 PA7INTR

D0

D7

RD

WRA0A1

CS

RST RD

WR

D0

D7

Gii ma ch

PB0

PB7

My in

A2

- An

VXL 8255A

Ghp ni 8255A vi MVT v TBN ch 0

Reset

ADC

/ACK

Busy

Data Strobe

EOC

Start

PC0

PC1

PC4

PC5

PC3

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Chng trnh trao i tin cho 8255A

Tu theo cch mc v TBN, chng trnh cn c cc khi lnh c bn sau:1. Khi to: l lnh ghi vo thanh ghi iu khin ca 8255 vi a ch thp A0, A1 =11 ti t iu khin. Cc bit t iu khin ny c xc nh bi:- Ch ca cc ca- Chiu (vo/ra) ca cc ca2. iu khin TBN: Cn a ni dung ca cc bit cho cc ca dng iu khin TBN.Nu ch 1,2 cc bit nay l cc bit PCi ca i thoi, ta khng cn phi vit lnh a gi trra na. Cn trng hp ch 0 ta c th dng mt trong hai cch sau:- Lp/ xo tng bit PCi ca ca PC- a tin ra cc bit ca cc ca3. c v kim tra trng thi:

- Cc lnh c voo Thanh ghi trng thi nu ca dng ch 1, 2o Mt ca bt k ch 0 dng ghi trng thi ca TBN.

- Lnh v logic (AND) chn cc bit khng cn kim tra- Lnh so snh (CMP) vi cc gi tr 1 ca bit - Lnh tr v v tr c lnh c trng thi nu kt qu so snh khng ng trng thi cn xt4. Trao i s liu:- a s liu vo (IN v VXL h 86) hay chuyn s liu MOV (ca VXL 8085)- a s liu ra (OUT ) hay chuyn s liu MOV

D0

D7

RD

WR

A0

A1

8

CS

RST

RD

WR

D0

D7

Gii ma ch

PC3

PC0

A2

- An

INTR

VXL8255A

Ghp ni 8255A vi MVT v TBN ch 1

Reset

PB

My in

ADC

/ACKBusy

Data Strobe

EOCStart

PA

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5.4 Ghp ni song song qua cng my in

5.4.1. Ghi thiu chung

Cng my in l giao din thng c s dng nhiu nht trong cc ng dng ghp ni mytnh n gin, do tnh ph cp v n gin trong vic ghp ni v iu khin cng vi yu cu ti

thiu v thit b phn cng thm vo. Cng ny cho php a vo ti 13 bit v a ra 12 bit songsong, trong c 4 ng iu khin, 5 ng bo trng thi v 8 ng d liu. Trong hu nhbt k PC no ta cng c th tm thy cng my in pha sau. u ni ny c dng DB 25 chn(gic ci female).

Cc cng song song gn y c chun ho theo chun IEEE 1284 a ra nm 1994. Chunny m t 5 ch hot ng ca cng my in nh sau:

1. Ch tng thch (Compatibility mode)

2. Ch Nibble

3. Ch Byte

4. Ch EPP

5. Ch d ECP

Ch c s (hay cn gi l Centronics mode) c bit dn t lu. Ch ny ch cho phpa d liu theo mt chiu ra (output), vi tc ti a 150kB/s. Mun thu d liu (input) taphi chuyn sang ch Nibble hay Byte. Ch Nibble c th cho php a vo 4 bit songsong mt ln. Ch Byte s dng tnh nng song song hai hng ca cng my in a vo

mt byte. a ra mt byte ra my in ( hoc cc thit b khc) trong ch c s, phn mm phi

thc hin cc bc sau:(1) Vit d liu ra cng my in (ghi vo thanh ghi d liu)(2) Kim tra my in c bn khng, nu my in bn, n s khng chp nhn bt c d

liu no, do d liu ghi ra lc s b mt

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(3) Nu my in khng bn, t chn Strobe (chn 1) xung thp (mc 0), bo vimy in l c d liu trn ng truyn ( chn 2 - 9)

(4) Sau ch 5 microgiy v t chn Strobe ln cao (mc 1).

Ch m rng (EPP) v nng cao (ECP) s dng cc thit b phn cng tch hp thm vo

thc hin v qun l vic i thoi vi thit b ngoi. ch ny cho phn cng kim tratrng thi my in bn, to xung strobe v thit lp s bt tay thch hp. Do ch cn s dngmt lnh vo ra trao i d liu nn gip tng tc thc hin. Khi cng ny c th ad liu ra vi tc 1 2 MB/s. Ngoi ra ch ECP cn h tr s dng knh DMA v c thmb m FIFO.

5.4.2. Cu trc cng my in

Chun IEEE 1284 a ra 3 u ni dng cho cng my in. Dng A (DB25) c th thy huht cc my PC, dng B (36 chn) thng thy my in, v dng C, 36 chn, ging dng Bnhng nh hn, c cc thuc tnh in tt hn v c thm 2 ng tn hiu dnh cho cc thit b

i mi sau ny.S hiuchn

(DB25)Tn

Hng(In/Out)

Thanhghi

M t

1 nStrobe In/Out Control Byte c in

2 Data 0 Out Data

ng d liuD0 - D7

3 Data 1 Out Data

4 Data 2 Out Data

5 Data 3 Out Data

6 Data 4 Out Data

7 Data 5 Out Data

8 Data 6 Out Data

9 Data 7 Out Data

10 nAck In Status Xc nhn (Acknowledge

11 Busy In Status My in bn

12 Paper-Out / Paper-End In Status Ht giy ( Paper Empty

13 Select In Status La chn ( Select )14 nAuto-Linefeed In/Out Control T np giy ( Auto Feed

15 nError / nFault In Status Li

16 nInitialize In/Out Control t li my in

17 nSelect-Printer / nSelect-In In/Out Control

18 - 25 Ground Gnd

nXXXX: Tch cc mc thp

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Bng s chn ca cng my in

Tn hiu ra ca cng my in thng cc mc logic TTL.

Address Cng

378h - 37Fh LPT 1

278h - 27Fh LPT 2

Khi khi ng BIOS gn a ch cho cc cng my in v lu thng tin a ch ny trong bnh a ch cho bng di:

a ch bt u M t

0000:0408 a ch c bn cng LPT1

0000:040A a ch c bn cng LPT20000:040C a ch c bn cng LPT3

0000:040E a ch c bn cng LPT4

Chng trnh v d c thng tin a ch ca cc cng my in c trong my tnh:

#include

#include

void main(void){

unsigned int far *ptraddr; /* Pointer to location of Port

Addresses */

unsigned int address; /* Address of Port */

int a;

ptraddr=(unsigned int far *)0x00000408;

for (a = 0; a < 3; a++)

{

address = *ptraddr;

if (address == 0)printf("No port found for LPT%d \n",a+1);

else

printf("Address assigned to LPT%d is

%Xh\n",a+1,address);

*ptraddr++;

}

}

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5.4.3. Cc thanh ghi ca cng my in:1. Thanh ghi d liu (Data Register)

a ch TnRead/Writ

eS hiu

bitM t

Base + 0 DataPort

Write Bit 7 Data 7Bit 6 Data 6

Bit 5 Data 5

Bit 4 Data 4

Bit 3 Data 3

Bit 2 Data 2

Bit 1 Data 1

Bit 0 Data 0

a ch c s (Base address) thng gi l cng d liu (Data port) hay Thanh ghi d liu(Data Register) thng s dng a d liu ra cc chn tn hiu ( Chn 2 9). Thanh ghi nythng l thanh ghi ch ghi. Nu ta c d liu cng ny ta s thu c gi tr m ghi ra gnnht. Nu cng my in l hai chiu th ta c th thu gi liu vo t cng ny.

2. Thanh ghi trng th i ( Status Register):

a ch Tn Read/Write S hiu bit M t

Base + 1 Status Port Read Only Bit 7 Busy

Bit 6 Ack

Bit 5 Paper OutBit 4 Select In

Bit 3 Error

Bit 2 IRQ (Not)

Bit 1 Reserved

Bit 0 Reserved

Thanh ghi trng thi l thanh ghi ch c. Bt k d liu no vit ra cng ny u b b qua.Cng trng thi c to bi 5 ng tn hiu vo (Chn 10, 11, 12, 13, 15), mt bit trng thingt IRQ v 2 bit dnh. Ch rng bit 7 (Busy) l u vo tch cc thp, ngha l khi c mttn hiu +5V chn 11, bit 7 s c gi tr logic 0. Tng t vi bit 2 (nIRQ) nu c gi tr 1 cngha l khng c yu cu ngt no xut hin.

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3. Thanh ghi iu khin ( Control Register):

ach

Tn Read/Write S hiu bit M t

Base + 2 Control

Port

Read/Write Bit 7 Unused

Bit 6 UnusedBit 5 Enable Bi-Directional Port

Bit 4 Enable IRQ Via Ack Line

Bit 3 Select Printer

Bit 2 Initialize Printer (Reset)

Bit 1 Auto Linefeed

Bit 0 Strobe

Thanh ghi iu khin c d nh l ch ghi. Khi mt my in c ni vi my tnh, 4

ng iu khin s c s dng. l cc ng Strobe, Auto Linefeed, Inittialize v SelectPrinter, tt c u l u ra o tr ng Initialize.

Bit 4 v 5 l cc bit iu khin ni. Bit 4 cho php ngt v bit 5 cho php ch vo ra 2chiu. t bit 5 cho php thu liu vo qua ng Data 0 7.

4. Thanh ghi iu khin m rng ECR (Extended Control Register ):

a ch Bit Function

Base + 402H 7:5 Selects Current Mode of Operation

000 Standard Mode001 Byte Mode

010 Parallel Port FIFO Mode

011 ECP FIFO Mode

100 EPP Mode

101 Reserved

110 FIFO Test Mode

111 Configuration Mode

4 ECP Interrupt Bit3 DMA Enable Bit

2 ECP Service Bit

1 FIFO Full

0 FIFO Empty

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5.4.4. EPP - Enhanced Parallel Port

Cng song song nng cao (EPP) c thit k bi s lin kt gia cc hng Intel, Xircom& Zenith Data Systems. Cng EPP ban u c thit k theo chun v sau l chun IEEE1284 ra i nm 1994. EPP c hai chun: EPP 1.7 v EPP 1.9. C mt vi s khc nhau gia ccchun ny m chng c nhng nh hng ti cc thao tc x l ca thit b. Vn ny s cn

c ni n trong phn sau. EPP c tc truyn d liu theo tiu chun l t 500KB/s ti2MB/s. iu ny cho php cc thit b phn cng ti cc cng to ra tn hiu bt tay (tn hiu mcni, hi thoi) chng hn nh tn hiu stroble, phn mm x l chng, v d nh caCentronics.

EPP c s dng rng ri hn ECP. EPP khc vi ECP ch cng EPP pht ra cc tn hiuiu khin v iu khin tt c qu trnh truyn d liu t n ti thit b ngoi vi. Bn cnh thECP li yu cu thit b ngoi vi c s hi thoi tr li bi mt tn hiu mc ni. iu ny lkhng mm do cho vic thit l p mt lin kt logic v nh vy cn c mt b iu khin chuyndng hoc mt chip ngoi vi ECP.

EPP Hardware Properties (cc c trng phn cng EPP)Khi s dng ch EPP, mt t p cc tc v khc nhau (c tn tng ng) c sp xp trn

mi ng dy tn hiu. Cc tn hiu ny c ch ra trong bng 4. Chng s dng cc tn chungtrong SPP v EPP trong cc bng m t v cng song song v cc ti liu. iu ny c th lmcho n rt cng nhc ch r chnh xc nhng g ang xy ra. Mc d tt c cc ti liu yu s s dng tn theo EPP.

Pin SPP Signal EPP Signal IN/OUT Function

1 Strobe Write OutMc thp th hin mt chu k ghi, mc cach nh l ang c

2-9 Data 0-7 Data 0-7 In-Out Data Bus. Hai chiu

10 Ack Interrupt InInterrupt Line. Ngt xut hin sn dnca xung

11 Busy Wait InUsed for handshaking. A EPP cycle can bstarted when low, and finished when high.

12Paper Out /End

Spare In Spare - Not Used in EPP Handshake

13 Select Spare In Spare - Not Used in EPP Handshake

14 Auto Linefeed Data Strobe OutKhi mc thp, ch nh l ang truyn d

liu (data)15 Error / Fault Spare In Spare - Note used in EPP Handshake

16 Initialize Reset Out Reset - Tch cc thp

17 Select Printer AddressStrobe

Out Khi mc thp, ch nh ang truyn i ch

18-25 Ground Ground GND Ground

Bang 1 S xp xp cac chn cua EPP.

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Cc tn hiu Paper Out, Select v Error khng c xc nh trong t p cc tn hiu bt tay caEPP. Cc tn hiu ny c th c s dng tu theo s nh ngha ca ngi s dng. Trngthi ca cc c tn hiu ny c th c xc nh ti bt k thi im no theo s xp xp tnhiu ca thanh ghi trng thi. ng tic l khng c u ra tha. iu ny c th tr nn phc tpcho vic xc nh trng thi ti mt thi im no ca cho k truyn/nhn thng tin.

Cc thanh ghi trong ch EPP

Ch EPP c mt tp cc thanh ghi mi, trong c 3 thanh ghi c t ch SPP

Address Port Name Read/Write

Base + 0 Data Port (SPP) WriteBase + 1 Status Port (SPP) ReadBase + 2 Control Port (SPP) WriteBase + 3 Address Port (EPP) Read/WriteBase + 4 Data Port (EPP) Read/WriteBase + 5 Undefined (16/32bit Transfers) -Base + 6 Undefined (32bit Transfers) -Base + 7 Undefined (32bit Transfers) -

Qu trnh bt tay ca EPP

Theo trnh t thc hin mt chu k truyn d liu hp khi s dng EPP, chng ta phi theoth t bt tay ca EPP. Do phn cng lm tt c mi vic nn cc tn hiu bt tay ny ch c sdng cho phn cng ca chng ta m khng c s dng cho phn mm nh trong trng hpvi SPP. khi to cho mt chu k EPP, phn mm ch cn thc hin mt thao tc vo/ra khi to cho thanh ghi EPP. Chi tit v vn ny s ni c th sau.

EPP Data Write Cycle

Hnh 1. Enhanced Parallel Port Data Write Cycle.

1. Chng trnh ghi d liu vo thanhghi d liu EPP (Base+4)

2. /Write c xo v 0. (Cho bitang c mt thao tc ghi)

3. D liu c t ln ng truynd liu (2 9).

4. /Data Strobe c kch hot nu/Wait ang mc thp (Sn sng btu mt chu k mi)

5. My tnh ch tn hiu xc nhn thhin bi /Wait chuyn sang mc cao

6. Ngng kch hot /Data Strobe

7. Chu k ghi d liu EPP kt thc

Qu trnh gi a ch EPP (Address Write Cycle)

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Hnh 2. Enhanced Parallel Port Address Write Cycle.

1. Chng trnh ghi gi tr a chvothnh ghi a ch EPP (Base+3)

2. /Write c xo v 0. (Cho bit qatrnh ghi)

3. Gi tr a ch c t ln ngtruyn d liu (2 7).

4. /Address Strobe c kch hotnu /Wait ang mc thp (Sn sngbt u)

5. My tnh ch tn hiu xc nhnvng vi /Wait t ln mc cao (TBN c a ch xong)

6. Tn hiu /Address Strobe ngng tchcc

7. Chu k gi a ch EPP

EPP Chu k c d liu

Hnh 3. Enhanced Parallel Port Data Read Cycle.

1.Chng trnh ra lnh c thanh ghi dliu EPP (Base+4)

2. /Data Strobe c kch hot nu /Waitang mc thp(Sn sng mt chu kmi)

3.My tnh ch tn hiu xc nhn (/Waitchuyn sang mc cao)

4.D liu c c t cc chn tn hiuca cng

5.Ngng kch hot tn hiu /Data Strobe

6.Kt thc chu k c d liu

EPP Address Read Cycle

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Hnh 4. Enhanced Parallel Port Address Read Cycle.

1. Program reads EPP Address Register(Base+3)2. nAddr Strobe is asserted if Wait is Low

(OK to start cycle)3. Host waits for Acknowledgment bynWait going high4. Data is read from Parallel Port Pins5. nAddr Strobe is de-asserted6. EPP Address Read Cycle Ends

Chu y: Nu s du ng EPP 1.7 (trc IEEE 1284) tin hiu Strobes cho d liu va iachi co th c dung xac nhn s bt u cua mt chu ky ri cua trang thai i.EPP 1.9 se chi bt u mt chu ky i mc thp. Ca EPP 1.7 va EPP 1.9 chuy n tinhiu i (strobe) ln mc cao kt thuc chu ky.

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Cc thanh ghi s dng trong ch EPP

Cng EPP cng c mt t p cc thanh ghi mi. Tuy nhin c 3 thanh ghi l c trc trongcng song song chun. Bng sau cho thy cc thanh ghi c v cc thanh ghi mi.

Address Port Name Read/Write

Base+0 Data Port (SPP) Write

Base+1 Status Port (SPP) Read

Base+2 Control Port (SPP) Write

Base+3 Address Port (EPP) Read/Write

Base+4 Data Port (EPP) Read/Write

Base+5 Undefined (16/32bit Transfers) -

Base+6 Undefined (32bit Transfers) -

Base+7 Undefined (32bit Transfers) -

Bang 2: EPP Registers

Nh ta c th thy, 3 thanh ghi u l ging ht cc thanh ghi trong t p thanh ghi ca cngsong song chun v chc nng cng l ging. V th nu ta s dng mt EPP ta c th a dliu ra thanh ghi d liu (Base+0) theo kiu ging nh ta c th a d liu ra nu s dng SPP(Standard Parallel Port). Nu ta kt ni vi mt my in v s dng ch ph hp, sau taphi kim tra xem cng c bn khng, tip theo ta c th bo (strobe) v kim (Ack) tra thngqua vic ghi/c thanh ghi iu khin v trng thi.

Nu mun truyn thng vi mt thit b tng thch EPP th tt c cng vic ta phi lm lgi d liu ra thanh ghi d liu EPP (EPP Data Register) ti a ch Base+4 v cng my in ssinh ra tt c cc tn hiu bt tay cn thit. Tng t nh vy, nu mun gi mt a ch ti thitb, ta s dng thanh ghi a ch EPP (EPP Address Register) ti a ch Base+3.

C thanh ghi a ch (Address Register) v d liu (Data Register) u c th c v ghi, do c d liu t thit b ta c th s dng cng mt thanh ghi. mc d, card my in phi khipht mt chu k c vi tn hiuData Strobe hocAddress Strobe u ra. Thit b ngoi vn cth a ra tn hiu yu cu c qua ng tn hiu yu cu ngt v ISR (chng trnh con phcv ngt) s thc hin cng vic c.

Cng trng thi c mt s thay i nh. Bit 0 l d tr i vi t p thanh ghi ca SPP th

gi y n l Bit Time-out EPP. Bit ny s c l p khi xut hin mt Time-out EPP. S kinny xy ra khi ng tn hiu nWaitl khng c xc nhn tr li trong khong 10us (gi trny tu thuc vo cng khc nhau) ca tn hiu IOR hoc IOW c xc nhn. Cc tn hiuIOR v IOW l cc tn hiu c v ghi thit b (I/O Read v I/O Write) trn bus ISA.

Ch EPP c gin thi gian rt ging vi gin thi gian ca bus ISA. Khi thc hinmt chu k c, cng phi m nhn trch nhim iu khin ph hp cc tn hiu hi thoiRead/Write v tr li d liu nh trong chu k bus ca ISA. Tt nhin qu trnh ny khng ngthi vi chu k bus ISA, v th cng s dng tn hiu iu khin IOCHRDY (I/O Channel Ready)

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trn bus ISA cho bit trng thi i cho n khi hon thnh chu k bus. By gi ta c thtng tng rng nu mt qu trnh c hoc ghi EPP c bt u nu nh khng c thit bngoi vi no ni vo th s ra sao? Cng s khng bao gi nhn c mt tn hiu xc nhn(nWait) v th m c c mt yu cu cho trng thi i, my tnh phi thc hin mt vngl p kim tra. , do n duy tr vic gi tn hiu yu cu v ch kt thc trng thi wait, v mytnh s b treo. V vy m EPP thc hin mt kiu kim tra watchdog m thi gian time out l xp

x 10uS.Ba thanh ghi: Base+5, Base+6 v Base+7 c th c s dng cho cc thao tc c/ghi 32

bits d liu nu nh cng c h tr cho n. iu ny c th lm gim cc thao tc vo/ra ca ta.Cng song song c th chi truyn d liu 8 bits ti mt thi im cho nn bt k mt word 16hay 32 bits c ghi ti cng song song s c chia thnh cc byte v c gi qua 8 bits(ng) d liu ca cng song song.

Lp trnh cng my in trong ch EPP.

EPP ch c 2 thanh ghi chnh v mt c trng thi time-out, chng ta c th thit l p chng

nhng g?Trc khi ta c th bt u bt k mt chu k EPP bng vic c v ghi ti thanh ghi d liu

v thanh ghi a ch th cng phi c cu hnh mt cch ng n cho ch lm vic ca n.trong trng thi t do, cng EPP cn phi c cc tn hiu nAddress Strobe, nData Strobe, nWritev nReset trng thi khng tch cc ( mc cao - high level). Mt vi cng yu cu ta phi thitl p cc tn hiu ny trc khi thc hin mt chu k bus EPP. V vy nhim v u tin ca chngta l khi to mt cch th cng cc tn hiu ny bng vic s dng cc thanh ghi ca SPP. Cth l ghi gi tr xxxx 0100 ti thanh ghi iu khin khi to.

Trn mt vi card, nu cng song song c t trong ch ngc li, th mt chu k ghi

EPP s khng th thc hin c. V vy n s t bit phi t cng vo ch hp l trc khis dng EPP. Xo bits 5 ca thanh ghi iu khin c th lm cho vic l p trnh tr nn th v hnm khng lm ph v s pht trin chng trnh.

Bit time-out ca EPP The EPP: Khi bit ny c l p, cng EPP c th khng m bo ngchc nng ca n. Mt s kin chung l lun lun c gi tr 0FFh t c chu k a ch v chu kd liu. Bit ny nn c xo cc thao tc c tin cy v n phi lun c kim tra.

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Chng 6: Ghp ni trao i tin ni tip

Chng 6 Ghp ni trao i tin ni tip

6.1 t vn

Mt trong nhng k thut ghp ni c s dng rng ri l k thut ghp ni TBN qua cngni tip

- Qua cng ni tip c th ghp ni chut, modem ngoi, my in, b bin i A/D, cc thit b olng,

- Cc cch ghp ni ny s dng phng php truyn thng tin (d liu) theo kiu ni tip. cc bitd liu c truyn ni tip nhau trn mt ng dy duy nht. Ti mt thi im ch c mt bitd liu c truyn trn ng dy.

- Truyn thng ni tip c u im l cn t ng dy, c th s dng mt ng truyn, mtng nhn. Thng tin thu nhn l tin cy, tuy nhin tc truyn l chm.

- Chun RS232 c xy dng thnh chun chnh thc dnh cho truyn thng ni tip, do hip hicc nh cng nghip in t EIA (Electronic Industries Association) nm 1962. Chun ny chophp truyn vi tc cc i 19.600 bit/s vi khong cch nh hn 20 m

- Sau ra i mt s chun nh RS422, RS449, RS485 c tc truyn v khong cch cho php

xa hn. Vd: RS422: Tc truyn 10Mbit/s, khong cch >1000m

6.2 Yu cu v th tc trao i tin ni tip:

6.2.1. Yu cu:

Khi khong cch gia hai thit b trao i tin l rt ln, vic s dng phng php truyn tinsong song s i hi chi ph tn km v ng dy ng thi cng kh khn trong vic chngnhiu trn ng truyn. Do vi vic truyn tin khong cch xa v yu cu v tc khngln th phng php truyn tin ni tip c s dng. Truyn thng ni tip cn thm cng ongia cng tn hiu chuyn tn hiu song song thnh tn hiu ni tip gi i, sau phi

chuyn t tn hiu ni tip thnh song song ni nhn. Vic gia cng tn hiu ny cng tn mtkhon chi ph nhng cng gim hn nhiu so vi truyn thng song song.

Cc thit b u cui trong lin kt ni tip c th l cc loi thit b khc nhau nhng chngphi thng nht vi nhau v cc quy tc v giao thc cng nh nh dng d liu. S thng nhtny m bo d liu c gi ti bn nhn v bn nhn c th hiu c d liu . Phn ny strnh by v nh dng d liu v giao thc truyn d liu s dng trong truyn thng ni tip, vs ch trng hn ti phng php truyn thng khng ng b do c dng trong chun RS232ca cng ni tip COM

Trong truyn tin ni tip, ti mt thi im ch c mt bit d liu c truyn i v cc bit d

liu c truyn tun t nhau. Mt lin kt gia hai bn c th s dng hai ng d liu truyn theo hai hng ring bit hoc c th s dng chung mt ng d liu truyn theo chai hng vo cc thi im khc nhau. Vic truyn thng se dng chung mt ng tn hiucho c hai hng gi l truyn bn song cng (Half-duplex) cn trng hp s dng hai ngtn hiu ring cho hai hng cho php truyn ng thi c hai hng th c gi l truyn songcng y (Full-duplex). Trong my tnh PC, lin kt ni tip s dng dng Full-duplex.

C mt tn hiu phi c trong truyn tin ni tip l tn hiu xung ng h (clock). Tn hiuny gip iu khin dng d liu. Bn gi v bn nhn s dng tn hiu ny quyt nh khi

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no gi v nhn mi bit. C hai phng php truyn thng ni tip l truyn thng ng b(Synchronous) v truyn thng khng ng b (Asynchronous). Vi mi loi th cch s dng tnhiu clock l khc nhau.

6.2.2. Trao i tin ng b: Synchronous

Trong truyn thng ng b, hai bn truyn thng s dng chung mt ng tn hiu clock.

Tn hiu ny c pht ra bi mt bn hoc bi mt thit b pht xung ng b ring. Tn hiung b ny c th c tn s thay i hoc c mt chu k khng xc nh. Ngha l mi bittruyn i c xc nh ti mt thi im khi c s thay i mc tn hiu ca tn hiu clock. Bnnhn cng s dng s thay i mc xc nh khi no th c bit d liu gi ti. Th d nhbn nhn s cht d liu gi ti khi xut hin sn ln ca xung clock hay l s thay i mc tnhiu t thp ln cao. Truyn ng b bn nhn khng cn phi bit trc tc trao i tin mch cn qua tm ti tn hiu ng b pht trn ng dy ng b.

Truyn thng ng b rt hu ch khi truyn khong cch gn bi n cho php truyn thngvi tc cao. Tuy vy vi khong cch xa, vic truyn thng ng b l khng kh thi do n

i hi c thm mt ng tn hiu clock, nh vy cn mt ng dy thm vo, hn na s db nhiu trn ng truyn.

Mi khi tin ng b thng gm nhiu byte, cc khi c nh du bi cc byte nh dukhung tin, cc byte ny c gi tr l 16H ( m ASCII ca ch Sync)

Truyn thng ng b phi thc hin lin tc, khi khng c d liu cn truyn th bn phtvn tip tc phi truyn cc d liu trng duy tr s ng b.

Truyn thng ng b thc hin kim tra li bng phng php s d vng (chia tng tin cakhung cho mt a thc - gi l a thc sinh). S d ca php chia c ghi vo mt byte FCS( Frame Check Sum). pha thu, cng tnh tng t v so snh kt qu. Nu bng nhau th tin

truyn khng b li.

6.2.3. Trao i tin khng ng b - Asynchronous:

Trong truyn thng khng ng b, ng truyn s khng cn c thm mt ng tn hiuclock bi v mi bn c b pht xung ng b ca ring n. lm c nh vy, hai bnphi thng nht mt tn s xung chung, v tt c cc xung clock phi khp nhau mt mc no . Mi byte truyn i s bao gm mt bit Start ng b xung ng h gia hai bn vmt bit Stop nh du kt thc byte c truyn. Cng RS-232 ca my PC s dng nhdng khng ng b truyn thng vi cc thit b ngoi nh modem, my in cng nh tru

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Giao Trinh Ghep Noi May Tinh