High Dynamic Range Multibit Σ∆ ADC Based Receiver Prototype Employing Dynamic Error Correction

Invited Paper

Leopold E. Pellon, Lockheed Martin Corporation Maritime Sensors and Systems,

Moorestown, New Jersey, (leopold.e.pellon@lmco.com)

Abstract: In this paper, dynamic performance results are presented on a prototype multibit Σ∆ band-pass Analog to Digital Converter (ADC), implemented for conversion of intermediate frequency (IF) input signals to digital base band I/Q samples. The results include “real-time” processed outputs that exhibits high dynamic range over programmable output bandwidths ranging from 2.5 MHz to 20 MHz, centered at an IF input frequency of 70MHz. This prototype represents the first in a series of receiver developments employing this tunable Σ∆ ADC topology, focused on 100 dB SNR and 100 dB multitone SFDR performance levels. The architecture employs a band-pass multibit Σ∆ modulator and a digital processor that includes nonlinearity error correction, digital down conversion and decimation filtering.

I Introduction

This paper presents an architecture and prototype results that demonstrate the capability for a high dynamic range IF to Digital conversion element with goals supporting Signal to Noise and Distortion Ratio (SNR) on the order of 100 dB. This element is the heart of a high dynamic range digital receiver subsystem for radio frequency applications that must enable detection of small signals of interest below large interference signals or background clutter. The terms that limit SNR Spurious Free Dynamic Range (SFDR), and Intermodulation Distortion (IMD) arise as a result of dynamic performance of components forming the receive chain, and includes mixers, amplifiers, and the Analog to Digital Converter (ADC) elements. A trend for digital receivers is to employ converters that enable direct radio frequency (RF) sampling where intermediate frequency (IF) sampling may provide a practical choice for achieving high dynamic range.

The core of a receiver topology addressing IF to Digital conversion is based on a multibit Σ∆ modulator and digital error correction and down conversion processor with unique architectural features. The intermodulation distortion of components upstream of the ADC can benefit from the nonlinear correction technique employed, given inclusion of the front-end component in ADC calibration path. A prototype has demonstrated High SNR and multitone SFDR well beyond reported converters to date. A printed wiring board

implementation, including the use of custom mixed signal GaAs HBT components and GaAs pHEMT amplifiers is employed.

x(t)NodeNode

LNALNA(8 dB)

Bandlimited RF Signal

NLFNLFNLF

Numerically Controlled

Down Conv erter

NCDRecursive

Transversal Filter

CombIntegratorCascade

Decimator& Equalizer

I

Q

Wide Band 48-b Output(e.g.24 b I/Q 100MSPS)Wide Band 48- b Output(e.g.24 b I/Q 100MSPS)

320 LO FrequenciesPredict and

Cancel DAC Errors

PassiveDirectional

Coupler InputNode

16 b

6 bx(t)LNALNA(8 dB)

Bandlimited RF Signal

NLFNLFNLFNLFNLF

Numerically Controlled

Down Conv erter

NCDRecursive

Transversal Filter

CombIntegratorCascade

Decimator& Equalizer

I

Q

Wide Band 48-b Output(e.g.24 b I/Q 100MSPS)Wide Band 48- b Output

(e.g.24 b I/Q)

320 LO FrequenciesPredict and

Cancel DAC Errors

PassiveDirectional

Coupler InputNode

16 b

6 b

6 b

Enco

de&

1:4

Dem

ux

NLF

DAC

ADC

fsTuningWeights

x(t)NodeNode

LNALNA(8 dB)

Bandlimited RF Signal

NLFNLFNLFNLFNLFNLF

Numerically Controlled

Down Conv erter

NCDRecursive

Transversal Filter

CombIntegratorCascade

Decimator& Equalizer

I

Q

Wide Band 48-b Output(e.g.24 b I/Q 100MSPS)Wide Band 48- b Output(e.g.24 b I/Q 100MSPS)

320 LO FrequenciesPredict and

Cancel DAC Errors

PassiveDirectional

Coupler InputNode

16 b

6 bx(t)LNALNA(8 dB)

Bandlimited RF Signal

NLFNLFNLFNLFNLF

Numerically Controlled

Down Conv erter

NCDRecursive

Transversal Filter

CombIntegratorCascade

Decimator& Equalizer

I

Q

Wide Band 48-b Output(e.g.24 b I/Q 100MSPS)Wide Band 48- b Output

(e.g.24 b I/Q)

320 LO FrequenciesPredict and

Cancel DAC Errors

PassiveDirectional

Coupler InputNode

16 b

6 b

6 b

Enco

de&

1:4

Dem

ux

NLF

DAC

ADC

fsTuningWeights

Figure 1 Simplified Block Diagram of the Σ∆ ADC Architecture

II. Architecture and Goals for Design

The architecture of the digital receiver incorporates a band-pass continuous-time multibit Σ∆ modulator and a digital signal conditioning element the includes nonlinear error correction of the feedback DAC, digital down conversion and decimation filtering. These elements form the IF to Digital converter of the receiver system while the front-end down-converter employs one or two stages of mixing. Goals for this design include, a noise spectral density on the order of -174 dBFS/Hz (dB below full scale over a 1 Hz bandwidth) over the pass band, equivalent to 17 Effective Number Bits (ENOB) at 10 MHz bandwidth. Multitone spurious free dynamic range on the order of 110 dB is also a goal, which includes third order intermodulation distortion (IMD) terms.

In the block diagram of Figure 1, the multibit Σ∆ modulator, which is also referred to in the paper as the Σ∆ Encoder, and a digital error correction and direct digital down converter element, is referred to as the Decoder are shown [1,2,3,4]. The Σ∆ Encoder incorporates a 6 b flash ADC-DAC element and a Recursive Transversal Filter (RTF) as a higher order continuous-time Σ∆ loop filter. An order 4 RTF is employed to enable periodic resonances capable of producing 4 band pass noise attenuating zeros. The natural latency and frequency response of this feedback loop, including ADC-DAC, loop filter and interconnects is incorporated into the Σ∆ transfer function design. This leads to unconditionally stable results. Continuous-time delay lines are employed, which produce a “mathematical” source of resonant gain, rather than

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gain from transistor gm directly.[2] However, the RTF must meet stringent noise figure and harmonic intercept point requirements to achieve the performance goals for this architecture.

For a given normalized bandwidth fbw’, the actual bandwidth achieved is fbw=fbw’/Tdelay, where Tdelay is the transversal delay period of the RTF. Hence, the Σ∆ bandwidth can be increased without reducing the Noise Improvement Factor by reducing the minimum achievable transversal delay. Also, Integral to the RTF is a passive input sum node employing a directional coupler which exhibits low latency and allows directive addition of the input signal with negligible distortion associated with combining a full scale input with the feedback signal. The passive addition causes a ∆ signal to form prior to the first active component of the RTF. This provides improved large signal loop filter performance.

The Decoder element implements the digital Nonlinear Filter Correction algorithm (NLFC) in a feedforward manner, thereby avoiding the complications and performance limits related to actually correcting the feedback DAC directly. This is needed since the tight coupling of the DAC to the ADC is required to minimize feedback latency, a key requirement defining the bandwidth potential the method of Σ∆ modulation employed. The calibration of the NLFC is done during integration and test, where multiple stored temperature dependent values can be used. One can also enable system automatic calibration with high SNR and low IMD multitone signal sources. The performance of the unit will be limited to the accuracy and noise of the signal sources.

II Prototype Implementation

A prototype of the Σ∆ Encoder and Decoder have been constructed to demonstrate the capability of the architecture for high dynamic range digital receivers. This prototype demonstrates a “narrow band” capability for this architecture, and relates to bandwidths between 2.5 MHz to 20 MHz. Figure 2 illustrates both a block diagram and photograph of the integrated prototype Σ∆ Encoder and Decoder, each on separate test boards.

Σ∆ Encoder

CML to LVDS

EEPROMDecoderCoeff.

FPGADecoderDesign

Bypa ss Data(NLFC Calibration)

I/Q Doclk=fs/Ndec

I

Q

Dataclk

bypass Dbclk=fs/8

24 b

24 b

96 b

70 MHz IF Filter 40-80 MHz

fsclkClockLoop

FilterTuning

IF Amplifier(optional)

BW Tuning States 2.5,7.5,12.5, 20 MHz

DAC Monitor

Input

Sets: NLFC, NCO, CIFIR Equalizer

(multiple states)

Source

Σ∆Decoder

FPGAΣ∆ Encoder

CML to LVDS

EEPROMDecoderCoeff.

FPGADecoderDesign

Bypa ss Data(NLFC Calibration)

I/Q Doclk=fs/Ndec

I

Q

Dataclk

bypass Dbclk=fs/8

24 b

24 b

96 b

70 MHz IF Filter 40-80 MHz

fsclkClockLoop

FilterTuning

IF Amplifier(optional)

BW Tuning States 2.5,7.5,12.5, 20 MHz

DAC Monitor

Input

Sets: NLFC, NCO, CIFIR Equalizer

(multiple states)

Source

Σ∆Decoder

FPGAΣ∆ Encoder

CML to LVDS

EEPROMDecoderCoeff.

FPGADecoderDesign

Bypa ss Data(NLFC Calibration)

I/Q Doclk=fs/Ndec

I

Q

Dataclk

bypass Dbclk=fs/8

24 b

24 b

96 b

70 MHz IF Filter 40-80 MHz

fsclkClockLoop

FilterTuning

IF Amplifier(optional)

BW Tuning States 2.5,7.5,12.5, 20 MHz

DAC Monitor

Input

Sets: NLFC, NCO, CIFIR Equalizer

(multiple states)

Source

Σ∆Decoder

FPGA

Figure 2 Prototype IF to Digital Conversion Element Breadboard

The Σ∆ Encoder is constructed on a Printed Wire Board which includes an Order 4 single ended RTF built with surface mount pHEMT transistors for gain blocks, PIN diodes for variable attenuation, and GaAs MESFET switches for calibration and delay control. High linearity feedback class-A amplifiers, are strategically placed to overcome the losses of the other components of the RTF and to provide the minimum weighting gain required for each path. Bulk delay lines employ coaxial and microstrip transmission lines in this implementation. A custom ferrite core coupler sum node provides DAC differential to single ended conversion and input signal passive summing. A custom GaAs/AlGaAs 6 bit ADC-DAC /1:4 Demux ASIC, developed for this architecture at Rockwell Scientific is used at 800 MHz sampling rate, and provides low ambiguity and low noise quantization and feedback and 24 bit demultiplexed data, and clock output. The feedback latency achieved in this prototype supports a 7.14 nsec transversal delay, which is used to center the 4 noise shaping zeros at a 70 MHz center frequency.

The Decoder is implemented on a separate test board interfaced to the data output of the Σ∆ Encoder board. The Decoder functions are mapped to a XCV6000 FPGA. The Nonlinear Filter Error Correction (NLFC) element accounts for less than 20 % of the gate count. A Numerically Controlled Down converter (NCD), and I/Q high order decimation filter employs a numerically simple form of

CSIC 2005 0-7803-9250-7/05/$20.00 ©2005 IEEE Digest 296

polyphase filter and Comb Integrator Cascade (CIC). This is followed by a linear phase FIR equalization filter to provide a flat magnitude response over the pass band. Calibration of the Nonlinear Filter Correction coefficients is supported through a bypass data path.

Table 1 Summary Results of “Narrow Band” IF to Digital Σ∆ ADC Prototype

Parameter Value

Center Frequency 70MHz

Modulator Sampling

6-b @ 800 MSPS

Demonstrated Output Mode

24-b I / 24-b Q @12.5 MSPS OSR=64, NCO Tuned to +70MHz IF

Full Scale Input 13 dBm (single tone power) ±1.41 Vpp Input Range

93.5 dB 7.5 MHz 97.5 dB small signal 90.9 dB 12.5 MHz 93.7 dB small signal 78.8 dB

SNDR

20 MHz 81.5 dB small signal

7.5 MHz 111 dB (18.4 b) 12.5 MHz 107 dB (17.7 b)

SFDR (single tone) 20 MHz 94 dB (15.6 b)

Multitone SFDR 100 dBFS typically

Multitone SNDR 97.5 dB (15.8 ENOB) 7.5 MHz BW

IV Demonstrated Results

Table 1 summarizing the dynamic performance results measured on this prototype. The results constitute the highest dynamic range for single and multitone ADC conversion reported to date, and generally show the capability for high dynamic range with this topology. Both single tone and two tone error corrected results are shown based on the steady state performance observed at the Decoder Base band I/Q output. The particular formats are programmable, where the bandwidths of 7.5 MHz bandwidth and the 12.5 MHz employ a 12.5 MHz I/Q (24-b each) output. The worst case dynamic range from SNDR is represented by full scale single tone results, such as 93.5 dB (15.2 ENOB) at 7.5 MHz of bandwidth. Figure 3 shows an FFT of the Σ∆ output spectrum,

after software error correction. Figure 4 shows an FFT test of the I/Q Decoder based band output for this case, with and without real-time nonlinear correction. Full scale two tone SNDR is shown to provide the best overall results with 15.8 ENOB (including IMD terms). Steady state performance of the error corrected real-time Σ∆ ADC receiver yields IMD terms -101 dBFS with much lower IMD immediately after calibration. This is shown in Figure 5. The noise floor of the two tone case is equivalent to that observed for smaller input single tone signals.

Figure 3 Output of Σ∆ Spectrum After NLFC, tuned for fbw=12.5 MHz at fc=70 MHz

a. correction off

b. correction on

a. correction off

b. correction on

Figure 4 Single-tone full scale input signal response shows 15.2 ENOB over 7.5 MHz of bandwidth at Decoder output.

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Figure 4 Steady state two tone response of error corrected ADC subsystem (15.8 ENOB over 7.5 MHz of bandwidth) with IMD at -100 dBFS.

For many applications, the interference signals received are closer to multitone in their amplitude distribution, and are often approximated as Gaussian signals. As a result, the multitone SNDR is a better measure for assessing the interference suppression supported by the digital receiver.

The nonlinear filter correction (NLFC) coefficients [4] with respect to the results of Figures 3,4 and 5, are calibrated as the optimum for eight different signal input excitation cases, ranging from single tone to two tone. Each calibration requires the capture of the decoder bypass data, for each of these cases. The coefficients are derived off line and stored with the decoder. Multiple sets can be calibrated and stored for temperature dependent look-up. The multiple signal cases ensure the suppression of spurious that may be produced by the NLFC under varying input signal conditions.

Figure 6 illustrates the transient response determined shortly after calibration. The comparison in this case is using the bypass data and software corrected results. The IMD are shown to cancel by 50.7 dB

50.7 dB

Without Correction Immediately After Correction

50.7 dB

Without Correction Immediately After Correction

Figure 5 Transient Response of Nonlinear Filter Correction the Multibit Σ∆ ADC.

V Conclusions

This paper presents a prototype of an architecture incorporating continuous-time multibit Σ∆ modulation and related digital processing to achieve high dynamic range RF sampling, with capability for 100 dB SNR and SFDR receiver chains. This is relevant for both demonstrating the limits of ADC conversion performance, and practical advantages for enabling that enhancing the entire chain in a highly integrated architectural manner. The results presented represent the highest dynamic range reported to date, known to the author.

Work to extend this architecture to higher levels of integration, greater bandwidth and input center frequencies is proceeding under support of DARPA, AFRL and ONR.

References:

[1] L.E. Pellon ,”RF to Digital Converters Employing Bandpass Multibit Σ∆ Modulator”, GaAs IC Symposium 1998

[2] Patent# 5673044 Cascaded Recursive Transversal Filters for Sigma delta Modulators, L.E. Pellon, Sept 30 1997

[3] Patent# 6160506 Low Noise Sigma-delta Converter, L.E. Pellon, Dec 12 2000

[4]Patent# 6271781 Nonlinear Filter Correctio of Multibit Sigma-delta Modulators, L.E. Pellon, Aug 2001

[5] M. Nejad and G. Temes, “A High Resolution Multibit Σ∆ ADC with Digital Error Correction and Relaxed Amplifier Requirements”, IEEE Journal of Solid State Circuits, VOL. 28 No. 6 pp648-660, Kune 1993

Achknowledments: The author thanks Gregg Daugherty and Junius Pridgen of Lockheed Martin, and M.J.Choe of Rockwell Scientific for their many contributions. Also the author thanks Dennis Healy, Charles Cerny and Dan Purdy for their support of this architecture.

CSIC 2005 0-7803-9250-7/05/$20.00 ©2005 IEEE Digest 298