Instruction Set Architectureviplab.cs.nctu.edu.tw/course/DSD2015_Spring/DSD_Lecture... · 2015. 5. 15. · Digital Systems Design Lecture 9 Computer Architecture Two classes of computer

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http://www.cs.nctu.edu.tw/~ldvan/

Instruction Set Architecture

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science National Chiao Tung University

Taiwan, R.O.C. Spring, 2015

Source: Prof. M. Morris Mano and Prof.

Charles R. Kime, Logic and Computer Design

Fundamentals, 3rd Edition, 2004, Prentice Hall.

Digital Systems Design

Lecture 9

Content Connections

Digital System Design Embedded System: Zedboard

DSP System: Adder, Mul, Filter

Computer Architecture

2

Embedded System: Galileo


Lecture 9

Outlines

Computer Architecture Concepts

Operand Addressing

Addressing Modes

Instruction Set Architectures

Data Transfer Instructions

Data Manipulation Instructions

Floating-Point Computations

Program Control Instructions

Summary

3


Lecture 9

Computer Architecture

Two classes of computer architectures:

— Reduced instruction set computers (RISCs)

— Complex instruction set computers (CISCs)

Three categories of elementary instructions:

— Data transfer, Data manipulation, Program control

Instruction set architecture (ISA):

— All hardware-implemented instructions, specify the symbolic

names and binary code format of the instructions, & a precise

definition of each instruction

Assembly language:

— Replace binary opcodes and addresses with symbolic names &

provides other features helpful to the programmer

Machine language:

— The binary language in which instrs are defined and stored in

memory 4


Lecture 9

Instruction Formats

Typical field of the Instruction formats:

— Opcode field:

Specifies the op to be performed

— Address field:

Provides either a memory addr or a reg addr

— Mode field:

Specifies the way the addr field is to be interpreted

— Others:

E.g.: # of positions to shift, operand field

5


Lecture 9

Basic Computer Operation Cycle

The execution steps for each instr:

— 1. Fetch the instr from memory into a control reg.

— 2. Decode the instr.

— 3. Locate the operands used by the instr.

— 4. Fetch operands from memory (if necessary)

— 5. Execute the op in processor regs.

— 6. Store the results in the proper place.

— 7. Go back to step 1 to fetch the next instr.

6


Lecture 9

Register Set

Register set consists of all regs in the CPU that

are accessible to the programmer.

— The programmer-accessible portion of the reg file

— The program counter (PC)

— The processor status reg (PSR) -- C, N, V, Z

— The stack pointer (SP)

7


Lecture 9 Operand Addressing

Operand addressing:

— Implied address:

the opcode / the addr of other operand

— Explicit address: (See next)

# of operands with explicitly addresses:

— is an important factor in defining the ISA for a

computer

— E.g.: X = (A + B) (C + D)

X, A, B, C, D: memory addrs

ADD, SUB, MUL: arithmetic ops

LD, ST: data transfer between reg and mem

MOVE: data transfer between regs

8


Lecture 9

Three-address Instructions

E.g.: X = (A + B) (C + D)

ADD T1, A, B M[T1] M[A] + M[B]

ADD T2, C, D M[T2] M[C] + M[D]

MUL X, T1, T2 M[X] M[T1] M[T2]

or

ADD R1, A, B R1 M[A] + M[B]

ADD R2, C, D R2 M[C] + M[D]

MUL X, R1, R2 M[X] R1 R2

— Adv.: Short programs

— Disadv.: The binary coded instrs require more bits.

9


Lecture 9

Two-address Instructions

E.g.: X = (A + B) (C + D)

MOVE T1, A M[T1] M[A]

ADD T1, B M[T1] M[T1] + M[B]

MOVE X, C M[X] M[C]

ADD X, D M[X] M[X] + M[D]

MUL X, T1 M[X] M[X] M[T1]

— can use a temporary storage reg R1 to replace T1

10


Lecture 9

One-address Instructions

E.g.: X = (A + B) (C + D)

LD A ACC M[A]

ADD B ACC ACC + M[B]

ST X M[X] ACC

LD C ACC M[C]

ADD D ACC ACC + M[D]

MUL X ACC ACC M[X]

ST X M[X] ACC

— ACC: accumulator with implied address

11


Lecture 9

Zero-address Instructions

Stack: LIFO (last input first output ) queue

— TOS: top of the stack

— Data manipulation instrs: no regs or reg addrs used

E.g.: ADD TOS TOS + (TOS1)

— Data transfer: memory addressing

E.g.: PUSH X TOS M[X]

POP X M[X] TOS

(new)

12


Lecture 9

E.g.: X = (A + B) (C + D)

PUSH A TOS M[A]

PUSH B TOS M[B]

ADD TOS TOS + TOS1

PUSH C TOS M[C]

PUSH D TOS M[D]

ADD TOS TOS + TOS1

MUL TOS TOS TOS1

POP X M[X] TOS

— Adv.: Use no addressed memory locations or regs to

execute data manipulation instrs

— Disadv.: 8 instrs

13

Zero-address Instructions


Lecture 9

Addressing Architectures

Addressing architectures are determined by

— The # of operands addressed

— The # of addrs to the mem in the instrs

— The mem addrs restricted to specific instrs

Addressing architectures/schemes:

— Memory-to-memory architecture

— Register-to-register or load/store architecture

— Register-memory architecture

— Single-accumulator architecture

— Stack architecture

14


Lecture 9

Mem-mem arch:

— All operands come directly from mem & all results are

sent directly to memory.

— Architecture has only control regs in the CPU (not

used in new designs)

— Adv.: The instr count is low.

— Disadvs.: Many memory accesses the execution

time is potentially high.

E.g.: 3-addr m-m arch, X = (A + B)(C + D)

ADD T1, A, B M[T1] M[A] + M[B]

ADD T2, C, D M[T2] M[C] + M[D]

MUL X, T1, T2 M[X] M[T1] M[T2]

Memory-to-Memory Architecture

15


Lecture 9

Reg-to-reg or load/store arch:

— Allow only one memory addr & restrict its use to load and

store types of instrs

— Architecture requires a sizeable reg file in typical modern

processors.

— E.g.: 3-addr r-r, X = (A + B)(C + D)

LD R1, A R1 M[A]

LD R2, B R2 M[B]

ADD R3, R1, R2 R3 R1 + R2

LD R1, C R1 M[C]

LD R2, D R2 M[D]

ADD R1, R1, R2 R1 R1 + R2

MUL R1, R1, R3 R1 R1 R3

ST X, R1 M[X] R1

Register-to-register OR Load/Store Architecture

16


Lecture 9

Reg-mem arch:

— Include 2-/3-addr instrs with one/two of the addrs to

memory

— E.g.: 2-addr instr with a single memory addr allowed

ADD R1, A R1 R1 + M[A]

— Architecture remains prevalent among the current

ISA.

— Architecture primarily provides compatibility with

older software using a specific arch.

Register-Memory Architecture

17


Lecture 9

Single-accu arch:

— Its single addr is used for accessing memory.

— Architecture has no reg file (is used in CPUs for

simple, low-cost applications that do not require high

performance).

E.g.: X = (A + B) (C + D)

LD A ACC M[A]

ADD B ACC ACC + M[B]

ST X M[X] ACC

LD C ACC M[C]

ADD D ACC ACC + M[D]

MUL X ACC ACC M[X]

ST X M[X] ACC

7 instrs 21 mem accesses

Single-Accumulator Architecture

18


Lecture 9

Stack architecture:

— Data manipulation instrs use no addr.

— Single mem-addr load and store ops are used for data

transfer (PUSH & POP).

— Arch:

i. Previous: most of the stack is located in memory

(may place a few of the locations at the top of the

stack in regs).

ii. Recent: store substantial #s of stack locations in

the processor chip & handle transfer b/t these

locations and memory transparently.

Stack Architecture (1/4)

19


Lecture 9

E.g.: X = (A + B)(C + D)

PUSH A TOS M[A]

PUSH B TOS M[B]

ADD TOS TOS + TOS1

PUSH C TOS M[C]

PUSH D TOS M[D]

ADD TOS TOS + TOS1

MUL TOS TOS TOS1

POP X M[X] TOS

8 instrs

32 mem accesses (if entire stack is in mem)

20



Lecture 9

Stack architecture Postfix expression:

E.g.:

— (A + B) × C + (D × E) … infix notation

— A B + C × D E × + … postfix (reverse Polish) notation,

RPN.

PUSH A

PUSH B

ADD

PUSH C

MUL

PUSH D

PUSH E

MUL

ADD

21



Lecture 9

A B + C × D E × +

PUSH A

PUSH B

ADD

PUSH C

MUL

PUSH D

PUSH E

MUL

ADD

22



Lecture 9

Addressing Modes (1/2)

Addressing mode:

— Specify a rule for interpreting or modifying the addr

field of the instr before the operand is actually

referenced

— Effective addr (EA):

The addr of the operand produced by applying such a rule

— Provisions:

To give programming flexibility to the user via such

capabilities as pointers to memory, counters for loop

control, indexing of data, and relocation of programs

To reduce the # of bits in the addr fields of the instr

23


Lecture 9

The availability of various addressing modes:

— Adv.: Give the experienced programmer the ability to

write programs that require fewer instrs

— Disadv.: The effect on throughput and execution time

must be carefully weighed.

Specification of the addressing mode:

— Use a distinct binary code:

Addr field: mem addr or processor reg

— Use a common binary code for both the operand and

the addressing mode

24

Addressing Modes (2/2)


Lecture 9

Implied Mode/Immediate Mode

Implied mode:

— No addr field

— Operand(s) is specified implicitly in the opcode.

— E.g:

Complement accumulator

Data manipulation instrs in a stack computer

Immediate mode:

— The operand is specified in the instr itself.

Has an operand field rather than an addr field

— Usage: Initialize regs to a constant value

25


Lecture 9

Register Mode and Register-Indirect Modes

Reg mode:

— The operand field is specified by a processor reg,

i.e., the operands are in regs.

— No EA item

Reg-indirect mode:

— The selected reg contains the mem addr of the

operand.

— EA = Contents of the reg

— Adv.: Use fewer bits to select a reg than to specify a

memory address

26


Lecture 9

Direct Addressing Mode (1/2)

27

Direct addressing mode:

— In a data transfer or data manipulation instr:

The addr field gives the addr of the operand in memory.

EA = Addr part of the instr = the addr of the operand

E.g.: ACC M[ADRS]


Lecture 9

— In a branch type instr:

— The addr field is the branch addr.

E.g.: Branch if ACC = 0

28

Direct Addressing Mode (2/2)


Lecture 9

Indirect Addressing Mode

800

300

800 300

29

Indirect addressing mode:

— The addr field gives the addr where the EA is stored

in mem:

— EA = M[ADRS]

— E.g.: ACC M[M[ADRS]]


Lecture 9

Relative Addressing Mode (1/2)

752

30

Relative addressing mode:

— The position of the EA in mem is relative to the addr

of the next instr in the program:

— EA = Addr part of the instr (signed) + Contents of PC

— E.g.: ACC M[ADRS + PC]


Lecture 9

— Usage:

It is often used in branch type instrs when the

branch addr is in a location close to the instr word.

— Advs.:

Use less bits in program

Program is relocatable.

31

Relative Addressing Mode (2/2)


Lecture 9

Indexed Addressing Mode (1/2)

Indexed addressing mode:

— EA = Addr part of the instr (unsigned)

+ Contents of an index reg

— Index reg holds an index # relative to the addr field

— the addr field defines the beginning addr

Base-reg mode:

— EA = similar to that of indexed addressing mode

— Base reg holds a base addr.

— The addr field gives a displacement relative to the

base.

32


Lecture 9

E.g.:

ACC M[ADRS + R1]

9 - 6

Opcode: Load ACC

Mode: Index

ADRS: 500

Operation: ACC M[500 + 400]

ACC 200

33

Indexed Addressing Mode (2/2)


Lecture 9

Summary of Addressing Modes (1/2)

Example:

34


Lecture 9

#: Immediate [ ] or @: Indirect

$: PC relative ( ): Reg indirect or indexed

35

Summary of Addressing Modes (2/2)


Lecture 9

Instruction Set Architecture

Two major types of ISAs:

— Complex instr set computers (CISCs)

provide hardware support for high-level language ops and

have compact programs

— Reduced instr set computers (RISCs)

emphasize simple instrs and flexibility that provide higher

throughput and faster execution

36


Lecture 9

Properties: — Memory accesses are restricted to load and store instrs, and

data manipulation instrs are reg to reg.

— Addressing modes are limited in number.

— Instr formats are all of the same length.

— Instrs perform elementary ops.

Goal: High throughput & fast execution

Organization: — A relatively large reg file

— The control unit is comparatively simple and is typically

hardwired.

— The underlying organization is universally a pipeline design.

37

RISC Architecture


Lecture 9

Properties: — Memory is directly available to most types of instr.

— Addressing modes are substaintial in number.

— Instr formats are of different lengths.

— Instrs perform both elementary and comoplex ops.

Goal: — Match more closely the ops used in programming languages

— Provide instrs that facilitate compact programs and conserve

memory

Organization: — The reg files in a CISC are smaller than that in a RISC

— Microprogrammed control is often used

— A CISC instr a seq of RICS-like ops the RISC-like pipeline

38

CISC Architecture


Lecture 9

Data transfer instrs

— Cause data transfer from one location to another

without changing its contents

Data manipulation instrs

— Perform arithmetic, logic, and shift ops

Program control instrs

— Provide decision making capabilities and change the

path taken by the program

39

Category of Instructions


Lecture 9 Data Transfer Instructions

Typical data transfer instrs:

LD: reg mem

ST: mem reg

MOVE: reg reg

reg mem

mem reg

mem mem

XCH: reg reg

reg mem

mem mem

PUSH, POP (A.)

IN, OUT (B.)

40


Lecture 9 Stack Instructions (1/3)

Applications:

— The evaluation of arithmetic expressions

— The handling of procedure calls and returns and

interrupts

Stack pointer (SP): holds the addr for the stack

— always 1

Stack instrs:

— Transfer data between a mem stack and a processor

reg or mem

— Push: Place a new item onto the top of the stack

(TOS)

— Pop: Remove one item from the stack

41


Lecture 9

E.g.: A memory stack

— Assumptions: SP points to the top of the stack (TOS).

The stack grows by decrementing the mem addr

The items in the stack communicate with reg R1 or mem addr X

Push op 2 -ops:

SP SP 1

M[SP] R1

Pop op 2 -ops:

R1 M[SP]

SP SP + 1

42

Stack Instructions (2/3)


Lecture 9

The organization of a stack:

— Direction of stack growth:

decrementing or increasing the mem addr

— Location pointed at by SP:

at the TOS or at the next empty location above the top

Initialization of the SP:

— The SP is loaded with an initial value which is the

bottom addr of an assigned stack in mem.

Adv. of a mem stack:

— The processor can refer to it without having to specify

an addr.

43

Stack Instructions (3/3)


Lecture 9

Independent vs. Memory-Mapped I/O

I/O instr:

— transfer data between processor regs and I/O

devices

Port:

— A computer may have some I/O ports with one or

more ports dedicated to communicate with a specific

I/O device.

— Each port is equivalent to an external reg and is

addressable.

44


Lecture 9

Two ways to assign port addrs:

— Independent I/O: isolated I/O

The addr assigned to mem and I/O ports are independent

from each other.

Full addr ranges for both mem and I/O.

Require special instrs for I/O, e.g., IN, OUT.

— Mem-mapped I/O:

Assign a subrange of the mem addr for addressing I/O ports.

Each I/O port is regarded as a mem location.

The same instrs are used for manipulating both mem and I/O

data.

45

Independent vs. Memory-Mapped I/O


Lecture 9

Data Manipulation Instructions

Three basic types of data manipulation instrs:

— 1. Arithmetic instrs

— 2. Logical and bit manipulation instrs

— 3. Shift instrs

Instr v.s. -op:

— A -op is an elementary op executed by the hardware

of the computer under the control of the control unit.

— An instr is typically processed by executing a seq of

one or more -ops:

May involve several elementary ops that fetch the instr, bring

the operands from appropriate processor regs, and store the

result in the specified location.

46


Lecture 9 Arithmetic Instructions

Typical arithmetic instrs:

— , (, )

— Each may be available for different types of data

and precission.

47


Lecture 9

Logical and Bit Manipulation Instructions

Typical logical and bit manipulation instrs:

AND: mask, bit clear

OR: bit set

XOR: bit complement

48


Lecture 9 Shift Instructions

Typical shift instrs:

— Logical shifts

— Arithmetic shifts

— Rotations

Multiple-field format for the shift instr:

OP REG TYPE RL COUNT

49


Lecture 9 Floating-Point Computation (1/3)

Floating-point number:

— Two parts:

i. The sign of the number and a fraction:

Representation: e.g., sign-magnitude

Fraction (F), mantissa: precision

ii. The position of the radix point in the number:

Exponent (E): range

Representation: e.g., biased

Floating-point notation:

— Decimal number: F 10E

— Binary number: F 2E

— E.g.: + 6132.789 Fraction Exponent

+ .6132789 + 04

50


Lecture 9

E.g.: + 1001.11

— Assumptions:

Fraction: 8-bit, sign-magnitude, an invisible binary point right

after sign bit

Exponent: 6-bit with 2’s complement

+ 1001.11 = + (0.1001110)2 2+4 => Fraction Exponent

0.1001110 000100

Normalization:

— The most significant digit of the fraction is nonzero,

i.e., different from the sign bit

— Give maximum possible precision

Zero = 00 0 x r0

51

Floating-Point Computation (2/3)


Lecture 9

Tradeoff: range & precision

— E.g.: 48-bit number for signed integers:

— (247 1) 1014

— 48-bit number for floating-point numbers with 1-bit

sign, 35-bit F, 12-bit E:

— (1 2-35) 2+2047 10615

precision , range

52

Floating-Point Computation (3/3)


Lecture 9

Arithmetic Operations (1/2)

& :

— E.g:

.5372400 102 + .1580000 10-1

= .5372400 102 + .0001580 102 = .5373980 102

.56780 105 .56430 105

= .00350 105 = .35000 103

Alignment:

— i. Shift the fraction that has the smaller exponent to

the right by a # of places equal to the difference

between the exponents. may loss precision ()

— ii. Shift the fraction that has the greater exponent to

the left may cause error ()

53


Lecture 9

— Overflow: When two normalized fractions are added, the sum may

contain an overflow.

Correction: Sum shift right once & exponent + 1

— Normalization: Shift the fraction to the left and decrement the exponent until

a nonzero digit appears in the first position

— Algorithm: 1. Comparison of the exponents

2. Alignment of the exponent by shifting

3. Addition (or subtraction) of the mantissa

4. Normalization of the result

— & : Require no alignment of the radix point : Multiply the fractions & add the exponents

: Divide the fractions & subtract the exponents

54

Arithmetic Operations (2/2)


Lecture 9

Biased Exponent (1/4)

Biased exponent:

— Bias:

An excess number added to the exponent s.t. all exponents

0 no sign digit is needed for exponent.

The most negative exponent is a biased exponent with all 0’s.

— E.g.: The range of decimal exponents 99 ~ +99

E: The actual exponent, 99 ~ +99

e: The biased exponent, e = E + 99, 000 ~ 198

negative-biased exponents: 000 ~ 098

positive-biased exponents: 099 ~ 198

— Advs:

i. Positive exponents Simple exponent comparisons

ii. Floating-point number Zero =Zero fraction and a zero

biased exponent. 55


Lecture 9


Two standard formats:

i. Single precision (FS): 32 bits

ii. Double precision (FL): 64 bits

IEEE standard single-precision format:

s: 1 bit, the sign bit of the fraction

e: 8 bits, the biased exponent; use an excess 127 bias

f: 23 bits, the significand = 1.f , 1.0 ~ (2.0 223)

(normalized)

56


Lecture 9

— Evaluating biased exponents:

57



Lecture 9

A valid value: 0 < e < 255 (1)s 2e127 (1.f) — The most positive normalized number:

[0] [254] [11 1] = (1)0 2254127 (2 223 )

— The smallest positive normalized number:

[0] [1] [00 0] = (1)0 21127 (1.0 ) = + 2126

Special conditions:

— : e = 255 & f = 0

— NaN (not a number): e = 255 & f 0

— 0: e = 0 & f = 0

— Denormalized numbers: e = 0 & f 0

s e f

58



Lecture 9

Program Control Instruction (1/2)

Program control instr: — Change the addr value in

PC & alter the flow of control

— Branch & Jump: Usually a one address

instruction

May be conditional or unconditional

— Skip: Does not need address field

A conditional skip instruction will skip the next instruction if the specified condition is met.

59


Lecture 9

Program Control Instruction (2/2)

Program control instr: — Call & Return:

Used in conjunction with procedures

— Compare & Test: The compare instruction performs a comparison via a

subtraction, with the difference not retained.

The test instruction performs the logical AND of two operands without retaining the result.

The first type executes the entire decision as a single instruction.

For example, the contents of two registers can be compared and a branch or jump taken if the contents are equal. Two registers and one memory are required.

The second type of compare and test instruction also uses three addressed, all of which are register addresses.

The third type of compare and test, with the most complex structure, has compare and test operations that set or reset stored status bits. Branch and jump instructions are then used to conditionally change the program sequence.

60


Lecture 9

Conditional Branch Instructions (1/3)

Conditional branch instrs relating to a single

status bit:

61


Lecture 9

Conditional branch instrs used after a compare

instr (A B) :

— For unsigned numbers:

62



Lecture 9

— For signed numbers:

63



Lecture 9

Procedure Call and Return Instrs (1/3)

Procedure: subroutine

— A self-contained seq of instrs that performs a given

computational task

— Each time the procedure is called, a branch is made

to the beginning of the procedure to start executing its

set of instrs.

Call procredure instr: 1-addr field

— Two ops:

1. Store the return addr (available in PC) in a temporary

locations

2. The addr specified in the instr is loaded into the PC.

Transfer control to the beginning of the subroutine

64


Lecture 9

Return instr:

— The final instr in every procedure is a return to the

calling procedure.

— op:

Take the addr that was stored by the call procedure instr and

place it in the PC.

Transfer the program execution back to the continuation

point in the calling procedure.

Storage of return addrs:

i. A fixed memory location

ii. A processor reg

iii. A memory stack: nested procedure calls ()

65



Lecture 9

-ops for a procedure call instr using a memory

stack:

(without instr fetch phase)

SP SP 1 Decrement stack pointer

M[SP] PC Store return addr on stack

PC Effective addr Transfer control to procedure

-ops for a return instr using a stack:

(without instr fetch phase)

PC M[SP] Transfer return addr to PC

SP SP + 1 Increment stack pointer

66



Lecture 9

Types of Interrupts

Three types of interrupts:

— External interrupts: Initiated by hardware

Sources: I/O devices, timing devices, power supply monitor

Conditions:

An I/O device requesting a transfer of data

An external device completing a transfer of data

The time-out of an event

An impending power failure

— Internal interrupts: Traps, initiated by hardware

Sources: illegal or erroneous use of an instr or data

Conditions: Arithmetic overflow, divide by zero, Invalid opcode,

memory stack overflow, protection violation

— Software interrupts: Initiated by a special instr

E.g.: system calls 67


Lecture 9

Processing External Interrupts (1/3)

External interrupts:

— May have single or multiple interrupt input lines

— Two or more interrupt sources may be ORed and

then use a common interrupt input.

— An interrupt signal may originate at any time during

program execution.

— An interrupt request is acknowledged.

Only after the execution of the current instr is completed

and only if the state of the processor warrants it.

68


Lecture 9

— A simplified external interrupt configuration:

EI: Enable interrupt flip-flop, set or reset by instrs (EIN & DSI)

INTACK: Interrupt acknowledge

IVAD: Interrupt vector addr, may be a response to INTACK

69



Lecture 9

-ops that implement the interrupt: SP SP 1 Decrement stack pointer

M[SP] PC Store return addr on stack

SP SP 1 Decrement stack pointer

M[SP] PSR Store processor status word on stack

EI 0 Reset enable-interrupt flip-flop

INTACK 1 Enable interrupt acknowledge

PC IVAD Transfer interrupt vector addr to PC

Go to fetch phase.

Return from an interrupt:

— is done with an instr at the end of the service program

— is similar to a return from a procedure

— The stack is popped & the return addr is transferred to the PC.

70



Lecture 9

Summary (1/2)

The concept of instr set architecture (ISA):

— RISC

The components of an instr:

— Four types of addressing architecture:

Mem-mem, Reg-reg, Single-accu, Stack

— Addressing modes

Categories of elementary instrs:

— Data transfer

— Data manipulation

— Program control

71


Lecture 9

Interruption of the normal seq of program

execution:

— Types of interrupts:

External

Internal

Software

— Special processing actions:

The initiation of routines to service them

Return to execution of the interrupted programs

72

Summary (2/2)

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Instruction Set Architectureviplab.cs.nctu.edu.tw/course/DSD2015_Spring/DSD_Lecture... · 2015. 5. 15. · Digital Systems Design Lecture 9 Computer Architecture Two classes of computer