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FACULTY OF ENGINEERING

LAB SHEET

PROCESSING AND FABRICATION

TECHNOLOGY

EEN3106TRIMESTER II 2010-2011

PFT1 NMOS Processing Simulation

PFT2 PMOS Processing Simulation

*Note: On-the-spot evaluation will e carrie! out !uring or at the en! o" the e#periments$

%uestions regar!ing metal o#i!e semicon!uctor &MOS' !evice processing an!"arication( as well as !evice simulation will e as)e! !uring the evaluation$

Stu!ents are a!vise! to rea! through this la sheet e"ore !oing e#periment$ our

in!ivi!ual per"ormance !uring on-the-spot evaluation( participation in the la simulationwor)( teamwor) e""ort( an! learning attitu!e will count towar!s the la mar)s( in a!!ition

to the la report$

Please ring along +our ,S stic) "or !ata "iles saving purpose$

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INTRODUCTION:

.omplementar+ metalo#i!esemicon!uctor &.MOS' is a ma/or class o" integrate!circuits$ .MOS technolog+ is use! in chips such as microprocessors( microcontrollers(

static 0M( an! other !igital logic circuits$ .MOS technolog+ is also use! "or a wi!e

variet+ o" analog circuits such as image sensors( !ata converters( an! highl+ integrate!transceivers "or man+ t+pes o" communication$ .MOS is also sometimes e#plaine! as

complementar+-s+mmetr+ metalo#i!esemicon!uctor$ The wor!s complementar+-

s+mmetr+ re"er to the "act that the t+pical !igital !esign st+le with .MOS usescomplementar+ an! s+mmetrical pairs o" p-t+pe an! n-t+pe MOSF3Ts "or logic

"unctions$ Two important characteristics o" .MOS !evices are high noise immunit+ an!

low static power suppl+ !rain$ Signi"icant power is onl+ !rawn when its transistors are

switching etween on an! o"" states4 conse5uentl+( .MOS !evices !o not pro!uce asmuch heat as other "orms o" logic such as TT6 &transistor-transistor logic'$ .MOS also

allows a high !ensit+ o" logic "unctions on a chip$

7n this simulation( the "un!amentals o" MOS chip "arication will e !iscusse! an! thema/or steps o" the process "low will e e#amine!$ The emphasis will e on the general

outline o" the process "low an! on the interaction o" various processing steps( whichultimatel+ !etermine the !evice an! the circuit per"ormance characteristics$ This

simulation shows that there are ver+ strong lin)s etween the "arication process an! the

!evice per"ormance$ 8ence( the circuit !esigner must have a wor)ing )nowle!ge o" chip"arication to create e""ective !esigns an! to optimi9e the circuits with respect to various

manu"acturing parameters$

The "ollowing !iscussion will concentrate on the well-estalishe! .MOS "aricationtechnolog+( which re5uires that oth the n-channel &nMOS' an! p-channel &pMOS'

transistors e uilt on the same chip sustrate$ To accommo!ate oth nMOS an! pMOS

!evices( special regions must e create! in which the semicon!uctor t+pe is opposite tothe sustrate t+pe$ These regions are calle! wells or tus$ p-well is create! in an n-t+pe

sustrate or( alternativel+( an n- well is create! in a p-t+pe sustrate$ 7n the simple n-well

.MOS "arication technolog+ presente!( the nMOS transistor is create! in the p-t+pesustrate( an! the pMOS transistor is create! in the n-well( which is uilt-in into the p-

t+pe sustrate$ 7n the twin-tu .MOS technolog+( a!!itional tus o" the same t+pe as the

sustrate can also e create! "or !evice optimi9ation$

The simpli"ie! process se5uence "or the "arication o" .MOS integrate! circuits on a p-

t+pe silicon sustrate is shown in Fig$ 1$ The process starts with the creation o" the n-well

regions "or pMOS transistors( + impurit+ implantation into the sustrate$ Then( a thic)o#i!e is grown in the regions surroun!ing the nMOS an! pMOS active regions$ The thin

gate o#i!e is suse5uentl+ grown on the sur"ace through thermal o#i!ation$ These steps

are "ollowe! + the creation o" n an! p regions &source( !rain an! channel-stopimplants' an! + "inal metalli9ation &creation o" metal interconnects'$

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Figure-1: Simpli"ie! process se5uence "or "arication o" the n-well .MOS integrate!

circuit with a single pol+silicon la+er( showing onl+ ma/or "arication steps$

The process "low se5uence picture! in Fig$1 ma+ at "irst seem to e too astract( since

!etaile! "arication steps are not shown$ To otain a etter un!erstan!ing o" the issues

involve! in the semicon!uctor "arication process( we "irst have to consi!er some o" theasic steps in more !etail$

Fabria!i"# Pr"$%% F&"' - Ba%i S!$(%

The integrate! circuit ma+ e viewe! as a set o" patterne! la+ers o" !ope! silicon(

pol+silicon( metal an! insulating silicon !io#i!e$ 7n general( a la+er must e patterne!e"ore the ne#t la+er o" material is applie! on chip$ The process use! to trans"er a pattern

to a la+er on the chip is calle! lithograph+$ Since each la+er has its own !istinct

patterning re5uirements( the lithographic se5uence must e repeate! "or ever+ la+er(

using a !i""erent mas)$

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To illustrate the "arication steps involve! in patterning silicon !io#i!e through optical

lithograph+( let us "irst e#amine the process "low shown in Fig$ 2$ The se5uence starts

with the thermal o#i!ation o" the silicon sur"ace( + which an o#i!e la+er o" aout 1micrometer thic)ness( "or e#ample( is create! on the sustrate &Fig$ 2&''$ The entire

o#i!e sur"ace is then covere! with a la+er o" photoresist( which is essentiall+ a light-

sensitive( aci!-resistant organic pol+mer( initiall+ insolule in the !eveloping solution&Fig$ 2&c''$ 7" the photoresist material is e#pose! to ultraviolet &,

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Fi)*r$-2: Process steps re5uire! "or patterning o" silicon !io#i!e$

The t+pe o" photoresist which is initiall+ insolule an! ecomes solule a"ter e#posure to

,< light is calle! positive photoresist$ The process se5uence shown in Fig$ 2 usespositive photoresist$ There is another t+pe o" photoresist which is initiall+ solule an!

ecomes insolule &har!ene!' a"ter e#posure to ,< light( calle! negative photoresist$ 7"

negative photoresist is use! in the photolithograph+ process( the areas which are notshiel!e! "rom the ,< light + the opa5ue mas) "eatures ecome insolule( whereas the

shiel!e! areas can suse5uentl+ e etche! awa+ + a !eveloping solution$ Negative

photoresists are more sensitive to light( ut their photolithographic resolution is not as

high as that o" the positive photoresists$ There"ore( negative photoresists are use! lesscommonl+ in the manu"acturing o" high-!ensit+ integrate! circuits$

Following the ,< e#posure step( the une#pose! portions o" the photoresist can eremove! + a solvent$ Now( the silicon !io#i!e regions which are not covere! +

har!ene! photoresist can e etche! awa+ either + using a chemical solvent &8F aci!' or

+ using a !r+ etch &plasma etch' process &Fig$ 2&e''$ Note that at the en! o" this step( weotain an o#i!e win!ow that reaches !own to the silicon sur"ace &Fig$ 2&"''$ The

remaining photoresist can now e strippe! "rom the silicon !io#i!e sur"ace + using

another solvent( leaving the patterne! silicon !io#i!e "eature on the sur"ace as shown in

Fig$ 2&g'$

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The se5uence o" process steps illustrate! in !etail in Fig$ 2 actuall+ accomplishes a single

pattern trans"er onto the silicon !io#i!e sur"ace( as shown in Fig$ ;$ The "arication o"

semicon!uctor !evices re5uires several such pattern trans"ers to e per"orme! on silicon!io#i!e( pol+silicon( an! metal$ The asic patterning process use! in all "arication steps(

however( is 5uite similar to the one shown in Fig$ 2$ lso note that "or accurate

generation o" high-!ensit+ patterns re5uire! in su-micron !evices( electron eam &3-eam' lithograph+ is use! instea! o" optical lithograph+$ 7n the "ollowing section( the

main processing steps involve! in the "arication o" an n-channel MOS transistor on p-

t+pe silicon sustrate will e e#amine!$

Fi)*r$-3: The result o" a single lithographic patterning se5uence on silicon!io#i!e( without showing the interme!iate steps$ .ompare the unpatterne! structure &top'

an! the patterne! structure &ottom' with Fig$ 2&' an! Fig$ 2&g'( respectivel+$

The process starts with the o#i!ation o" the silicon sustrate &Fig$ =&a''( in which a

relativel+ thic) silicon !io#i!e la+er( also calle! "iel! o#i!e( is create! on the sur"ace&Fig$ =&''$ Then( the "iel! o#i!e is selectivel+ etche! to e#pose the silicon sur"ace on

which the MOS transistor will e create! &Fig$ =&c''$ Following this step( the sur"ace is

covere! with a thin( high-5ualit+ o#i!e la+er( which will eventuall+ "orm the gate o#i!eo" the MOS transistor &Fig$ =&!''$ On top o" the thin o#i!e( a la+er o" pol+silicon

&pol+cr+stalline silicon' is !eposite! &Fig$ =&e''$ Pol+silicon is use! oth as gate electro!e

material "or MOS transistors an! also as an interconnect me!ium in silicon integrate!circuits$ ,n!ope! pol+silicon has relativel+ high resistivit+$ The resistivit+ o" pol+silicon

can e re!uce!( however( + !oping it with impurit+ atoms$

"ter !eposition( the pol+silicon la+er is patterne! an! etche! to "orm the interconnects

an! the MOS transistor gates &Fig$ =&"''$ The thin gate o#i!e not covere! + pol+silicon isalso etche! awa+( which e#poses the are silicon sur"ace on which the source an! !rain

/unctions are to e "orme! &Fig$ =&g''$ The entire silicon sur"ace is then !ope! with a high

concentration o" impurities( either through !i""usion or ion implantation &in this case with!onor atoms to pro!uce n-t+pe !oping'$ Figure =&h' shows that the !oping penetrates the

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e#pose! areas on the silicon sur"ace( ultimatel+ creating two n-t+pe regions &source an!

!rain /unctions' in the p-t+pe sustrate$ The impurit+ !oping also penetrates the

pol+silicon on the sur"ace( re!ucing its resistivit+$ Note that the pol+silicon gate( which ispatterne! e"ore !oping actuall+ !e"ines the precise location o" the channel region an!(

hence( the location o" the source an! the !rain regions$ Since this proce!ure allows ver+

precise positioning o" the two regions relative to the gate( it is also calle! the sel"-aligne!process$

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Fi)*r$-+: Process "low "or the "arication o" an n-t+pe MOSF3T on p-t+pe silicon$

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Once the source an! !rain regions are complete!( the entire sur"ace is again covere! with

an insulating la+er o" silicon !io#i!e &Fig$ =&i''$ The insulating o#i!e la+er is then

patterne! in or!er to provi!e contact win!ows "or the !rain an! source /unctions &Fig$=&/''$ The sur"ace is covere! with evaporate! aluminum which will "orm the interconnects

&Fig$ 2$=&)''$ Finall+( the metal la+er is patterne! an! etche!( completing the

interconnection o" the MOS transistors on the sur"ace &Fig$ =&l''$ ,suall+( a secon! &an!thir!' la+er o" metallic interconnect can also e a!!e! on top o" this structure + creating

another insulating o#i!e la+er( cutting contact &via' holes( !epositing( an! patterning the

metal$

The schematic cross-section o" a simple .MOS inverter circuit constitute! + an n-

channel MOS transistor an! a p-channel MOS transistor is shown in Fig$ > elow$ The

.MOS integrate! circuit can e accomplishe! + "aricating the n-channel an! p-channelMOS !evices on the same sustrate( "ollowing the "arication processes !iscusse! in Fig$

1-=$

Fi)*r$-,: Schematic cross-section o" a .MOS inverter constitute! + an n-channel MOS

transistor an! a p-channel MOS transistor$

References:8ou!a Braoui an! mir l-a+ati( ccurac+ o" Coping an! Process Optimi9ation "or

D$1Aum PMOS technolog+( 7333$ 7on 7mplantation Tech$( pg$1AE-1E2( 2DD2

0e"erences$ Mal+( tlas o" 7. Technologies( Menlo Par)( .: en/aminG.ummings( 1EA@$

$ S$ Brove( Ph+sics an! Technolog+ o" Semicon!uctor Cevices( New or)( N: Hohn

ile+ I Sons( 7nc$( 1E?@$

B$ 3$ nner( Planar Processing Primer( New or)( N:

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PFT1 NMOS Pr"$%%i#) Si.*&a!i"#

OB/ECTIES:

To !esign D$>DJm NMOS

To anal+9e NMOS 7-< curves un!er !i""erent in"luent "actors

SIMULATION SOFTARE:

Silvaco T.C

METHODOLOGY:

asic MOS T83N to T6S inter"ace e#ample simulating an 7!G

operator o" particular use in NMOS !evice e#traction is ab%4$ This ta)es the asolute

value o" a variale an! can e use! to ma)e all PMOS an! NMOS e#tractions e5uivalent$

Par! A: Si.*&a!i"# "5 !$ $i%!i#) NMOS $a.(&$

1$ Coule clic) on L!ec)uil! icon$2$ 0ight clic) on LMain .ontrol an! choose L3#amples$;$ Coule clic) on L1 MOS1: MOS pplication 3#amples$

=$ From the e#amples( !oule clic) on L1$1 mos1e#D1$in:NMOS: 7!G

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1D$ 7n +our report( s)etch the 7!G

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PFT2 PMOS Pr"$%%i#) Si.*&a!i"#

OB/ECTIES:

To !esign D$>DJm PMOS To anal+9e PMOS 7-< curves un!er !i""erent in"luent "actors

SIMULATION SOFTARE:

Silvaco T.C

METHODOLOGY:

asic MOS T83N to T6S inter"ace e#ample simulating an 7!G

operator o" particular use in PMOS !evice e#traction is ab%4$ This ta)es the asolute

value o" a variale an! can e use! to ma)e all PMOS an! NMOS e#tractions e5uivalent$

Par! A: Si.*&a!i"# "5 !$ $i%!i#) PMOS $a.(&$

1$ Coule clic) on L!ec)uil! icon$2$ 0ight clic) on LMain .ontrol an! choose L3#amples$;$ Coule clic) on L1 MOS1: MOS pplication 3#amples$

From the e#amples( !oule clic) on L1$A mos1e#DA$in:PMOS: 7!G$ From the trace in mi!!le( clic) Lrun to simulate the e#ample$?$ "ter a while( PMOS structure an! its 7!G

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E$ 7n +our report( s)etch the 7!G Qm n-t+pe or p-t+pe metal o#i!e

"iel! e""ect transistor &MOSF3T'$

;$ ou are e#pecte! to evaluate the D$2> Qm n-t+pe or p-t+pe MOSF3T per"ormancein terms o" !evice characteristics such as suthreshol! slope( threshol! voltage an!

charge carrier moilit+$

=$ ase! on +our evaluations( compare the !evice per"ormance o" the D$2> Qm n-t+peor p-t+pe metal o#i!e "iel! e""ect transistor &MOSF3T' with that o" a D$>D Qm

MOSF3T$

>$ Ciscuss +our comparison results$

Mari#) S$.$

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Lab

10;4

A%%$%%.$#!

C".("#$#!%

D$!ai&%

8an!s-On I 3""orts&2R'

The han!s-on capailit+ o" the stu!ents an! their e""orts!uring the la sessions will e assesse!$

On the Spot3valuation &2R'

The stu!ents will e evaluate! on the spot ase! on thela e#periments an! the oservations on the !evice

characteristics$

6a 0eport

&?R'

3ach stu!ent will have to sumit hisGher la "inal report

within 1D !a+s o" per"orming the la e#periment PFT2$

The report shoul! cover the "ollowings:

1$ 7ntro!uction( which inclu!es ac)groun!in"ormation on monolithic integrate! MOSF3Ts

processing an! !evice simulation$

2$ 3#perimental section( which inclu!es the generalsummar+ o" the la e#periment wor) in PFT1

an! PFT2$;$ 0esults an! Ciscussions( which inclu!e the

!evice simulation results( anal+sis( an!

evaluations( with neat graphsGimages o" the

results an! recor!e! !ata( as well as the

!iscussion on the !evice !esign o" the D$2> an!D$>D Qm MOSF3Ts$

=$ .onclusion( which inclu!es a conclusion on the

e#perimental an! !esign wor)$>$ 6ist o" 0e"erences( which inclu!es all the

technical re"erences cite! throughout the entire

la report$

The report must have re"erences ta)en "rom online

scienti"ic /ournals &e$g$ www$science!irect$com(http:GGieee#plore$ieee$orgG#plGperio!icals$/sp(

http:GGwww$aip$orgGpusG' an!Gor con"erence procee!ings

&e$g$http:GGieee#plore$ieee$orgG#plGcon"erences$/sp'$

Format o" re"erences: The re"erences to scienti"ic

/ournals an! te#t oo)s shoul! "ollow the "ollowing

stan!ar! "ormat:

3#amples:1 illiam U( unte 3( Stieig 8( Unipp C(

7n"luence o" low temperature thermal annealing onthe per"ormance o" microcr+stalline silicon thin-"ilm

transistors( Hournal o" pplie! Ph+sics( 2DD@( 1D1( p$

D@=>D;$

2 8o!ges C( Hac)son 8B( nal+sis an! !esign o"!igital integrate! circuits( New or)( McBraw-8ill

1=

http://www.sciencedirect.com/http://ieeexplore.ieee.org/xpl/periodicals.jsphttp://www.aip.org/pubs/http://ieeexplore.ieee.org/xpl/conferences.jsphttp://ieeexplore.ieee.org/xpl/conferences.jsphttp://www.sciencedirect.com/http://ieeexplore.ieee.org/xpl/periodicals.jsphttp://www.aip.org/pubs/http://ieeexplore.ieee.org/xpl/conferences.jsp

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oo) .ompan+( 1EA;( p$ @?$

0eports must e t+pe! an! single-space!( an! a!opt a

12-point Times New 0oman "ont "or normal te#ts in the

report$

n+ stu!ent "oun! plagiari9ing their reports will havethe assessment mar)s "or this component &?R' "or"eite!$

The la report has to e sumitte! to the

Nanotechnolog+ la sta""$ Please ma)e sure +ou sign the

stu!ent list "or +our sumission$ No plagiarism is

allowe!$ Though the transistor structures an! the7!sG