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8/16/2019 LAsdsd 9docx
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Laporan Akhir
I.Data pengamatan
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
eniy !"#nr#ller_"#$e is
%#r & "l'(rs ) in STD_LOGIC;
Green(Re$( *ell#+ ) #u STD_LOGIC,;
en$ !"#nr#ller_"#$e;
ar"-ie"ure e-a/i#ral #! !"#nr#ller_"#$e is
si0nal "#un)ine0er ran0e # 1 )2 ;
si0nal sae)ine0er ran0e # 3 )2 ;
be0in
r#"ess&"l'( rs,
be0in
i!&rs 2 515, -en
sae 2 ;
Re$ 2 515;
Green 2 55;
*ell#+ 2 55;
"#un 2 ;
elsi! "l'5e/en an$ "l'2515 -en
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"ase sae is
+-en 27 88 Re$ Li0-
i!&"#un29, -en
"#un 2 ;
sae 2 1;
else
"#un 2 &"#un : 1,;
Re$ 2 515;
Green 2 55;
*ell#+ 2 55;
en$ i!;
+-en 1 27 88Green Li0-
i!&"#un29, -en
"#un 2 ;
sae 2 3;
else
"#un 2 "#un : 1;
Re$ 2 55;
Green 2 515;
*ell#+ 2 55;
en$ i!;
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+-en 3 27 88*ell#+ Li0-
i!&"#un23, -en
"#un 2 ;
sae 2 ;
else
"#un 2 "#un : 1;
Re$ 2 55;
Green 2 55;
*ell#+ 2 515;
en$ i!;
+-en #-ers 27
sae 2 ;
"#un 2 ;
en$ "ase;
en$ i!;
en$ r#"ess;
en$ e-a/i#ral;
II.Analisis
%a$a %ra'i'u 'ali ini ra'i'an ela'u'an er"#baan enan0 ali'asi traffic
light $en0an eneraan /-$l.Inu $ala er"#baan ini a$ala- "l' $an rs .Rs $isini
a$ala- rese a$a 'asus ini a'an en0ebali'an 'e '#n$isi a+al yaiu 'ei'a red
enyala se$an0'an yellow $an green a'an ai.Disini
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yaiu unu' enenu'an 'ea$aan asin08asin0 lau.Disini a$a = state yan0
$i0una'an ya'ni state (1($an 3.%r#ses 'ali ini -anya $i'ena'an unu' inu sa
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V.Refrensi
• -)@@-#e.a0-.e$u.l@#sr#+s'@e'sy@B4ls4B.$! &$ia'ses a$a an00al 19
ei 316 u'ul 1=.=,
• -)@@+++."see.ub".e$u@#ral@-el@HDL@"#n"urren.-l &$ia'ses a$a
an00al 19 ei 316 u'ul 1=.49,
• -s)@@+eb$#"s."s.ualbera."a@aaral@"#urses@=3@labs@HDL_Re!eren"e.-l
&$ia'ses a$a an00al 19 ei 316 u'ul 14.,
http://home.agh.edu.pl/~ostrowsk/teksty/74ls47.pdfhttp://www.csee.umbc.edu/portal/help/VHDL/concurrent.htmlhttps://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.htmlhttp://www.csee.umbc.edu/portal/help/VHDL/concurrent.htmlhttps://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.htmlhttp://home.agh.edu.pl/~ostrowsk/teksty/74ls47.pdf