Lect10_Analog Layout and Process Concern

Analog Layout and Process Concern

授課教師 : 顏志仁博士

• Introduction

• Integrated-Circuit Devices and Modeling

• Modern CMOS Process

• Analog Layout Considerations

• SPICE Simulation

Contents

References

I. P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, 2002.

II. D. A. Johns and K. Martin, “Analog Integrated Circuit Design”, John Wiely & Sons, 1997.

III. R. Gregorian, “Introduction to CMOS Op-Amps and Comparators”, John Wiely & Sons, 1999.

Analog Layout and Process Concern

Introduction

Analog Integrated Circuits

1

Reference : J.-T. Wu, Analog Integrated Circuits.

C.–J. Yen

Major Functions of Analog ICs

• Provide interfaces between the analog environment of the physical world and a digital environment.

– amplification

– filtering

– analog-to-digital conversion

– digital-to-analog conversion

– power supply conditioning

• Sometimes integrated with digital VLSI circuits for better performance or lower cost.

Introduction

2C.–J. Yen Analog Layout and Process Concern

Signals

• An analog signal is defined over a continuous range of time and a continuous range of amplitudes.

• A digital signal is defined only at discrete values of time and amplitude. D = b12-1+ b22-2 +b32-3 + ·····bN2-N =

• An analog sampled-data signal is defined over a continuous range of amplitudes but only at discrete values of time.

N

i

iib

1

2

Introduction


Bandwidths of Signals

Introduction


Signal Bandwidths can be Processed

Introduction


Digitization of a Nature Signal

Introduction


Symbols for MOS Transistors

Integrated-Circuit Devices and Modeling

Commonly used symbols for p-channel transistors.

Commonly used symbols for n-channel transistors.


Cross Section of a MOS Transistor

8


A cross section of a typical n-channel transistor.

C.–J. Yen Analog Layout and Process Concern

N-Channel MOS Transistor (VG << 0)

9


VG << 0 resulting in an accumulated channel (no current flow).


N-Channel MOS Transistor (VG >> 0)

10


The channel is present (current flow possible from drain to source).


Dimensions of a MOS Transistor

11



Channel Charge Density

12



Pinch Off

13



ID-VDS Curve for a MOS Transistor

14



ID-VDS Curve for Different VGS

15



Weak Inversion

16


nkT

qV

DOD

G

eIL

Wi

)( kT

qV

kT

qV

nkT

qV

DOD

DSG

eeeIL

Wi

if 1kT

qVD and

then

0SV

is a characteristic currentDOI


Moderate Inversion

17


)()1(2)()1( 22ghighthPglowthgs VVtVttVVtV

dshighPdslowds ItIttItI 22 )1(2)1(


Transfer Characteristics of Temperature

18



Small-Signal Capacitances

19



Small-Signal Model in Active Region

20



MOS Transistor Equations in Active Region

21



Small-Signal Model in Triode Region

22



MOS Transistor Equations in Triode Region

23



MOS Parameters for a 0.8-μm Technology

24



SPICE Parameters for Modeling BJTs

25



Simple CMOS Logic Circuits

26

Modern CMOS Process


Cross Section of the CMOS IC

27

Modern CMOS Process


SiO2 and Si3 N4

28

Modern CMOS Process

• Following initial cleaning, an SiO2 layer is thermally grown on the silicon substrate. A Si3N4 layer is then deposited by LPCVD. Photoresist is spun on the wafer to prepare for mask 1 operation.


Mask 1

29

Modern CMOS Process

• Mask 1 patterns the photoresist. The Si3N4 layer is removed where it is not protected by the photoresist by dry etching.


Field Oxide

30

Modern CMOS Process

• After photoresist stripping, the field oxide is grown in an oxidizing ambient.


Mask 2

31

Modern CMOS Process

• Photoresist is used to mask the regions where PMOS devices will be built using mask 2. A boron implant provides the doping for the P wells for the NMOS devices.


Mask 3

32

Modern CMOS Process

• Photoresist is used to mask the regions where NMOS devices will be built using mask 3. A phosphorus implant provides the doping for the N wells for the PMOS devices.


N and P Wells

33

Modern CMOS Process

• A high temperature drive-in completes the formation of the N and P wells.


Mask 4

34

Modern CMOS Process

• After spinning photoresist on the wafer, mask 4 is used to define the NMOS transistors. A boron implant adjusts the N-channel VTH.


Mask 5

35

Modern CMOS Process

• After spinning photoresist on the wafer, mask 5 is used to define the PMOS transistors. A arsenic implant adjusts the P-channel VTH.


Polysilicon Gate

36

Modern CMOS Process

• A layer of polysilicon is deposited. Ion implantation of phosphorus follows the deposition to heavily dope the poly.


Mask 6

37

Modern CMOS Process

• Photoresist is applied and mask 6 is used to define the regions where MOS gates are located. The polysilicon layer is then etched using plasma etching.


Mask 7

38

Modern CMOS Process

• Mask 7 is used to cover the PMOS devices. A phosphorus implant is used to form the tip or extension (LDD) regions in the NMOS devices.


Mask 8

39

Modern CMOS Process

• Mask 8 is used to cover the NMOS devices. A boron implant is used to form the tip or extension (LDD) regions in the PMOS devices.


Sidewall of Polysilicon

40

Modern CMOS Process

• The deposited SiO2 layer is etched back anisotropically, leaving sidewall spacers along the edges of the polysilicon.


Mask 9

41

Modern CMOS Process

• After growing a thin “screen” oxide, photoresist is applied and mask 9 is used to protect the PMOS transistors. An arsenic implant then forms the NMOS source and drain regions.


Mask 10

42

Modern CMOS Process

• After applying photoresist, mask 10 is used to protect the NMOS transistors. A boron implant then forms the PMOS source and drain.


Coating of Ti

43

Modern CMOS Process

• An unmasked oxide etch removes the SiO2 from the devices source drain regions and form the top surface of the polysilicon. Titanium is deposited on the wafer surface by sputtering.


TiSi2 and TiN

44

Modern CMOS Process

• The titanium is reacted in an N2 ambient, forming TiSi2 where it contacts silicon or polysilicon (black regions in the figure) and TiN elsewhere.


Mask 11

45

Modern CMOS Process

• Photoresist is applied and mask 11 is used to define the regions where TiN local interconnects will be used. The TiN is then etched.


SiO2 Deposited and Planarized

46

Modern CMOS Process

• After stripping the photoresist, a conformal SiO2 layer is deposited by LPCVD. Chemical-Mechanical Polishing (CMP) or resist etchback is used to polish or etchback the deposited SiO2 layer. This planarizes the wafer surface.


Mask 12

47

Modern CMOS Process

• Photoresist is spun onto the wafer. Mask 12 is used to define the contact holes. The

deposited SiO2 layer is then etched to allow connections to the silicon, polysilicon and local interconnect regions.


TiN/W Deposited and Planarized

48

Modern CMOS Process

• A thin TiN layer is deposited on the wafer by sputtering, followed by deposition of a W layer by CVD. CMP is used to polish back the W and TiN layer, leaving a planar surface on which the first level metal can be deposited.


Mask 13

49

Modern CMOS Process

• Aluminum is deposited on the wafer by sputtering. Photoresist is spun on the wafer and mask 13 is used to define the first level of metal. The Al is then plasma etched.


Masks 14/15/16

50

Modern CMOS Process

• The steps to form the second level of Al interconnect follow those in 1-55 to 1-58. Mask 14 is used to define via holes between metal 1 and metal 2. Mask 15 is used to define metal 2. The last step in the process is deposition of a final passivation layer, usually Si3N4 deposited by PECVD. The last mask 16 is used to open holes in this mask over the bonding pad.


MOS Transistor

51

Analog Layout Considerations


Parallel Transistors

52


• Node 1 should be connected to the more critical node.

• To minimize voltage drops due to silicon-junction resistivity.


Weight Current Cell Layout

53



Current Mirror Layout Technique (I)

54



Current Mirror Layout Technique (II)

55



Current Mirror Layout Technique (III)

56



Current Mirror Layout Technique (IV)

57



Current Mirror Layout Technique (V)

58



Serious-Connected Transistors

59



CMOS Inverter

60



Input Transistors

61



Cross-Coupled Transistors

62


• Offsets can be minimized.

• Minimum bends and corners in transistors to be matched.


Common-Centroid Layout

63


• Reducing errors caused by gradient effects.

• Dummy fingers are used for better matching accuracy.


Input Stages of Op-Amp

64



Layout Floor Plan for a Two-Stage Op-Amp

65



Integrated Resistor

66


• The contact contributes 0.14 squares.

• Each bend contributes 2.11 squares.


Accurate Resistor Ratios

67


• Reducing errors caused by R1/R2 contact impedance.

• Matching boundary conditions with dummy fingers.


Resistor Matching

68



Resistor Layout Technique (I)

69



Resistor Layout Technique (II)

70



Resistor Layout Technique (III)

71



Resistor Layout Technique (IV)

72



R-string Layout (I)

73



R-string Layout (II)

74



Integrated Capacitor (I)

75



Integrated Capacitor (II)

76



Capacitor Array (I)

77


• Boundary-condition matching.

• The top plate should be connect to critical nodes.


Capacitor Array (II)

78



Capacitor Array (III)

79



BJT Layout (I)

80



BJT Layout (II)

81



Shielding

82


• To keep noise from being coupled into and out of the substrate.


Signal Line Shielding

83



Guard Rings

84


• Minimizing the injection of noise into the substrate.


Decoupling

85



Separate Power Supplies

86


• Preventing the digital noise coupling.

• To minimize substrate noise.


Layout of a Two-Stage Op-Amp

87



Layout of a Cascode Op-Amp

88



Layout Floor Plan for Switched-Capacitor Circuits

89



Latch-Up

90


• The equivalent circuit of the parasitic bipolar transistors.

• The voltages after latch-up has occurred.


Critical Layout Issues


• RC Delay

• Signal coupling

• Device matching

• Parasitic capacitance

• Noise considerations

• Latch-up

C.–J. Yen 91Analog Layout and Process Concern

SPICE Simulation

Simulation of a Common-Source Gain Stage


SPICE Simulation

Simulation of the Common-Source Gain Stage with a

Capacitive Load


SPICE Simulation

Simulation of a Source Follower


SPICE Simulation

Step Response of a Source Follower


SPICE Simulation

Simulation of the Source Follower with aCompensation Circuit


SPICE Simulation

Simulation of the Cascode Gain Stage


Documents

Lect10_Analog Layout and Process Concern