Ltc 1968 datasheet

7/27/2019 Ltc 1968 datasheet

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LTC1968

1968f

Precision Wide Bandwidth,RMS-to-DC Converter

High Linearity:0.02% Linearity Allows Simple System Calibration

Wide Input Bandwidth:Bandwidth to 1% Additional Gain Error: 500kHzBandwidth to 0.1% Additional Gain Error: 150kHz3dB Bandwidth Independent of Input VoltageAmplitude

No-Hassle Simplicity:True RMS-DC Conversion with Only One ExternalCapacitor

Delta Sigma Conversion Technology Ultralow Shutdown Current:

0.1A Flexible Inputs:

Differential or Single EndedRail-to-Rail Common Mode Voltage RangeUp to 1VPEAKDifferential Voltage

Flexible Output:Rail-to-Rail OutputSeparate Output Reference Pin Allows Level Shifting

Small Size:

Space Saving 8-Pin MSOP Package

True RMS Digital Multimeters and Panel Meters True RMS AC + DC Measurements

DESCRIPTIO UFEATURES

APPLICATIO SU

The LTC1968 is a true RMS-to-DC converter that uses ainnovative delta-sigma computational technique. The beefits of the LTC1968 proprietary architecture, when compared to conventional log-antilog RMS-to-DC converteare higher linearity and accuracy, bandwidth independeof amplitude and improved temperature behavior.

The LTC1968 operates with single-ended or differential iput signals and accurately supports crest factors up to 4.Common mode input range is rail-to-rail. Differential iput range is 1VPEAK, and offers unprecedented linearity. TheLTC1968 allows hassle-free system calibration at any input voltage.

The LTC1968 has a rail-to-rail output with a separate ouput reference pin providing flexible level shifting; it opates on a single power supply from 4.5V to 5.5V. A low powshutdown mode reduces supply current to 0.1A.

The LTC1968 is packaged in the space-saving MSOP pacage, which is ideal for portable applications.

Single Supply RMS-to-DC Converter

CAVE10F VOUT

+

1968 TA01

4.5V TO 5.5V

OUTPUTDIFFERENTIAL

INPUTLTC1968

V+

0.1FOPT. AC

COUPLING

EN GNDOUT RTN

IN1

IN2

TYPICAL APPLICATIO U

VIN(mV ACRMS)0

1.0 L I N E A R I T Y E R R O R ( V

O U T m

V D C

V I

N m

V A C

R M S

)

0.8

0.6

0.4

0.2

0

0.2

100 200 300 4001968 TA01b

500

LTC1968,

60Hz SINEWAVE

CONVENTIONALLOG/ANTILOG

Linearity Performance

, LTC and LT are registered trademarks of Linear Technology Corporation.Protected under U.S. Patent Numbers 6,359,576, 6,362,677 and 6,516,291


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Supply VoltageV+ to GND............................................................. 6V

Input Currents (Note 2) .....................................10mAOutput Current (Note 3).....................................10mAENABLE Voltage ......................................... 0.3V to 6VOUT RTN Voltage ........................................ 0.3V to V+Operating Temperature Range (Note 4)

LTC1968C/LTC1968I ......................... 40C to 85CSpecified Temperature Range (Note 5)

LTC1968C/LTC1968I ......................... 40C to 85CMaximum Junction Temperature ......................... 150CStorage Temperature Range ................ 65C to 150CLead Temperature (Soldering, 10 sec)................. 300C

ORDER PARTNUMBER

LTC1968CMS8LTC1968IMS8

TJMAX= 150C,JA = 220C/ W

ABSOLUTE AXI U RATI GS W W W U PACKAGE/ORDER I FOR ATIOU UW(Note 1)

MS8 PART MARKIN

LTAFG

The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are T A= 25C. V+ = 5V, VOUTRTN= 2.5V, CAVE= 10F, VIN= 200mVRMS, VENABLE= 0.5Vunless otherwise noted.

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature rangThe temperature grade (I or C) is indicated on the shipping container.

1234

GNDIN1IN2NC

8765

ENABLEV+

OUT RTNVOUT

TOP VIEW

MS8 PACKAGE8-LEAD PLASTIC MSOP

SYMBOL PARAMETER CONDITIONS MIN TYP MAX

Conversion Accuracy

GERR Low Frequency Gain Error 50Hz to 20kHz Input (Notes 6, 7) 0.1 0.3 % 0.4 %

VOOS Output Offset Voltage (Notes 6, 7) 0.2 0.75 mVOOS / T Output Offset Voltage Drift (Note 11) 2 10 V/ C

LINERR Linearity Error 50mV to 350mV (Notes 7, 8) 0.02 0.15 %

PSRRG Power Supply Rejection (Note 9) 0.02 0.20 %/V 0.25 %/V

VIOS Input Offset Voltage (Notes 6, 7, 10) 0.4 1.5 mVVIOS / T Input Offset Voltage Drift (Note 11) 2 10 V/ C

Additional Error vs Crest Factor (CF)

CF = 3 60Hz Fundamental, 200mVRMS 0.2 mV

CF = 5 60Hz Fundamental, 200mVRMS 5 mV

Input Characteristics

VIMAX Maximum Peak Input Swing Accuracy = 1% (Note 14) 1 1.05 V

IVR

Input Voltage Range 0 V+ V

ZIN Input Impedance Average, Differential (Note 12) 1.2 MAverage, Common Mode (Note 12) 100 M

CMRRI Input Common Mode Rejection (Note 13) 50 400 V/V

VIMIN Minimum RMS Input 5 mV

PSRRI Power Supply Rejection (Note 9) 250 700 V/V


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The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are T A= 25C. V+ = 5V, VOUTRTN= 2.5V, CAVE= 10F, VIN= 200mVRMS, VENABLE= 0.5Vunless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 1:Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2:The inputs (IN1, IN2) are protected by shunt diodes to GND and

V+. If the inputs are driven beyond the rails, the current should be limitedto less than 10mA.

Note 3:The LTC1968 output (VOUT) is high impedance and can beoverdriven, either sinking or sourcing current, to the limits stated.Note 4:The LTC1968C/LTC1968I are guaranteed functional over theoperating temperature range of 40C to 85C.Note 5:The LTC1968C is guaranteed to meet specified performance from0C to 70C. The LTC1968C is designed, characterized and expected tomeet specified performance from 40C to 85C but is not tested nor QAsampled at these temperatures. The LTC1968I is guaranteed to meetspecified performance from 40C to 85C.Note 6:High speed automatic testing cannot be performed withCAVE= 10F. The LTC1968 is 100% tested with CAVE= 47nF.Note 7:The LTC1968 is 100% tested with DC and 10kHz input signals.Measurements with DC inputs from 50mV to 350mV are used to calculatethe four parameters: GERR, VOOS, VIOSand linearity error. Correlation testshave shown that the performance limits can be guaranteed with theadditional testing being performed to guarantee proper operation of allinternal circuitry.Note 8:The LTC1968 is inherently very linear. Unlike older log/antilogcircuits, its behavior is the same with DC and AC inputs, and DC inputs areused for high speed testing.Note 9:The power supply rejections of the LTC1968 are measured withDC inputs from 50mV to 350mV. The change in accuracy from V+ = 4.5Vto V+ = 5.5V is divided by 1V.

Note 10:Previous generation RMS-to-DC converters required nonlinearinput stages as well as a nonlinear core. Some parts specify a DC reverserror, combining the effects of input nonlinearity and input offset voltag

The LTC1968 behavior is simpler to characterize and the input offsetvoltage is the only significant source of DC reversal error.Note 11: Guaranteed by design.Note 12:The LTC1968 is a switched capacitor device and the input/outpuimpedance is an average impedance over many clock cycles. The inputimpedance will not necessarily lead to an attenuation of the input signalmeasured. Refer to the Applications Information section titled InputImpedance for more information.Note 13:The common mode rejection ratios of the LTC1968 are measurewith DC inputs from 50mV to 350mV. The input CMRR is defined as thechange in VIOSmeasured with the input common mode voltage at 0V andV+, divided by V+. The output CMRR is defined as the change in VOOSmeasured with OUT RTN = 0V and OUT RTN = V+ 350mV divided byV+ 350mV.

Note 14:The LTC1968 input and output voltage swings are limited byinternal clipping. However, its topology is relatively tolerant ofmomentary internal clipping.Note 15:The LTC1968 exploits oversampling and noise shaping to reducthe quantization noise of internal 1-bit analog-to-digital conversions. Athigher input frequencies, increasingly large portions of this noise arealiased down to DC. Because the noise is shifted in frequency, it becomea low frequency rumble and is only filtered at the expense of increasinglylong settling times. The LTC1968 is inherently wideband, but the outputaccuracy is degraded by this aliased noise.

SYMBOL PARAMETER CONDITIONS MIN TYP MAXOutput CharacteristicsOVR Output Voltage Range 0 V+ VZOUT Output Impedance (Note 12) 10 12.5 16 kCMRRO Output Common Mode Rejection (Note 13) 50 250 V/VVOMAX Maximum Differential Output Swing Accuracy = 1%, DC Input (Note 14) 1.0 1.05

0.9 VPSRRO Power Supply Rejection (Note 9) 250 1000 V/VFrequency Responsef1P 1% Additional Gain Error (Note 15) 500 kHf3dB 3dB Frequency (Note 15) 15 MHPower SuppliesV+ Supply Voltage 4.5 5.5 V

IS Supply Current IN1 = 20mV, IN2 = 0V 2.3 2.7 mAIN1 = 200mV, IN2 = 0V 2.4 m

Shutdown CharacteristicsISS Supply Current VENABLE= 4.5V 0.1 10 AIIH ENABLE Pin Current High VENABLE= 4.5V 1 0.1 AIIL ENABLE Pin Current Low VENABLE= 0.5V 3 0.5 0.1 AVTH ENABLE Threshold Voltage 2.1VHYS ENABLE Threshold Hysteresis 0.1


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LTC1968

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TYPICAL PERFOR A CE CHARACTERISTICS U W

Gain and Offsetvs Output Common Mode Voltage

Gain and Offsetvs Input Common Mode Voltage

INPUT COMMON MODE VOLTAGE (V)0

0.5

G A I N E R R O R ( % )

O F F S E T V

O L T A

G E

( mV

)

0.4

0.2

0.1

0

0.5

0.2

1.0 2.0 2.5 5.04.5

1968 G01

0.3

0.3

0.4

0.1

1.0

0.8

0.4

0.2

0

1.0

0.4

0.6

0.6

0.8

0.2

0.5 1.5 3.0 3.5 4.0

VIOS

VOOS

GAIN ERROR

50mV VIN 350mV

OUTPUT COMMON MODE VOLTAGE (V)0

0.5

G A I N E R R O R ( % )

O F F S E T V

O L T A

G E

( mV

)

0.4

0.2

0.1

0

0.5

0.2

1.0 2.0 2.5 5.04.5

1968 G02

0.3

0.3

0.4

0.1

1.0

0.8

0.4

0.2

0

1.0

0.4

0.6

0.6

0.8

0.2

0.5 1.5 3.0 3.5 4.0

VIOSVOOS

GAIN ERROR

50mV VIN 350mV

Gain and Offset vs TemperatureGain and Offset vs Supply Voltage

SUPPLY VOLTAGE (V)4.5

G A I N E R R O R ( % )

O F F S E T V

O L T A

G E

( mV

)

0.1

0.3

0.5

5.7

1968 G03

0.1

0.3

0

0.2

0.4

0.2

0.40.5

0.2

0

0.6

1.0

0.2

0.6

0.4

0.8

0.4

0.81.0

4.8 5.1 5.4 6.0

VOOS

VIOS

GAIN ERROR

50mV VIN 350mV

TEMPERATURE (C)40

0.5

G A I N E R R O R ( % )

O F F S E T V

O L T A

G E

( mV

)

0.4

0.2

0.1

0

0.5

0.2

15 10 85

1968 G04

0.3

0.3

0.4

0.1

0.50.4

0.2

0.1

0

0.5

0.2

0.3

0.3

0.4

0.1

35 60

VIOS

VOOSGAIN ERROR

50mV VIN 350mV


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LTC1968

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Performance vs Large Crest Factor AC Linearity

DC Linearity Supply Current vs Supply Voltage Supply Current vs Temperature

Power Supply and ENABLE PinCurrent vs ENABLE Voltage

Input Signal Bandwidthvs RMS Value

Performance vs Crest Factor

ENABLE PIN VOLTAGE (V)0

3.0

2.5

2.0

1.5

0.5

1.0

0.5

0

1.0

0

100

100IS

IEN

200

200

300

300

4003 5

1968 G11

1 2 4 6

S U P P L Y C U R R E N T ( m A ) E N

A B L E P I N

C U R R E N T

( n A

)

Input Signal Bandwidth

CREST FACTOR1

199.0

199.8

199.6

199.4

199.2

O U T P U T V O L T A G E ( m V D C )

200.0

200.2

200.4

200.6

2 3 4 5

1kHz

10kHz

1968 G05

200.8

201.0200mVRMS SCR WAVEFORMS

CAVE= 10FO.1%/DIV

60Hz

20Hz

CREST FACTOR1

O U T P U T V O L T A G E ( m V D C )

220

4

1968 G06

190

170

2 3 5

160

150

140

130

120

210200

180

6 7 8

200mVRMSSCR WAVEFORMSCAVE= 10F5%/DIV

60Hz40kHz

10kHz

1kHz

20Hz

VIN1 (mV ACRMS)0

V O U T

( m V D C )

V

I N ( m V A C

R M S

)

0.20

0.15

0.10

0.05

0

0.05

0.10

0.15

0.20400

60Hz

40kHz

1968 G07

100 200 300 500

SINEWAVESCAVE= 10FVIN2= MIDSUPPLY

VIN1(mV)500

{ V O U T D C

| V I N D C

| } ( m V )

0.02

0.06

0.10

300

1968 G08

0.02

0.06

0

0.04

0.08

0.04

0.08

0.10300 100 100 500

CAVE= 10FVIN2= MIDSUPPLY

EFFECT OF OFFSETSMAY BE POSITIVE ORNEGATIVE AT V

IN= 0V

SUPPLY VOLTAGE (V)0

0

S U P P L Y C U R R E N T ( m A )

0.5

1.0

1.5

2.0

3.0

1 2 3 4

1968 G09

5 6

2.5

TEMPERATURE (C)55

2.30

S U P P L Y C U R R E N T ( m A )

2.32

2.36

2.38

2.40

15 25 45 125

1968 G10

2.34

35 5 65 85 105

2.44

2.42

INPUT SIGNAL FREQUENCY (Hz)1k 10k

10

O U T P U T D C

V O L T A G E ( m V )

100

1000

100k 1M 10M 100M

1968 G12

3dB

1% ERROR

1% ERROR

INPUT SIGNAL FREQUENCY (Hz)100

190

O U T P U T D C

V O L T A G E ( m V )

192

194

196

198

1k 10k 100k 1M 10M

1968 G13

188

186

184

182

200

202

1%/DIVCAVE= 10FVIN= 200mVRMS


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LTC1968

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Bandwidth to 500kHz DC Transfer Function Near ZeroInput Common Mode RejectionRatio vs Frequency

Output Accuracyvs Signal Amplitude Output Noise vs Input Frequency

INPUT FREQUENCY (kHz)0

199

200

202

400

1968 G14

198

197

100 200 300 500

196

195

201

O U T P U T V O L T A G E ( m V )

0.5%/DIVCAVE= 10FVIN= 200mVRMS

VIN1(mV DC)30

10

V O U T

( m V D C )

0

10

20

20 10 0 10

1968 G15

20

30

40

5

5

15

25

35

30

VIN2= MIDSUPPLYTHREE REPRESENTATIVE UNITS

INPUT FREQUENCY (Hz)10

0

I N P U T C M R R ( d B )

20

40

60

100 1k 10k 100k

1967 G16

1M

80

10

30

50

70

90

10M

4.5V COMMONMODE INPUTCONVERSIONTO DC OUTPUT

VIN1 (VRMS)0

20

{ V O U T

( m V D C )

V

I N ( m V

R M S

) } ( m V )

15

10

5

0

5

10

0.5 1 1.5

DC

2

1967 G17

1% ERROR VIN2= MIDSUPPLY

1% ERRORAC 60HzSINEWAVE

INPUT FREQUENCY (Hz)10k

0.001

P E A K O U T P U T N O I S E ( %

O F R E A D I N G )

0.01

0.1

1

100k 1M

1967 G18

PEAK NOISE MEASUREDIN 10 SECOND PERIOD

CAVE= 1F

CAVE= 100F

CAVE= 10F

Output Noise vs Device

INPUT FREQUENCY (Hz)1k

0.01

P E A K O U T P U T N O I S E ( %

O F R E A D I N G )

0.1

1

10k 100k 1M1968 G19

LTC1966CAVE= 1F

LTC1967CAVE= 1.5F

LTC1968CAVE= 6.8F

AVE CAPACITOR CHOSEN FOR EACH DEVICETO GIVE A 1 SECOND, 0.1% SETTLING TIME


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LTC1968

1968f

GND (Pin 1):Ground. The power return pin.

IN1 (Pin 2):Differential Input. DC coupled (polarity is

irrelevant).IN2 (Pin 3):Differential Input. DC coupled (polarity isirrelevant).

VOUT(Pin 5):Output Voltage. Pin 5 is high impedance. TheRMS averaging is accomplished with a single shunt ca-pacitor from Pin 5 to OUT RTN. The transfer function isgiven by:

V OUT RTN Average IN INOUT ( )= ( )2 1 2

U U UPI FU CTIO S

OUT RTN (Pin 6):Output Return. The output voltage iscreated relative to this pin. The VOUTand OUT RTN pinsare not balanced and this pin should be tied to a lowimpedance, both AC and DC. Although Pin 6 is often tito GND, it can also be tied to any arbitrary voltage:

GND < OUT RTN < (V+ Max Output)

V+ (Pin 7):Positive Voltage Supply. 4.5V to 5.5V.

ENABLE (Pin 8):An Active-Low Enable Input. LTC1968debiased if open circuited or driven to V+. For normaloperation, pull to GND.

APPLICATIO S I FOR ATIO W U U U

RMS-TO-DC CONVERSION

Definition of RMS

RMS amplitude is the consistent, fair and standard way tomeasure and compare dynamic signals of all shapes andsizes. Simply stated, the RMS amplitude is the heatingpotential of a dynamic waveform. A 1VRMSAC waveformwill generate the same heat in a resistive load as will 1V DC.Mathematically, RMS is the Root of the Mean of theSquare:

V VRMS = 2

+ R1V DC

R

1968 F01

SAMEHEAT1V ACRMS

R1V (AC + DC) RMS

Figure 1

Alternatives to RMS

Other ways to quantify dynamic waveforms include pedetection and average rectification. In both cases, aaverage (DC) value results, but the value is only accuraat the one chosen waveform type for which it is calibratetypically sine waves. The errors with average rectificatiare shown in Table 1. Peak detection is worse in all casand is rarely used.Table 1. Errors with Average Rectification vs True RMS

AVERAGERECTIFIED

WAVEFORM VRMS (V) ERROR*

Square Wave 1.000 1.000 11%

Sine Wave 1.000 0.900 *Calibrate for 0% Error

Triangle Wave 1.000 0.866 3.8%

SCR at 1/2 Power, 1.000 0.637 29.3% = 90

SCR at 1/4 Power, 1.000 0.536 40.4% = 114

The last two entries of Table 1 are chopped sine waves is commonly created with thyristors such as SCRs anTriacs. Figure 2a shows a typical circuit and Figure shows the resulting load voltage, switch voltage and loa


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the lowpass filter. The input to the LPF is the calculatiofrom the multiplier/divider; (VIN)2 /VOUT. The lowpassfilter will take the average of this to create the outputmathematically:


currents. The power delivered to the load depends on thefiring angle, as well as any parasitic losses such as switchON voltage drop. Real circuit waveforms will also typi-cally have significant ringing at the switching transition,dependent on exact circuit parasitics. For the purposes ofthis data sheet, SCR Waveforms refers to the idealchopped sine wave, though the LTC1968 will do faithfulRMS-to-DC conversion with real SCR waveforms as well.

The case shown is for = 90, which corresponds to 50%of available power being delivered to the load. As noted inTable 1, when = 114, only 25% of the available poweris being delivered to the load and the power drops quicklyas approaches 180.

With an average rectification scheme and the typicalcalibration to compensate for errors with sine waves, theRMS level of an input sine wave is properly reported; it isonly with a non-sinusoidal waveform that errors occur.Because of this calibration, and the output reading inVRMS, the term True-RMS got coined to denote the use ofan actual RMS-to-DC converter as opposed to a calibratedaverage rectifier.

CONTROL

VLOAD

ACMAINS VLINE

VTHY

1968 F02a

+

+

+

ILOAD

VLINE

VLOAD

VTHY

ILOAD1968 F02b

Figure 2a

Figure 2b

How an RMS-to-DC Converter Works

Monolithic RMS-to-DC converters use an implicit compu-tation to calculate the RMS value of an input signal. Thefundamental building block is an analog multiply/divideused as shown in Figure 3. Analysis of this topology iseasy and starts by identifying the inputs and the output of

VVV

V

V

Vso

VV

Vand

V V or

V V RMS V

OUTIN

OUT

OUT

IN

OUT

OUTIN

OUT

OUT IN

OUT IN IN

=( )

( )=

( )

=( )

( ) = ( )

= ( ) = ( )

2

2 2

2

2 2

2

,

,

,

,

Because V is DC,

V

OUT

IN

Figure 3. RMS-to-DC Converter with Implicit Computation

VIN VOUT

1968 F03

LPF

V

VIN

OUT

( )2

Unlike the prior generation RMS-to-DC converters, tLTC1968 computation does NOT use log/antilog circuiwhich have all the same problems, and more, of logantilog multipliers/dividers, i.e., linearity is poor, the banwidth changes with the signal amplitude and the gain drifwith temperature.

How the LTC1968 RMS-to-DC Converter Works

The LTC1968 uses a completely new topology for RMS-DC conversion, in which a modulator acts as thedivider, and a simple polarity switch is used as the multplier1 as shown in Figure 4.

1Protected by multiple patents.


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LTC1968

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Note that the internal scalings are such that the outputduty cycle is limited to 0% or 100% only when VINexceeds4 VOUT.

Linearity of an RMS-to-DC Converter

Linearity may seem like an odd property for a device thimplements a function that includes two very nonlineprocesses: squaring and square rooting.

However, an RMS-to-DC converter has a transfer funtion, RMS volts in to DC volts out, that should ideally haa 1:1 transfer function. To the extent that the input toutput transfer function does not lie on a straight line, thpart is nonlinear.

A more complete look at linearity uses the simple modshown in Figure 5. Here an ideal RMS core is corrupted both input circuitry and output circuitry that have impefect transfer functions. As noted, input offset is introducein the input circuitry, while output offset is introduced the output circuitry.

Any nonlinearity that occurs in the output circuity wcorrupt the RMS in to DC out transfer function. A nonlearity in the input circuitry will typically corrupt thtransfer function far less simply because with an AC inpthe RMS-to-DC conversion will average the nonlinearfrom a whole range of input values together.

But the input nonlinearity will still cause problems in RMS-to-DC converter because it will corrupt the accuraas the input signal shape changes. Although an RMS-toDC converter will convert any input waveform to a output, the accuracy is not necessarily as good for awaveforms as it is with sine waves. A common way describe dynamic signal wave shapes is Crest Factor. Thcrest factor is the ratio of the peak value relative to the RMvalue of a waveform. A signal with a crest factor of 4, instance, has a peak that is four times its RMS valu

The modulator has a single-bit output whose averageduty cycle (D) will be proportional to the ratio of the inputsignal divided by the output. The is a 2nd order

modulator with excellent linearity. The single-bit output isused to selectively buffer or invert the input signal. Again,this is a circuit with excellent linearity, because it operatesat only two points:1 gain; the average effective multipli-cation over time will be on the straight line between thesetwo points. The combination of these two elements againcreates a lowpass filter input signal equal to (VIN)2 /VOUT,which, as shown above, results in RMS-to-DC conversion.

The lowpass filter performs the averaging of the RMSfunction and must be a lower corner frequency than the

lowest frequency of interest. For line frequency measure-ments, this filter is simply too large to implement on-chip,but the LTC1968 needs only one capacitor on the outputto implement the lowpass filter. The user can select thiscapacitor depending on frequency range and settling timerequirements, as will be covered in the Design Cookbooksection to follow.

This topology is inherently more stable and linear than log/ antilog implementations primarily because all of the signalprocessing occurs in circuits with high gain op ampsoperating closed loop.

More detail of the LTC1968 inner workings is shown in theSimplified Schematic towards the end of this data sheet.

Figure 4. Topology of LTC1968

-REF

VIN

VOUTLPF1968 F04

1

DV

VIN

OUT

INPUT CIRCUITRY VIOS INPUT NONLINEARITY

IDEALRMS-TO-DCCONVERTER

OUTPUT CIRCUITRY VOOS OUTPUT NONLINEARITY

INPUT OUTPUT

1968 F05

Figure 5. Linearity Model of an RMS-to-DC Converter


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LTC1968

1968f

Because this peak has energy (proportional to voltagesquared) that is 16 times (42) the energy of the RMS value,the peak is necessarily present for at most 6.25% (1/16)of the time.

The LTC1968 performs very well with crest factors of 4 orless and will respond with reduced accuracy to signalswith higher crest factors. The high performance with crestfactors less than 4 is directly attributable to the highlinearity throughout the LTC1968.

DESIGN COOKBOOK

The LTC1968 RMS-to-DC converter makes it easy to

implement a rather quirky function. For many applicationsall that will be needed is a single capacitor for averaging,appropriate selection of the I/O connections and powersupply bypassing. Of course, the LTC1968 also requirespower. A wide variety of power supply configurations areshown in the Typical Applications section towards the endof this data sheet.

Capacitor Value Selection

The RMS or root-mean-squared value of a signal,the root of the mean of the square , cannot be computed withoutsome averaging to obtain themean function. The LTC1968true RMS-to-DC converter utilizes a single capacitor onthe output to do the low frequency averaging required forRMS-to-DC conversion. To give an accurate measure of adynamic waveform, the averaging must take place over asufficiently long interval to average, rather than track, the

lowest frequency signals of interest. For a single averagincapacitor, the accuracy at low frequencies is depicted Figure 6.

Figure 6 depicts the so-called DC error that results atgiven combination of input frequency and filter capacivalues2. It is appropriate for most applications, in whicthe output is fed to a circuit with an inherently band-limitfrequency response, such as a dual slope/integrating A/converter, aA/D converter or even a mechanical analometer.

However, if the output is examined on an oscilloscope wa very low frequency input, the incomplete averaging wbe seen, and this ripple will be larger than the errodepicted in Figure 6. Such an output is depicted iFigure 7. The ripple is at twice the frequency of the inp


Figure 6. DC Error vs Input Frequency

Figure 7. Output Ripple Exceeds DC Error

TIME

O U T P U T

1968 F07

DCERROR(0.05%)

IDEALOUTPUT

DCAVERAGE

OF ACTUALOUTPUT

PEAKRIPPLE

(5%)

ACTUAL OUTPUTWITH RIPPLEf = 2 fINPUT

PEAKERROR =

DC ERROR +PEAK RIPPLE

(5.05%)

2This frequency-dependent error is in additon to the static errors that affect all readings and atherefore easy to trim or calibrate out. The Error Analyses section to follow discusses the efof static error terms.


2.0

D C E R R O R ( %

)

1.6

1.2

0.8

0.4

10 100

1968 F06

0

1.8

1.4

1.0

0.6

0.2

C = 0.22FC = 0.47FC = 1FC = 10F C = 2.2F

C = 22F

C = 47F

C = 4.7F


11/2811

LTC1968

1968f


because of the computation of the square of the input. Thetypical values shown, 5% peak ripple with 0.05% DC error,occur with CAVE= 10F and fINPUT= 6Hz.

If the application calls for the output of the LTC1968 to feeda sampling or Nyquist A/D converter (or other circuitrythat will not average out this double frequency ripple) alarger averaging capacitor can be used. This trade-off isdepicted in Figure 8. The peak ripple error can also bereduced by additional lowpass filtering after the LTC1968,but the simplest solution is to use a larger averagingcapacitor.

A 10F capacitor is a good choice for many applications.The peak error at 50Hz/60Hz will be


12/2812

LTC1968

1968f

Input Connections

The LTC1968 input is differential and DC coupled. The

LTC1968 responds to the RMS value of the differentialvoltage between Pin 2 and Pin 3, including the DC portionof that difference. However, there is no DC-coupled pathfrom the inputs to ground. Therefore, at least one of the twoinputs must be connected with a DC-return path to ground.

Both inputs must be connected to something. If eitherinput is left floating, a zero volt output will result.

For single-ended DC-coupled applications, simply con-nect one of the two inputs (they are interchangeable) tothe signal, and the other to ground. This will work well for

dual supply configurations, but for single supply con-figurations it will only work well for unipolar input sig-nals. The LTC1968 input voltage range is from rail-to-rail,and when the input is driven above V+ or below GND thegain and offset errors will increase substantially after justa few hundred millivolts of overdrive. Fortunately, mostsingle supply circuits measuring a DC-coupled RMSvalue will include some reference voltage other thanground, and the second LTC1968 input can be connectedto that point.

For single-ended AC-coupled applications, Figure 9 showsthree alternate topologies. The first one, shown in Figure9a uses a coupling capacitor to one input while the otheris grounded. This will remove the DC voltage difference fromthe input to the LTC1968, and it will therefore not be partof the resulting output voltage. Again, this connection will


work well with dual supply configurations, but in singsupply configurations it will be necessary to raise the voage on the grounded input to assure that the signal at thactive input stays within the range of 0V to V+. If there isalready a suitable voltage reference available, connect tsecond input to that point. If not, a midsupply voltage cabe created with two resistors as shown in Figure 9b.

Finally, if the input voltage is known to be between 0V aV+, it can be AC coupled by using the configuration showin Figure 9c. Whereas the DC return path was providthrough Pin 3 in Figures 9a and 9b, in this case, the returpath is provided on Pin 2, through the input signal volages. The switched capacitor action between the two inp

pins of the LTC1968 will cause the voltage on the couplicapacitor connected to the second input to follow the Daverage of the input voltage.

For differential input applications, connect the two inputsthe differential signal. If AC coupling is desired, one of two inputs can be connected through a series capacitor.

In all of these connections, to choose the input couplincapacitor, CC, calculate the low frequency coupling timconstant desired, and divide by the LTC1968 differentinput impedance. Because the LTC1968 input impedan

is about 100 times its output impedance, this capacitor itypically much smaller than the output averaging capactor. Its requirements are also much less stringent, and aceramic chip capacitor will usually suffice.

Figure 9. Single-Ended AC-Coupled Input Connection Alternatives

+

LTC1968

GND

V+ V+ V+

V

(9a)

CC

IN1

VIN IN2

2

3

LTC1968

(9b)

CC

R110k

R210k

0.1F

IN1

VIN

V+

IN2

2

3

LTC1968

(9c)

CC

IN1

VIN1968 F09

VDC

IN2

2

3


13/2813

LTC1968

1968f

Output Connections

The LTC1968 output is differentially, but not symmetri-

cally, generated. That is to say, the RMS value that theLTC1968 computes will be generated on the output (Pin 5)relative to the output return (Pin 6), but these two pins arenot interchangeable. For most applications, Pin 6 will betied to ground (Pin 1). However, Pin 6 can be tied to anyvoltage between 0V and V+ (Pin 7) less the maximumoutput voltage swing desired. This last restriction keepsVOUTitself (Pin 5) within the range of 0V to V+. If areference level other than ground is used, it should be alow impedance, both AC and DC, for proper operation ofthe LTC1968.

In any configuration, the averaging capacitor should beconnected between Pins 5 and 6. The LTC1968 RMS-DCoutput will be a positive voltage created at VOUT(Pin 5)with respect to OUT RTN (Pin 6).

Power Supply Bypassing

The LTC1968 is a switched capacitor device, and largetransient power supply currents will be drawn as theswitching occurs. For reliable operation, standard powersupply bypassing must be included. A 0.01F capacitorfrom V+ (Pin 7) to GND (Pin 1) located close to the devicewill suffice. If there is a good quality ground plane avail-able, the capacitors can go directly to that instead. Powersupply bypass capacitors can, of course, be inexpensiveceramic types.

Up and Running!

If you have followed along this far, you should have theLTC1968 up and running by now! Dont forget to enablethe device by grounding Pin 8, or driving it with a logic low.

Keep in mind that the LTC1968 output impedance is fairlyhigh, and that even the standard 10M input impedanceof a digital multimeter (DMM) or a 10scope probe will loaddown the output enough to degrade its typical gain errorof 0.1%. In the end application circuit, either a buffer oranother component with an extremely high input imped-ance (such as a dual slope integrating ADC) should be used.


For laboratory evaluation, it may suffice to use a bench-tDMM with the ability to disconnect the 10M shunt.

If you are still having trouble, it may be helpful to skahead a few pages and review the Troubleshooting Guid

What About Response Time?

With a large value averaging capacitor, the LTC1968 ceasily perform RMS-to-DC conversion on low frequensignals. It compares quite favorably in this regard to priogeneration products because nothing about thecircuitry is temperature sensitive. So the RMS resudoesnt get distorted by signal driven thermal fluctuationlike a log-antilog circuit output does.

However, using large value capacitors results in a sloresponse time. Figure 10 shows the rising and falling steresponses with a 10F averaging capacitor. Although theboth appear at first glance to be standard exponentiadecay type settling, they are not. This is due to thnonlinear nature of an RMS-to-DC calculation. Also nthe change in the time scale between the two; the risinedge is more than twice as fast to settle to a giveaccuracy. Again this is a necessary consequence of RMto-DC calculation.3

Although shown with a step change between 0mV an100mV, the same response shapes will occur with thLTC1968 for ANY step size. This is in marked contrasprior generation log/antilog RMS-to-DC converters, whoaveraging time constants are dependent on the signalevel, resulting in excruciatingly long waits for the outpto go to zero.

The shape of the rising and falling edges will be dependeon the total percent change in the step, but for less than th100% changes shown in Figure 10, the responses will bless distorted and more like a standard exponential decaFor example, when the input amplitude is changed fro

3 To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV a100mV. At very low frequencies, the LTC1968 will essentially track the input. But as the ifrequency is increased, the average result will converge to the RMS value of the input. If the risefall characteristics were symmetrical, the output would converge to 50mV. In fact though, the Rvalue of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetricaand fall characteristics will converge to as the input frequency is increased.


14/2814

LTC1968

1968f

100mV to 110mV (+10%) and back (10%), the stepresponses are essentially the same as a standard expo-nential rise and decay between those two levels. In suchcases, the time constant of the decay will be in betweenthat of the rising edge and falling edge cases of Figure 10.Therefore, the worst case is the falling edge response asit goes to zero, and it can be used as a design guide.

Figure 11 shows the settling accuracy vs settling time fora variety of averaging capacitor values. If the capacitorvalue previously selected (based on error requirements)gives an acceptable settling time, your design is done.

But with 220F, the settling time to even 10% is a full 1seconds, which is a long time to wait. What can be donabout such a design? If the reason for choosing 220F isto keep the DC error with a 200mHz input less than 0.1%the answer is: not much. The settling time to 1% of 2seconds is just 4 cycles of this extremely low frequencAveraging very low frequency signals takes a long tim

However, if the reason for choosing 220F is to keep thepeak error with a 10Hz input less than 0.2%, there another way to achieve that result with a much improvsettling time.


TIME (SEC)0

0

O U T P U T ( m V )

20

40

60

80

100

120

0.10 0.20 0.30 0.40

1968 F10a

0.50

CAVE= 10F

Figure 10a. LTC1968 Rising Edge with CAVE= 10F Figure 10b. LTC1968 Falling Edge with CAVE= 10F

Figure 11. Settling Time vs Cap Value, One Cap Averaging

TIME (SEC)0

0

O U T P U T ( m V )

20

40

60

80

100

120

0.20 0.40 0.60 0.80

1968 F10b

1

CAVE= 10F

SETTLING TIME (SEC)0.01

0.1

S E T T L I N G A C C U R A C Y ( % )

1

10

1 100.1 100

1968 F11

C = 0.1F

C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 10F C = 22F C = 47F C = 100F C = 220F


15/2815

LTC1968

1968f

Reducing Ripple with a Post Filter

The output ripple is always much larger than the DC error,

so filtering out the ripple can reduce the peak errorsubstantially, without the large settling time penalty ofsimply increasing the averaging capacitor.

Figure 12 shows a basic 2nd order post filter, for a net 3rdorder filtering of the LTC1968 RMS calculation. It uses the12.5k output impedance of the LTC1968 as the first re-sistor of a 3rd order Sallen-Key active-RC filter. This topol-ogy features a buffered output, which can be desirabledepending on the application. However, there are disad-vantages to this topology, the first of which is that the opamp input voltage and current errors directly degrade theeffective LTC1968 VOOS. The table inset in Figure 12 showsthese errors for four of Linear Technologys op amps.

A second disadvantage is that the op amp output has tooperate over the same range as the LTC1968 output, includ-ing ground, which in single supply applications is the nega-tive supply. Although the LTC1968 output will function finejust millivolts from the rail, most op amp output stages (andeven some input stages) will not. There are at least two waysto address this. First of all, the op amp can be operated splitsupply if a negative supply is available. Just the op amp

would need to do so; the LTC1968 can remain single sup-ply. A second way to address this issue is to create a signalreference voltage a half volt or so above ground. This is mostattractive when the circuitry that follows has a differentialinput, so that the tolerance of the signal reference is not a


concern. To do this, tie all three ground symbols shown iFigure 12 to the signal reference, as well as to the diffeential return for the circuitry that follows.

Figure 13 shows an alternative 2nd order post filter, fornet 3rd order filtering of the LTC1968 RMS calculationalso uses the 12.5koutput impedance of the LTC1968 athe first resistor of a 3rd order active-RC filter, but thtopology filters without buffering so that the op amp Derror characteristics do not affect the output. Although thoutput impedance of the LTC1968 is increased from 12.5kto 41.9k, this is not an issue with an extremely high inpuimpedance load, such as a dual-slope integrating ADC lithe ICL7106. And it allows a generic op amp to be use

such as the SOT-23 one shown. Furthermore, it easilworks on a single supply rail by tying the noninvertininput of the op amp to a low noise reference as optionalshown. This reference will not change the DC voltage at tcircuit output, although it does become the AC ground fthe filter, thus the (relatively) low noise requirement.

Step Responses with a Post Filter

Both of the post filters, shown in Figures 12 and 13, areoptimized for additional filtering with clean step responses. The 12.5k output impedance of the LTC1968working into a 10F capacitor forms a 1st order LPF witha 3dB frequency of ~1.27Hz. The two filters have 10Fat the LTC1968 output for easy comparison with a10F-only case, and both have the same relative Bessellike shape. However, because of the topological differences of pole placements between the various compo-nents within the two filters, the net effective bandwidtfor Figure 12 is slightly higher (1.2 1.27 1.52Hz) thanwith 10F alone, while the bandwidth for Figure 13 i

Figure 13. DC Accurate Post FilterFigure 12. Buffered Post Filter

LTC1968 CAVE10F

5

6

R15.6k

+

R224.9k

RB

C21F

C110F

LT1077

1968 F12

OP AMPLTC1968 VOOS

VIOSIB/OS R

TOTAL OFFSETRB VALUE

ISQ

LT1494

375V11V1.1mV

43k1A

LT1880

150V48V

940VSHORT1.2mA

LT1077

60V48V

858V43k

48A

LTC2054

3V13V

766VSHORT150A

750V

LTC1968 CAVE10F

5

6

OTHERREF VOLTAGE,

SEE TEXT

R129.4k

+

R2100k

C12.2F

C22.2F

LT1782

1068 F13


16/2816

LTC1968

1968f


somewhat lower (0.7 1.27 0.9Hz) than with 10Falone. To adjust the bandwidth of either of them, simplyscale all the capacitors by a common multiple, and leavethe resistors unchanged.The step responses of the LTC1968 with 10F-only andwith the two post filters are shown in Figure 14. This is therising edge RMS output response to a 10Hz input startingat t = 0. Although the falling edge response is the worstcase for settling, the rising edge illustrates the ripple thatthese post filters are designed to address, so the risingedge makes for a better intuitive comparison.

The initial rise of the LTC1968 will have enhanced slew rateswith DC and very low frequency inputs due to saturationeffects in themodulator. This is seen in Figure 14 in twoways. First, the 10F-only output is seen to rise very quicklyin the first 40ms. The second way this effect shows up isthat the post filter outputs have a modest overshoot, on theorder of 3mV to 4mV, or 3% to 4%. This is only an issuewith input frequency bursts at 50Hz or less, and even withthe overshoot, the settling to a given level of accuracyimproves due to the initial speedup.

As predicted by Figure 6, the DC error with 10F is wellunder 1mV and is not noticeable at this scale. However, as

predicted by Figure 8, the peak error with the ripple froma 10Hz input is much larger, in this case about 5mV. As canbe clearly seen, the post filters reduce this ripple. Even thewider bandwidth of Figure 12s filter is seen to cut theripple down substantially (to


17/2817

LTC1968

1968f


Figures 18 and 19 show the settling time versus settlingaccuracy for the Buffered and DC accurate post filters,respectively. The different curves represent differentscalings of the filters, as indicated by the CAVEvalue. Theseare comparable to the curves in Figure 11 (single capacitorcase), with somewhat less settling time for the bufferedpost filter, and somewhat more settling time for theDC-accurate post filter. These differences are due to thechange in overall bandwidth as mentioned earlier.

Although the settling times for the post-filtered configura-tions shown on Figures 18 and 19 are not that muchdifferent from those with a single capacitor, the point ofusing a post filter is that the settling times are far better fora given level peak error. The filters dramatically reduce thelow frequency averaging ripple with far less impact onsettling time.

Crest Factor and AC + DC Waveforms

In the preceding discussion, the waveform was assumedto be AC coupled, with a modest crest factor. Bothassumptions ease the requirements for the averagingcapacitor. With an AC-coupled sine wave, the calculatioengine squares the input, so the averaging filter thatfollows is required to filter twice the input frequencymaking its job easier. But with a sinewave that includeDC offset, the square of the input has frequency contenat the input frequency and the filter must average out thalower frequency. So with AC + DC waveforms, the rquired value for CAVEshould be based on half of the lowestinput frequency, using the same design curves presentedin Figures 6, 8, 16 and 17.

Figure 17. Peak Error vs Input Frequency with DC-Accurate Post Filter

Figure 16. Peak Error vs Input Frequency with Buffered Post Filter


1.2 P E A K E R R O R ( % )

1.0

0.8

0.6

0.4

10 100 1000

1968 F08

1.4

1.6

1.8

2.0

0.2

0

C = 22F

C = 100F

C = 47F C = 10F C = 4.7F C = 2.2F C = 0.47F C = 0.22F C = 0.1FC =1F


1.2 P E A K E R R O R ( % )

1.0

0.8

0.6

0.4

10 100 1000

1968 F08

1.4

1.6

1.8

2.0

0.2

0

C = 22F

C = 47F

C = 10F C = 4.7F C = 2.2F C = 0.47F C = 0.22F C = 0.1F C = 0.047FC =1F


18/2818

LTC1968

1968f


Crest factor, which is the peak to RMS ratio of a dynamicsignal, also effects the required CAVEvalue. With a highercrest factor, more of the energy in the signal is concentratedinto a smaller portion of the waveform, and the averaginghas to ride out the long lull in signal activity. For busywaveforms, such as a sum of sine waves, ECG traces orSCR-chopped sine waves, the required value for CAVEshould be based on the lowest fundamental input frequencydivided as such:

ff

CFDESIGN

INPUT MIN= ( )

3 2

using the same design curves presented in Figures 6, 8,16 and 17. For the worst case of square top pulse trains,that are always either zero volts or the peak voltage, basethe selection on the lowest fundamental input frequencydivided by twice as much:

ff

CFDESIGN

INPUT MIN= ( )

6 2

The effects of crest factor and DC offsets are cumulativSo for example, a 10% duty cycle pulse train from 0VPEAKto 1VPEAK(CF = 10 = 3.16) repeating at 16.67ms (60Hzinput is effectively only 30Hz due to the DC asymmetry ais effectively only:

f HzDESIGN= =306 3 16 2

3 78 .

.

for the purposes of Figures 6, 8, 16 and 17.

Obviously, the effect of crest factor is somewhat simplifiabove given the factor of two difference based on subjective description of the waveform type. The resulwill vary somewhat based on actual crest factor an

Figure 19. Settling Time with DC-Accurate Post Filter

Figure 18. Settling Time with Buffered Post Filter


0.1


1

10

10.1 10 100

1968 F18

C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 10F C = 22F C = 47F C = 100F C = 220F C = 470F


0.1


1

10

10.1 10 100

1968 F19

C = 0.1F C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 10F C = 22F C = 47F C = 100F C = 220F

C = 470F


19/2819

LTC1968

1968f

waveform dynamics and the type of filtering used. Theabove method is conservative for some cases and aboutright for others.

The LTC1968 works well with signals whose crest factoris 4 or less. At higher crest factors, the internalmodulator will saturate, and results will vary depending onthe exact frequency, shape and (to a lesser extent) ampli-tude of the input waveform. The output voltage could behigher or lower than the actual RMS of the input signal.

The modulator may also saturate when signals withcrest factors less than 4 are used with insufficient averag-ing. This will only occur when the output droops to lessthan 1/4 of the input voltage peak. For instance, a DC-coupled pulse train with a crest factor of 4 has a duty cycleof 6.25% and a 1VPEAKinput is 250mVRMS. If this input is50Hz, repeating every 20ms, and CAVE= 10F, the outputwill droop during the inactive 93.75% of the waveform.This droop is calculated as:

V V eMIN RMSINACTIVETIME

=

21 2 Z COUT AVE

For the LTC1968, whose output impedance (ZOUT) is12.5k, this droop works out to 3.6%, so the output

would be reduced to 241mV at the end of the inactiveportion of the input. When the input signal again climbs to1VPEAK, the peak/output ratio is 4.15.

With CAVE= 100F, the droop is only 0.37% to 249.1mVand the peak/output ratio is just 4.015, which the LTC1968has enough margin to handle without error.

For crest factors less than 3.5, the selection of CAVEaspreviously described should be sufficient to avoid thisdroop and modulator saturation effect. But with crestfactors above 3.5, the droop should also be checked for

each design.

Error Analyses

Once the RMS-to-DC conversion circuit is working, it istime to take a step back and do an analysis of the accuracyof that conversion. The LTC1968 specifications includethree basic static error terms, VOOS, VIOSand GAIN. Theoutput offset is an error that simply adds to (or subtracts


from) the voltage at the output. The conversion gain of thLTC1968 is nominally 1.000 VDCOUT /VRMSINand the gainerror reflects the extent to which this conversion gain not perfectly unity. Both of these affect the results infairly obvious way.

Input offset on the other hand, despite its conceptuasimplicity, effects the output in a nonobvious way. As iname implies, it is a constant error voltage that adddirectly with the input. And it is the sum of the input aVIOSthat is RMS converted.

This means that the effect of VIOS is warped by thenonlinear RMS conversion. With 0.4mV (typ) VIOS, and a200mVRMSAC input, the RMS calculation will add the Dand AC terms in an RMS fashion and the effect inegligible:

VOUT= (200mV AC)2 + (0.4mV DC)2= 200.0004mV= 200mV + 2ppm

But with 10 less AC input, the error caused by VIOS is100 larger:

VOUT= (20mV AC)2 + (0.4mV DC)2= 20.004mV= 20mV + 200ppm

This phenomena, although small, is one source of thLTC1968s residual nonlinearity.

On the other hand, if the input is DC coupled, the inpoffset voltage adds directly. With +200mV and a +0.4mVIOS, a 200.4mV output will result, an error of 0.2% o2000ppm. With DC inputs, the error caused by VIOScan bepositive or negative depending if the two have the same opposing polarity.

The total conversion error with a sine wave input using t

typical values of the LTC1968 static errors is computed follows:

VOUT= ( (500mV AC)2 + (0.4mV DC)2) 1.001 + 0.2mV= 500.700mV= 500mV + 0.140%



20/2820

LTC1968

1968f


As can be seen, the gain term dominates with large inputs,while the offset terms become significant with smallerinputs. In fact, 5mV is the minimum RMS level needed tokeep the LTC1968 calculation core functioning normally,so this represents the worst-case of usable input levels.

Using the worst-case values of the LTC1968 static errors,the total conversion error is:

VOUT= ( (500mV AC)2+ (1.5mV DC)2) 1.003 + 0.75mV= 502.25mV

= 500mV + 0.45%VOUT= ( (50mV AC)2 + (1.5mV DC)2) 1.003 + 0.75mV

= 50.923mV= 50mV + 1.85%


These static error terms are in addition to dynamic errorterms that depend on the input signal. See the DesignCookbook for a discussion of the DC conversion error withlow frequency AC inputs. The LTC1968 bandwidth limita-tions cause additional errors with high frequency inputs.Another dynamic error is due to crest factor. The LTC1968performance versus crest factor is shown in the TypicalPerformance Characteristics.

Output Errors Versus Frequency

As mentioned in the design cookbook, the LTC1968 per-forms very well with low frequency and very low frequencyinputs, provided a large enough averaging capacitor is used.

However, the LTC1968 will have additional dynamic errorsas the input frequency is increased. The LTC1968 is de-signed for high accuracy RMS-to-DC conversion of sig-nals up to 100kHz. However, the switched capacitor cir-cuitry samples the inputs at a modest 2MHz nominal. Theresponse versus frequency is depicted in the Typical Per-formance Characteristics titled Input Signal Bandwidth.


Although there is a pattern to the response versus frequency that repeats every sample frequency, the errorare not overwhelming. This is because LTC1968 RMcalculation is inherently wideband, operating properly wminimal oversampling, or even undersampling, using several proprietary techniques to exploit the fact that the RMvalue of an aliased signal is the same as the RMS value the original signal. However, a fundamental feature of t modulator is that sample estimation noise is shapedsuch that minimal noise occurs with input frequenciemuch less than the sampling frequency, but such noisepeaks when input frequency reaches half the samplinfrequency. Fortunately the LTC1968 output averaging ter greatly reduces this error, but the RMS-to-DC topolofrequency shifts the noise to low (baseband) frequencieSee Output Noise vs Input Frequency in the Typical Perfmance Characteristics.

Input Impedance

The LTC1968 true RMS-to-DC converter utilizes a 0.8capacitor to sample the input at a nominal 2MHz sampfrequency. This accounts for the 1.2M input impedance.See Figure 20 for the equivalent analog input circuit. Nohowever, that the 1.2M input impedance does not di-

rectly affect the input sampling accuracy. For instance,a 15.5k source resistance is used to drive the LTC1968, thsampling action of the input stage will drag down thvoltage seen at the input pins with small spikes at eversample clock edge as the sample capacitor is connected tbe charged. The time constant of this combination ismall, 0.8pF 15.5k = 12.5ns, and during the 125nsperiod devoted to sampling, ten time constants elapse

Figure 20. LTC1968 Equivalent Analog Input Circuit

IN1

VDD

VDD

VSS

VSS

RSW (TYP)2k

CEQ0.8pF(TYP)

CEQ0.8pF(TYP)

IIN1

IN2

IIN2

1968 F20

RSW (TYP)2k

I INV V

R

I INV V

RR M

AVGIN IN

EQ

AVGIN IN

EQ

EQ

1

2

1.2

1 2

2 1

( ) =

( ) =

=


21/2821

LTC1968

1968f


This allows each sample to settle to within 46ppm and it isthese samples that are used to compute the RMS value.

This is a much higher accuracy than the LTC1968 conver-sion limits, and far better than the accuracy computed viathe simplistic resistive divider model:

Output Impedance

The LTC1968 output impedance during operation is sim

larly due to a switched capacitor action. In this case, 20pof on-chip capacitance operating at 2MHz translates in25k. The closed-loop RMS-to-DC calculation cuts thathalf to the nominal 12.5k specified.

In order to create a DC result, a large averaging capacitis required. Capacitive loading and time constants are nan issue on the output.

However, resistive loading is an issue and the 10Mimpedance of a DMM or 10 scope probe will drag theoutput down by 0.125% typ.

During shutdown, the switching action is halted and fixed 12.5k resistor shunts VOUTto OUT RTN so that CAVEis discharged.

Interfacing with an ADC

The LTC1968 output impedance and the RMS averagiripple need to be considered when using an analog-todigital converter (ADC) to digitize the LTC1968 Rresult.

The simplest configuration is to connect the LTC196

directly to the input of a type 7106/7136 ADC as shownFigure 21a. These devices are designed specifically fDVM/DPM use and include display drivers for a 3 1/2 dLCD segmented display. Using a dual-slope conversiothe input is sampled over a long integration window, whicresults in rejection of line frequency ripple when integrtion time is an integer number of line cycles. Finally, theparts have an input impedance in the G range, withspecified input leakage of 10pA to 20pA. Such a leakacombined with the LTC1968 output impedance, results less than 1V of additional output offset voltage.

Another type of ADC that has inherent rejection of RMaveraging ripple is an oversampling ADC such as theLTC2420. Its input impedance is 6.5M, but only when itis sampling. Since this occurs only half the time at mosif it directly loads the LTC1968, a gain error of 0.08%0.11% results. In fact, the LTC2420 DC input current

V V RR R

V M

V

IN SOURCEIN

IN SOURCE

SOURCE

SOURCE

=+

=

=

1.2

1 25 . %M k+1.2 15.5

This resistive divider calculation does give the correctmodel of what voltage is seen at the input terminals by aparallel load averaged over a several clock cycles, which iswhat a large shunt capacitor will doaverage the currentspikes over several clock cycles.

When high source impedances are used, care must be takento minimize shunt capacitance at the LTC1968 input so asnot to increase the settling time. Shunt capacitance of just0.8pF will double the input settling time constant and theerror in the above example grows from 46ppm to 0.67%(6700ppm). As a consequence, it is important tonot try tofilter the input with large input capacitances unless drivenby a low impedance. Keep time constant


22/2822

LTC1968

1968f

not zero at 0V, but rather at one half its reference, so bothan output offset and a gain error will result. These errorswill vary from part to part, but with a specific LTC1968 andLTC2420 combination, the errors will be fixed, varying lessthan0.05% over temperature. So a system that has digi-tal calibration can be quite accurate despite the nominalgain and offset error. With 20 bits of resolution, this partis more accurate than the LTC1968, but the extra resolu-tion is helpful because it reduces nonlinearity at the LSBtransitions as a digital gain correction is made. Further-more, its small size and ease of use make it attractive.

This connection is shown in Figure 21b, where the LTC2420is set to continuously convert by grounding the CS pin. Thegain error will be less if CS is driven at a slower rate,however, the rate should either be consistent or at a ratelow enough that the LTC1968 and its output capacitor havefully settled by the beginning of each conversion, so thatthe loading errors are consistent.

Other types of ADCs sample the input signal once andperform a conversion on that one sample. With theseADCs (Nyquist ADCs), a post filter will be needed in mostcases to reduce the peak error with low input frequencies.The DC-accurate filter of Figure 13 is attractive from anerror standpoint, but it increases the impedance at the ADCinput. In most cases, the buffered post filter of Figure 12will be more appropriate for use with Nyquist analog-to-digital converters.

SYSTEM CALIBRATION

The LTC1968 static accuracy can be improved with en

system calibration. Traditionally, calibration has beedone at the factory, or at a service depot only, typicalusing manually adjusted potentiometers. Increasinglsystems are being designed for electronic calibratiowhere the accuracy corrections are implemented in digitcode wherever possible, and with calibration DACs whnecessary. Additionally, many systems are now designefor self calibration, in which the calibration occurs insithe machine, automatically without user intervention.

Whatever calibration scheme is used, the linearity of thLTC1968 will improve the calibrated accuracy over thachievable with older log/antilog RMS-to-DC converterAdditionally, calibration using DC reference voltages aessentially as accurate with the LTC1968 as those usingAC reference voltages. Older log/antilog RMS-to-DC coverters required nonlinear input stages (rectifiers) whoselinearity would typically render DC-based calibratiounworkable.

The following are four suggested calibration methodImplementations of the suggested adjustments are dependent on the system design, but in many cases, gain an

output offset can be corrected in the digital domain, anwill include the effect of all gains and offsets from tLTC1968 output through the ADC. Input offset voltage,the other hand, will have to be corrected with adjustmeto the actual analog input to the LTC1968.

AC-Only, 1 Point

The dominant error at full scale will be caused by the gaerror, and by applying a full-scale sine wave input, therror can be measured and corrected for. Unlike older loantilog RMS-to-DC converters, the correction should bmade for zero error at full scale to minimize errors througout the dynamic range.

The best frequency for the calibration signal is roughly ttimes the 0.1% DC error frequency. For 10F, 0.1% DCerror occurs at 6Hz, so 60Hz is a good calibration frequencalthough anywhere from 60Hz to 100Hz should suffice


Figure 21a. Interfacing to DVM/DPM ADC

Figure 21b. Interfacing to LTC2420

CAVE

LTC1968

OUTPUT

OUT RTN

7106 TYPE

IN HI

IN LO

5

6

31

1968 F21a

30

CAVE

LTC1968

OUTPUT

OUT RTN

LTC2420

VIN SERIALDATA

DIGITALLY CORRECTLOADING ERRORS

GND

SDO

SCK

CS

5

6

3

1968 F21b

4


23/2823

LTC1968

1968f

The trade-off here is that on the one hand, the DC error isinput frequency dependent, so a calibration signal fre-quency high enough to make the DC error negligibleshould be used. On the other hand, as low a frequency ascan be used is best to avoid attenuation of the calibratedAC signal, either from parasitic RC loading or insufficientop amp gain. For instance, with a 1kHz calibration signal,a 1MHz op amp will typically only have 60dB of open-loopgain, so it could attenuate the calibration signal a full 0.1%.

AC-Only, 2 Point

The next most significant error for AC-coupled applica-tions will be the effect of output offset voltage, noticeable

at the bottom end of the input scale. This too can becalibrated out if two measurements are made, one with afull-scale sine wave input and a second with a sine waveinput (of the same frequency) at 10% of full scale. Thetrade-off in selecting this second level is that it should besmall enough that the gain error effect becomes smallcompared to the gain error effect at full scale, while on theother hand, not using so small an input that the input offsetvoltage becomes an issue.

The calculations of the error terms for a 200mV full-scalecase are:

Gain = Reading at 200mV Reading at 20mV180mV

Output Offset = Reading at 20mVGain

20mV

DC, 2 Point

DC-based calibration is preferable in many cases becausea DC voltage of known, good accuracy is easier to gener-ate than such an AC calibration voltage. The only downside is that the LTC1968 input offset voltage plays a role.It is therefore suggested that a DC-based calibrationscheme check at least two points:full scale. Applying the

full-scale input can be done by physically inverting thvoltage or by applying the same +full-scale input to thopposite LTC1968 input.

For an otherwise AC-coupled application, only the gterm may be worth correcting for, but for DC-couplapplications, the input offset voltage can also be calculated and corrected for.

The calculations of the error terms for a 200mV full-scacase are:

Gain = Reading at 200mV +Reading at 200mV400mV

Input Offset =Reading at 200mV Reading at 200mV

2Gain

Note: Calculation of and correction for input offset voltaare the only way in which the two LTC1968 inputs (ININ2) are distinguishable from each other. The calculatiabove assumes the standard definition of offset; that positive offset is the case of a positive voltage error insithe device that must be corrected by applying a liknegative voltage outside. The offset is referred to whicever pin is driven positive for the +full-scale reading.

DC, 3 Point

One more point is needed with a DC calibration schemedetermine output offset voltage: +10% of full scale.

The calculation of the input offset is the same as for th2-point calibration above, while the gain and output offsare calculated for a 200mV full-scale case as:

Gain = Reading at 200mV Reading at 20mV180mV

Output Offset =Reading at 200mV +Reading at 200mV 400mV Gai

2



24/2824

LTC1968

1968f


TROUBLESHOOTING GUIDE

Top Ten LTC1968 Application Mistakes

1. Circuit wont workDead On Arrivalno power drawn. Probably forgot to enable the LTC1968 by pulling

Pin 8 low.

Solution: Tie Pin 8 to Pin 1.

2. Circuit wont work, but draws power. Zero or verylittle output, single-ended input application. Probably didnt connect both input pins.

Solution: Tie both inputs to something. See InputConnections in the Design Cookbook.

4. Gain is low by a few percent, along with other screwresults. Probably tried to use output in a floating, different

manner.Solution: Tie Pin 6 to a low impedance. See OutpConnections in the Design Cookbook.

LTC1968

CONNECT PIN 3

IN12

3NC IN2

1968TS02

LTC1968

IN12

3IN2

1968 TS03

DC-COUPLE ONE INPUT

LTC1968

DC-CONNECT ONE INPUT

IN12

3IN2

3. Screwy results, particularly with respect to linearityor high crest factors; differential input application. Probably AC-coupled both input pins.

Solution: Make at least one input DC-coupled. SeeInput Connections in the Design Cookbook.

TYPE 7136ADC

LTC1968

HI31

30

5

6LO

VOUT

OUT RTN

1968 TS04

GROUND PIN 6

5. Offsets perceived to be out of specification because 0in 0V out. The offsets are not specified at 0V in. No RMS-t

DC converter works well at 0 due to a divide-by-zecalculation.

Solution: Measure VIOS /VOOSby extrapolating read-ings >5mVDC.

6. Linearity perceived to be out of specification particlarly with small input signals. This could again be due to using 0V in as one of th

measurement points.

Solution: Check Linearity from 5mVRMS to500mVRMS.

The input offset voltage can cause small AC lineityerrors at low input amplitudes as well. See ErrAnalyses section.Possible Solution: Include a trim for input offset.


25/2825

LTC1968

1968f


7. Output is noisy with >200kHz inputs. This is a fundamental characteristic of this topol-

ogy. The LTC1968 is designed to work very wellwith inputs of 100kHz or less. It works okay as highas 1MHz, but it is limited by aliased noise.

Solution: Bandwidth limit the input or digitally filterthe resulting output.

8. Large errors occur at crest factors approaching, butless than 4. Insufficient averaging.

Solution: Increase CAVE. See Crest Factor and AC +DC Waveforms section for discussion of output

droop.9. Screwy results, errors > spec limits, typically 1% to 5%.

High impedance (12.5k) and high accuracy (0.1%)require clean boards! Flux residue, finger grime, etc.all wreak havoc at this level.

Solution: Wash the board.

10. Gain is low by 1% or more, no other problems. Probably due to circuit loading. With a DMM o

10 scope probe, ZIN = 10M. The LTC1968output is 12.5k, resulting in 0.125% gainerror. Output impedance is higher with the Daccurate post filter.

Solution: Remove the shunt loading or buffer thoutput.

Loading can also be caused by cheap averagincapacitors.

Solution: Use a high quality metal film capacitfor CAVE.

LTC1968

KEEP BOARD CLEAN

1968 TS09

200mVRMSIN0.125%

DMM

DCV

LTC1968

10M

5

12.5k6

VOUT

OUT RTN

1968 TS10

LOADING DRAGS DOWN GAIN

mV


26/2826

LTC1968

1968f

TYPICAL APPLICATIO S U

SI PLIFIED SCHE ATICW W

5V Single Supply, Differential,AC-Coupled RMS-to-DC Converter

Single Supply RMS Current Measurement

V+

5V

LTC1968

IN1 DC OUTPUTCAVE10F

CC1F

IN2

1968 TA02

VOUTAC INPUTS(1VPEAK

DIFFERENTIAL) OUT RTN

GND EN

V+

LTC1968IN1

VOUT= 4mVDC /ARMSCAVE10F

0.1F

IN2

1968 TA03

VOUTAC CURRENT

75A MAX50Hz TO 400Hz

OUT RTN

GND EN10k

10k

10

T1: CR MAGNETICS CR8348-2500-Nwww.crmagnetics.com

T1

2nd ORDER MODULATORIN1

IN2

EN

V+

+

+

OUTPUT

OUT RTN

50kBLEED RESISTORFOR CAVE

CAVE

1968 SS

TO BIAS CONTROL

GND

C1

C2

Y1 Y2

C12

C11

CLOSEDDURING

SHUTDOWN

C9

C10

C5C3

C4

C6

C8

C7

A2A1


27/2827

LTC1968

1968f

UPACKAGE DESCRIPTIO

MS8 Package8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

TYPICAL APPLICATIO S U

2.5V Supplies, Single Ended, DC-CoupledRMS-to-DC Converter with Shutdown RMS Noise Measurement

V+

2.5V

2.5V

2.5V

LTC1968

IN1 DC OUTPUTCAVE10F

0.1F

X7R

IN2

1968 TA04

VOUTDC + AC

INPUT(1VPEAK) OUT RTN

GND

EN

OFF2V 2VON V+

2.5V

2.5V

2.5V

2.5V

LTC1968

IN1 CAVE10F

0.1F

1.5F

IN2

1968 TA05

VOUT

VOLTAGENOISE IN

OUT RTN

GND EN

1mVDC1VRMS OF INPUT NOISE

VOUT=

+1k

100

100 100k

BW 1kHz TO 100kHzINPUT SENSITIVITY = 1VRMSTYP

1/2LTC6203

MSOP (MS8) 0204

0.53 0.152(.021 .006)

SEATINGPLANE

NOTE:1. DIMENSIONS IN MILLIMETER/(INCH)2. DRAWING NOT TO SCALE3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.18(.007)

0.254(.010)

1.10(.043)MAX

0.22 0.38(.009 .015)

TYP

0.127 0.076(.005 .003)

0.86(.034)REF

0.65(.0256)

BSC

0 6 TYP

DETAIL A

DETAIL A

GAUGE PLANE

1 2 3 4

4.90 0.152(.193 .006)

8 7 6 5

3.00 0.102(.118 .004)

(NOTE 3)

3.00 0.102(.118 .004)

(NOTE 4)

0.52(.0205)

REF

5.23(.206)MIN

3.20 3.45(.126 .136)

0.889 0.127(.035 .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 0.038(.0165 .0015)

TYP

0.65(.0256)

BSC


28/28

LTC1968

RELATED PARTSPART NUMBER DESCRIPTION COMMENTS

LT1077 Micropower, Single Supply Precision Op Amp 48A IS, 60V VOS(MAX), 450pA IOS(MAX)LT1175-5 Negative, 5V Fixed, Micropower LDO Regulator 45A IQ, Available in SO-8 or SOT-223

LT1494 1.5A Max, Precision Rail-to-Rail I/O Op Amp 375V VOS(MAX), 100pA IOS(MAX)LT1782 General Purpose SOT-23 Rail-to-Rail Op Amp 40A IS, 800V VOS(MAX), 2nA IOS(MAX)LT1880 SOT-23 Rail-to-Rail Output Precision Op Amp 1.2mA IS, 150V VOS(MAX), 900pA IOS(MAX)LTC2054 Zero Drift Op Amp in SOT-23 150A I

S, 3V V

OS(MAX), 150pA I

B(MAX)LT2178/LT2178A 17A Max, Single Supply Precision Dual Op Amp 14A IS, 120V VOS(MAX), 350pA IOS(MAX)LTC1966 Precision Micropower RMS-to-DC Converter 155A ISLTC1967 Precision Extended Bandwidth RMS-to-DC Converter 320A ISLTC2402 2-Channel, 24-bit, Micropower, No LatencyTMADC 200A IS, 4ppm INL, 10ppm TUE

LTC2420 20-bit, Micropower, No Latency ADC in SO-8 200A IS, 8ppm INL, 16ppm TUE

LTC2422 2-Channel, 20-bit, Micropower, No Latency ADC Dual channel version of LTC2420

No Latency is a trademark of Linear Technology Corporation.

Audio Amplitude Compressor

TYPICAL APPLICATIO U

+

+

+

8

7

92

1

14

R42.49k

R1100k

VIN

R37.5k

R55.9k

R1547

VFS

R21k

C20.47F

C147nF

13

A1

A2

V+LT1256

V V+

VOUT

C30.1F

R133.3k

R143.3k

12

RFS

10

RC

5

VC

R62k

R10200k

R121k

R910k

R815k

V+

LT1636

ATTENUATION CONTROL

GAIN OF 4

ATTENUATEBY 1/4

V+

V

R75.9k

3

C50.22F

C41F

LTC1968

1968 TA07

VDD

GND EN

VOUTOUT RTN

IN1IN2

0.1F

Documents

Ltc 1968 datasheet