Microprocesoret – Sistemet me mikroprocesore - Pak histori ... fileTipet e sistemeve digitale Qarqet logjike - Fakulteti Ekonomik, Agim Çami , 2010 2 Kombinatore. . . osepa memorje

Microprocesoret – Sistemet me mikroprocesore- Pak histori- Koncepte- Intel mikroprocesors-Sisteme me mikroprocesore

Qarqet logjike - Fakulteti Ekonomik, Agim Çami , 20101

Agim Çami

Tipet e sistemeve digitale


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Kombinatore . . . ose pa memorje (memoryless)Kryejne veprime te llojit AND, OR, NOT, … mbi te dhena ne forme digitale (bite)

Sekuenciale … ose me memorje ( me nje numer te kufizuargjendjesh)

Kalimi nga njera gjendje ne tjetren varet nga :

•Gjendja e mepareshme•Hyrjet (Inputs)

Te Programueshem … me nje numer te pakufizuar gjendjesh. Ne kete rastkemi te bejme me sisteme digtale te bazuar ne mikroprocesore.


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Çfare paisjesh jane keto? ……. Perse ?

A jane keta kompjutera??


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PERSE ???


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Mobile Device = Computing System

Embeded Device = Computing System

Kompjuteri duhet te ofroje :


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Perpunim te informacionit Rujatje (memorizim) te te dhenave Komunikimin me perdoruesit (njerezit)

Mobile Device = Computing System

I have always wished that my computer would be as easy to use as my telephone...My wish has come true: I no longer know how to use my telephone.

Prof. Bjarne Stroustrup, father of C++

Ne vitin 2006 jane shitur me shume telefonamobile se sa PC !!


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Disa perfundime…


Sistemet digitale te bazuar ne mikroporocesore mund te jene :

Kompjutera … ose te perdorimit te pergjithshemDisponojne burime informatike te konsiderueshne : kujtesa, mundesiperpunimi te dhenash.Kontrollohen gjithmone nga nje “general purpose OS”.

Embedded . . . ose te perdorimit specifikDisponojne burime informatike te kufizuara: kujtesa, mundesi perpunimi tedhenash.Zakonisht kontrollohen nga nje “software te tipit “real-time”.

Pak histori…


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1943-1946: ENIAC - kompjuteri i pare “Turing complet” dhe teresisht elektronik

Digital, decimal arithmetic

Programi = kabllo dhe switches

ENIAC (Electronic Numerical Integrator and Calculator) ne Universitetin e Pensilvanise ngaJohn Mauchly dhe Presper Eckert.Hardware :Llampa electronike, MTBF – koha mesatare ndermjetdy difekteve- e rendit 15 minuta. Peshonte 30 ton dhe perbehej nga18.000 llampa elektronike

ENIAC= Electronic Numerical Integrator and Computer

EDVAC – arkitektura John von Neumann


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EDVAC (1945–1949)

EDVAC introduced the stored program concept in a real machine (John Eckert, J. Presper Mauchly and John von Neumann)

Binary logic

EDVAC = Electronic Discreet Variable Computer

Ky eshte nje “bug” …


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Sot, per ta gjetur ju duhet te “debug” programin…

1964


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1964: IBM System/360 Integrated circuits OS: millions of line of assembly code

IBM 360, CDC 6000, te ndjekur nga minikompjuterat PDP 11Hardware :Qarqe te integruar, paralelizem ne ekzekutimin e instruksioneve per te rriur shpejtesineProgramet (software) :Kompilatore te gjuheve te prorgramimit : : FORTRAN 56, Cobol 60, Algol 60, ndjekur nga Basic 64, APL 69, Lisp, Pascal 69, C 70. Siteme shfrytezimi me ndarje kohe, minikompjutera (OS Unix 1970).Perdorimi :Kompjutera qendrore (mainframe); ordinatore te spacializuar per adminsitrim (gestion) ose llogaritje matematikore

Shenim : OS = Operating System, Sistem shfrytezimi i kompjuterit

1971-…Epoka e mikroprocesoreve


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1971 - Intel 4004 Mikroprecoseri i pare “single-chip” 8-bit architecture, 4-bit implementation VLSIC (Very Large Scale Integration Circuit) 2,300 transistore Performance < 0.1 MIPS

(Million Instructions per Sekonde) Clock rate : 740 Khz. 8008: 8-bit implementation ne vitin 1972

3,500 transistore

1973 – Micral – Mikrokompjuteri i pare i ndertuar bazuar ne mikroprocesorin8008.

1974 – Motorola 6800 , clock 2 Mhz, 4100 tranzistore 1977 – Apple 1, Apple computer

1978.. Intel 8086 , 16 bits


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16-bit architecture Performance < 0.5 MIPS◦ “Assembly language” compatible with

8080◦ 29,000 transistors◦ Includes memory protection, support

for Floating Point coprocessor

1981, IBM PC◦ Bazuar ne 8088—versioni 8-bit bus i

8086

1981 IBM PC(Personal Computer)


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Intel 8088, 4.77 Mhz

256 K RAM (Random Access Memory) standard

1 ose 2 floppy disk drives MS-DOS (Microsoft Disk Operating

System) IBM-Intel-Microsoft joint venture

1979 – Gjenerata e II (32-bit) e MP-Motorola 68000


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Avancim cilesor ne arkitektuen e microprocessoreve : 32-bit architecture Flat 32-bit address General-purpose register architecture 68,000 transistors < 1 MIPS (Million Instructions Per Second)

Apple Macintoch - 1984 Bazuar ne Motorola 68000 Kompiuteri i pare komercial me GUI (Graphical User Interface ) dhe

mouse.

Intel : 1971-2010


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Modeli Viti i leshimit No. i transistoreve

4004 1971 2,2508008 1972 2,5008080 1974 5,0008086 1978 29,00080286 1982 120,00080386™ processor 1985 275,00080486™ DX processor 1989 1,180,000Pentium® processor 1993 3,100,000Pentium II processor 1997 7,500,000Pentium III processor 1999 24,000,000Pentium 4 processor 2000 42,000,000Itanium 2001 25,000,000Core Duo 2006 151,000,000Core2 2006 291,000,000Atom 2008 47,000,000Core i7 2008 730,000,000Xeon “Nahlem-X” 2010 2,300,000,000

Motorola


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6800 1974 41006809 1979 40,00068000 1979 68,00068020 1984 190.00068030 1987 273,00068040 1990 1,200,000PowerPC 601 1993 (IBM) 2,800,000PowerPC 604 1994 (IBM) 3,600,000PowerPC 750 1997 (IBM) 6,350,000PowerPC 7450 2001 (IBM) 22,000,000

AMD – Advanced Micro Devices


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K5 1996 4,300,000K6 1997 8,800,000Athlon 1999 22,000,000Optreon 2003 106,000,000Athlon 64 2005 243,000,000Phenom 2008 450,000,000Phenom II 2009 758,000,000Optreon”Magny-Cours” 2010 1,810,000,000

Te tjere mikroprocesore…


SPARC, UltraSPARC (Sun Microsystems)

ARM cores (Advanced RISC Machines)

MIPS cores (MIPS Technologies)

TI’s TMS DSP chips (Texas Instruments)

StarCore (Motorola, Agere)

• • • • • •

Evolucioni i mikropocesoreve “Single-Chip”


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1970’s 1980’s 1990’s 2010

Numri iTransistoreve

10K-100K

100K-1M 1M-100M >1Miliard

Clock Frequency 0.2-2MHz

2-20MHz 20M-1GHz

10GHz

Instruction/Cycle < 0.1 0.1-0.9 0.9- 2.0 10 (?)

MIPS/MFLOPS < 0.2 0.2-20 20-2,000 100,000

“Ligji i Moor-it” - Moore’s Law

Qarqet logjike - Fakulteti Ekonomik, Agim Çami , 2010 22

Exponential growth2,250

Transistor count will be doubled every 18 months Gordon Moore, Intel co-founder

42millions

1.7 billionsMontecito

10 μm13.5mm2

0.09 μm596 mm2


10 8

10 7

10 6

10 5

10 4

10 3

10 2

10 1

10 0

10 9

10 10

’60 ’65 ’70 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10

10 11

1K1K4K4K 16K16K

64K64K256K256K

1M1M

16M16M4M4M

64M64M

40044004

8080808080868086

8028680286i386™i386™

i486™i486™PentiumPentium®®

MemoryMemoryMicroprocessorMicroprocessor

PentiumPentium®® IIIIPentiumPentium ®® IIIIII

256M256M512M512M

PentiumPentium®® 4ItaniumItanium®®

1G2G 4G

128M128M

Rritja reale 1960-2010 e No. te tranzistoreve e krahasuar me parashikimin e Gordon Moore

Actual IC Performance to Gordon’s Prediction

Aplikime te microprocesoreve


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Por…çfare eshte nje mikroprocesor ?


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Le te kthehmi per njemoment tek 3 funksionet themelorete nje kompjuteri !

ALU = Arithmetic and Logic Unit

Mikroprocesori ? = CPU


Microprocesori (shkurt MPU) eshte nje CPU i fabrikuar ne nje qark te vetem teintegruar !

CPU = CU + ALU

CPU – Central Processing UnitCU- Control UnitALU – Arithmetic Logic Unit

ALU, CU, Regjistra – kjo eshte perberjae MPU !


Arithmetic LogicUnit

Register Arrays

Control Unit

ALU performs computing tasks – manipulates the data/ performs numerical and logical computationsRegisters are used for temp. storageControl unit is used for timing and other controlling functions – contains a program counter (next instruction’s address and status register)

X

Y

Controlunit

IR

PC

ALU ACC

MAR

Data bus

Control bus

Address bus

Tre nivelet e trajtimit temikroprocesoreve


ISA – Instruction Set ArchitectureSpecifikon makinen logjike te cilen shikon progamuesi. Pra, percakton “instuction set” qe perdoretnga programuesi ose qe gjenerohet nga kompilatori. ISA konsiderohet edhe si kufiri ndermjethardware dhe software.

Implementimi ose mikroarkitekturaPercakton strukturen e procesorit te nevojshme per realizimin e ISA.Percakton organizimin dhe strukturen e MPU.

Realizimi (Chip)Trajton strukturen fizike te MPU qe ben te mundur implementimin e mikroarkitektures.

Shembull - Struktura e Intel 8088 -Pentium


AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

ALU

Flag register

Execution Unit (EU)

EU control

Σ

CS

DS

SS

ESALU Data bus (16 bits)

Address bus (20 bits)

Instruction Queue

Bus control

External bus

IP

Data bus(16 bits)

Bus Interface Unit (BIU)

General purpose register

Segment register

MPU Intel 8088-8086

Veshtrim i pergjithshem i 8088


Te dhena rreth Intel 8088

8088

VDD (5V)

GND

CLK

20-bit address

8-bit data•• •••

control signals To 8088

control signals from 8088

8088 signal classification

20 bit address bus allow accessing 1 M memory locations

16-bit internal data bus and 8-bit external data bus. Pra, duhen 2 operacione read ose write per telexuar ose shkruar 16 bite data.

Byte addressable and byte-swapping

Memory locations

5A2F18000

18001Low byte of wordHigh byte of word

Word: 5A2F

Intel 8088/86/286 Progammer visible registers


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15 8 7 0

AX

BX

CX

DX

AH AL

BH BL

CH CL

DH DL

Accumulator

Base

Counter

Data

SP

BP

SI

DI

Data Group

Pointer and Index Group

Stack Pointer

Base Pointer

Source Index

Destination Index

16 bits data registers

Progammer visible registers


8086/8/286 kane regjistra 16-bite 80386/486/Pentium/Pro kane reg. 32-bite

Shenim : Keta regjistra quhen “programmer visible registers “ te ndare ne “General

Purpose Registres=GPR” dhe SPR =Special Purpose Registers”

Regjistrat e perdorimit te pergji-thshemte Intel 8088-Pentium


EAX (accumulator) perdoret prej instruksioneve (p.sh. mbledhje/zbrije, shumezim/pjestim) dhe mund te mbaje pjesen “offset” te nje adresse ne kujtese.

EBX (base index) mban pjesen “offset” te nje adresse ne kujtese. ECX (count) mban parametrin “count” per disa instruksione si p.sh.

Rep dhe Loop. P. Sh. REP = Repeats execution of string instructions while CX != 0

EDX (data) mban nje pjese te rezultatit te shumezimit ose pjese tepjestuesit.

EBP (base pointer) shenjon (point) ne nje adrese ne kujtese. EDI (destination index) addresses string destination data for the

string instructions ESI (source index) addresses source string data for the string

instructions

Shembuj instruksionesh qe pedorinregjistrat GPR


ADD CH,BL ; (CH)+(BL)-> (CH)

MOV CX, [SI] ; MEMORY [SI] -> CX

MOV [DI], 0C0F2H ; 0C0F2H-> MEMORY [DI]

POP DX ; STACK (top) -> DX (SP+2)

PUSH DX ; (DX) -> STACK (top) (SP-2)

SUB AX,BX ; (BX)-(AX) -> AXJZ EXACT ; if ZF=1 then JUMP EXACT, else

; next instruction

SPR=Special Purpose Registers


SPR qunen regjistrat EIP, ESP, EFLAGS dhe “segment registers” CS, DS, ES, SS, FS, and GS

EIP (instruction pointer) shenjon instruksionin e rradhes (next instruction) teprogramit ne “code segment”.

ESP (stack pointer) shenjon nje zone ne kujtese e quajtur “stack” qemanipulohet me instruksione te posacme (push/pop).

EFLAGS (indikatoret e gjendjeve) tregon gjendjet e posacme te rezultatit ne dalje te ALU-se, te mikroprocesorit si dhe kontrollon punen e tij.

Flags=Indikatoret e gjendjeve


C (carry) - vendoset mbetja (carry) pas nje operacioni mbledhjeose “the borrow” pas zbritjes. P (parity) - ka vleren 0 per çiftesi teke (odd parity) dhe 1 per çiftesi çift (even parity).A (auxiliary carry) - vendoset mbetja (half-carry) pas njeoperacioni mbledhje ose “the borrow” pas zbritjes ndermjetbiteve 3 dhe 4 te rezultatit.Z (zero) tregon se cili eshte rezultati i nje operacioni arithmetikose logjik. Z=1, if rezultati eshte 0; Z=0, if rezultati eshtendryshe nga 0.S (sign) tregon shenjen e rezultatit pas ekzekutimit te njeoperacioni arithmetik ose logjik. T (trap) aktivizon (enables) ekzekutimin step-by-step (trapping) per te bere “debugging” e nje programi.I (interrupt)) kontrollon nje operacion INTR (interrupt request) qe vjen nga nje “input pin” e MPU.

Flags=Indikatoret e gjendjeve … vazhdim…


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D (direction) flag selects either the increment or decrement mode for the DI and/or SI register during string instructionsO (overflow) flag indicates the result of addition or subtraction has exceeded the capacity of the machineIOPL (I/O privilege level) is used in protected mode operation to select the privilege level for I/O devicesNT (nested task) flag indicates that the current task is nested within another task in protected mode operationRF (resume flag)) is used with debugging to control the resumption of execution after the next instructionVM (virtual mode) flag bit selects virtual mode operation in a protected mode systemAC (alignment check) flag bit activates if a word or a doubleword is addressed on a non-word or a non-doubleword boundaryVIF (Virtual Interrupt Flag)) is a copy of the interrupt flag bit available to the Pentium/Pro µPVIP (Virtual Interrupt Pending) provides information about a virtual mode interrupt for the Pentium/Pro µP

Permbledhje per Flags=Indikatoret e gjendjes te MPU


NT IOPL OF DF IF TF ZFSF AF PF CF

015

Control Flags Status Flags

IF: Interrupt enable flagDF: Direction flagTF: Trap flag

CF: Carry flagPF: Parity flagAF: Auxiliary carry flagZF: Zero flagSF: Sign flagOF: Overflow flagNT: Nested task flagIOPL: Input/output privilege level

Regjistri Flag eshte nje regjister i modifikueshem individualisht (bit-per-bit) qeregjistron gjendje te posacme te rezultatit te ALU si dhe gjendjen e mikroprocesorit. Nepermjet ketyre gjendjeve kontrollohet puna e mikroprocesorit. Dallohen dy grupe : Control Flags dhe Status Flags

Hapsira e kujtese dhe hyrje/daljeve(Memory and In/Out address space)


Intel 8086 perdor dy hapsira adresimiteresisht te ndara ndermjet tyre:Hapsire adresimi e kujteses qendrore(central memory address space) dhehapsire e hyrje/daljeve (input/output address space) • Memory address space-1,048,576 bytes long(1Mbyte)

• Input/output address space- 65,536 bytes long (64K-bytes)

Hapesira e adresimit te kujtesesqendrore


Memory in the 8088/8086 microcomputer is organizedas individual bytes• Memory address space corresponds to the 1M addresses in the range 00000H to FFFFFH

00000H= 00000000000000000000FFFFFH = 11111111111111111111

220= 1,048,576 = 1M

• Data organization:• Double-word: contents of 4 contiguous byte addresses• Word: contents of two contiguous byte addresses• Byte: content of any individual byte address

Intel 8086 Memory Map


• Memory address space ndahet ne pjese te perdorimit te pergjithshem dhete perdorimit te dedikuar

Dedicated/Reserved:• 0H → 7FH interrupt vector table• 1st 128 bytes• 32 4-byte pointers

• 16-bit segment base address—2 MSBytes• 16-bit offset—2 LSBytes

• 0H → 13H dedicated to internal interrupts andexceptions• 14H → 7FH reserved for external user-definedinterrupts• FFFF0H → FFFFBH dedicated to hardware reset• FFFFCH → FFFFFH reserved for future products• General use:• 80H → FFFEFH• Available for stack, code, and data

SPR … Segment Registers


CS (code) eshte regjistri qe mban adresen e fillimit tepjeses se kujteses ku gjendet programet (code = programs and procedures)

DS (data) eshte regjistri qe mban adresen e fillimit tepjeses se kujteses ku gjenden te dhenat (data ) qeperdoren nga nje program. Per kapjen e nje te dhenebrenda kesaj pjese te kujteses perdoret “offset address”.

SS (stack) eshte regjistri qe mban adresen e fillimit tepjeses se kujteses qe quhet stack. Per te kapur tedhenat brenda “stack-ut” perdoret regjistri BP.

ES (extra) percakton nje segment te dhenash shteseqe perdoren nga disa instruksione qe manipulojne“strings”.

Segment Registers jane regjistra te posacem qe duke u kombinuarme regjistra te tjere gjenerojne adresa me te cilat adresohet kujtesaqendrore.

Segment Registers – grafikisht


Si gjenerohet “physical address” nepermjet “logical address”


Logical address: real-mode architecture described by a segment address and an offset Segment base address (CS, DS, ES, SS) are 16 bit quantities Offsets (IP, SI, DI, BX, DX, SP, BP, etc.) are 16 bit quantities Shembull:CS:IP 100H:100H Code accessDS:SI 2000H:1EFH Data accessES:DI 3000H:0H Data accessSS:SP F000H:FFH Stack access Physical Address: actual address used for accessing memory 20-bits in length Formed by: Shifting the value of the 16-bit segment base address left 4 bit positions Filling the vacated four LSBs with 0 (zero)Adding the 16-bit offset

Pyetje : Sa eshte madhesia makismale e nje segmenti ?

Shembull : Gjenerimi i adreses se kujteses


Shembull :

Segment base address = 1234HOffset = 0022H

1234H = 0001 0010 0011 01000022H = 0000 0000 0010 0010Shifting base address,00010010001101000000 = 12340H

Adding segment address and offset

00010010001101000000 + 0000000000100010 == 00010010001101100010= 12362H

Pyetje :

Perse baza e segmentit duhet bere shift majtas me 4 bite?

IP Register – Instruction Poiner


Instruction pointer (IP): Percakton se bashku me CS – Code Segment vendodhjen e “next word of instruction code” qe duhetlexuar (fetch) nga segmenti korent i kodit.

Pra :

CS:IP formon 20-bit adrese fizike i “ next word of instruction code”

8088/8086 fetches a word of instruction code from code segment in memory Increments value in IP by 2Word placed in the instruction queue to await execution

Shembull adresimi i nje instruk-sioni


Cila eshte adresa nga do te lexohet (fetch) instruksioni i rradhes?

CSIP

1 2 3 40 0 1 2

1 2 3 5 2

12352 MOV AL, 0

Intel MPU Memory

Update regjistrin IP

— Pasi instruksioni eshte lexuar (fetch), regjistri IP ndryshohet (updtade) :

IP = IP + gjatesia e instruksionit te lexuar

— Shembull : Gjatesia e MOV AL, 0 eshte 2 bytes. Pas leximit te instruksionit regjistri IP do te marre vleren 0014”

Kujtese rreth hapve qe ndjekekzekutimi i nje instruksioni


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1) IFetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute:

Mem-reference :Llogarit adresen e operandeArith-logaritje : Kryej veprimin arith./logjik

4) Memory: Load: Read Data from MemoryStore: Write Data to Memory

5) Write Back: Write Data to Register (eventualisht)

Skematikisht si ekzekutohet njeinstruksion


I-1 I-2 I-3 I-4

PC program

I-1instructionregister

op1op2

memory fetch

ALU

registers

writ

e

decode

execute

readw

rite

(output)

registers

flags

Executoin Unit (EU) Control – Njesia qeekzekuton Instruksinet


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ALU Data bus (16 bits)

AH ALBH BLCH CLDH DL

SPBPSIDI

General purpose register

ALU

Flag register

EU control instruction

1011000101001010

1. Fetch an instruction from instruction queue

2. According to the instruction, EU controllogic generates control signals. (This process is also referred to as instructiondecoding)

3. Depending on the control signal,EU performs one of the following operations:

An arithmetic operation A logic operation Storing a datum into a registerMoving a datum from a register Changing flag register

Permbledhje e perdorimi te regjistrave“Special Pupose”


Stack—temporary storage area for information such asdata and addresses

Located in stack segment of memory Real mode—64K bytes long Organized as 32k words Information saved as words, not bytes Organization of stack

SS:0000H end of stack (lowest addressed word) SS:FFFEH bottom of stack (highest addressed word) SS:SP top of stack (last stack location to which datawas pushed Stack grows down from higher to lower address Used by call, push, pop, and return operations ShembujPUSH SI causes the current content of the SIregister to be pushed onto the “top of the stack”

POP SI causes the value at the “top of the stack”to be popped back into the SI register

Si funksionon Stiva ( Stack) !


Instruksioni Push Stack


Status of the stack prior to execution of theInstruction

PUSH AXAX = 1234HSS = 0105HEOS = SS:00 01050H = end of stackSP = 0008HBOS = SS:FFFEH 1104EHTOS = SS:SP 01058H = current top of stack

BBAAH = Last value pushed to stackAddresses < 01058H = invalid stack dataAddresses >= 01058H = valid stack data

Hapat gjate ekzekutimit te instruksionit PUSHAX1. Regjistri SP 0006H decremented by 2ATOP 01056H2. Memory write to stack segmentAL = 34H 01056HAH = 12H 01057H

Pyetje : Perse jane te vertete keto mosbarazime ?

Addresses < 01058H = invalid stack dataAddresses >= 01058H = valid stack data

Instruksioni Pop Stack


Status of the stack prior to execution of the instruction POP AX:

AX = XXXXHSS = 0105HSP = 0006HTOS = SS:SP 01056H = current top of stack1234H = Last value pushed to stack

Addresses < 01056H = invalid stack dataAddresses >= 01056H = valid stack data

Instruksioni Pop Stack … vazhdim


Hapat gjate ekzekutimit te instruksionit POP AX 1. Memory read to AX01056H = 34H AL01057H = 12H AH2. SP 0008H incremented by 2TOP 01058H Hapat gjate ekzekutimit te instruksionit POP BX 1. Memory read to BX01058H = AAH BL01059H = BBH BH2. SP 000AH incremented by 2: TOP 0105AH

Permbledhje rreth stives - stack


Stiva eshte nje strukture ne kujtese e tipit LIFO (Last In First Out)

Ne stive vendosen vetem te dhena Manipulohet kryesisht me dy instruksione :

Organizimi i hapesires se hyrje/daljeve(In/Out address space )


Input/output address space eshte :

Place where I/O devices are normallyimplemented I/O addresses are only 16-bits in length Independent 64K-byte address spaceAddress range 0000H through FFFFH Page 0 First 256 byte addresses 0000H -00FFH Can be accessed with direct or variable I/O instructions Ports F8H through FF reserved

I /O maped I/O


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Advantazhet e I/O te dedikuara(I/O maped I/O)

Complete memory address space available foruse by memory devices I/O instructions tailored to maximize performance

Dizavantazhet e I/O te dedikuara

All inputs/output must take place between I/Oport and accumulator register

SHEMBULL :MOV DX,372H ; load DX with port addressOUT DX,AL ; output byte in AL to port 372 (hex)IN AX,DX ; input word to AX

Input/output data organization

Supports byte or word I/O ports 64K independent byte-wide I/O ports 32K independent aligned word-wide I/O ports Shembuj:Byte ports 0,1, 2 addresses 0000H, 0001H, and 0002HAligned word ports 0,1, 2 addresses 0000H,0002H, 0004H

8086 In/Out ports


Microprocessor-Based Systems

• Central Processing Unit (CPU)• Memory• Input/Output (I/O) circuitry• Buses

– Address bus– Data bus– Control bus

Microprocessor-Based System with Buses: Address, Data, and Control

Microprocessor-based Systems - BUS The three components – MPU, memory, and I/O – are connected by a group of

wires called the BUS

Address bus consists of 16, 20, 24, or 32 parallel signal lines (wires) - unidirectional these lines contain the address of the memory location to read or written

Control bus consists of 4 to 10 (or more) parallel signal lines CPU sends signals along these lines to memory and to I/O ports

examples: Memory Read, Memory Write, I/O Read, I/O Write Data bus

consists of 8,16, or 32 parallel signal lines bi-directional only one device at a time can have its outputs enabled, this requires the devices to have three-state output

Microprocessor-based SystemsMemory Types

R/W: Read/Write Memory; also called RAM It is volatile (losses information as power is removed) Write means the processor can store information Read means the processor can receive information from the memory

ROM: Read-Only memory; It is typically non-volatile (permanent) – can be erasable

Microprocessor-based SystemsMemory Classification

Expensive Fast/

CheapSlow Onetime programmable

Electronically ErasablePROM

Teknologjitekryesoreme te cilatrealizohen: Semiconductor Magnetic Optical(ose kombinim ityre)


Mikroprocesoret

Kujtesen

Dy modelet se si CPU e shikonkujtesen


66

Ja perse CPU “dashuron” kujtesen !


67

Ja pikat e kontaktit te CPU-Kujtese


Microprocessor-based SystemsI/O Ports

The way the computer communicates with the outside world devices

I/O ports are connected to Peripherals Peripherals are I/O devices Input devices Output devices

Examples Printers and modems, keyboard and mouse scanner Universal Serial Bus (USB)

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Microprocesoret – Sistemet me mikroprocesore - Pak histori ... fileTipet e sistemeve digitale Qarqet logjike - Fakulteti Ekonomik, Agim Çami , 2010 2 Kombinatore. . . osepa memorje