Performed by: Yaron Recher & Shai Maylat

Supervisor: Mr. Rolf Hilgendorf

מהירות ספרתיות למערכות המעבדה

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

Sub -Nyquist SamplingSystem Architecture

אביב 2010סמסטר

High speed digital systems laboratory

Characterization presentation

Project Overview

• Design system architecture

• Creating debug environment

• Architecture implementation on FPGA

• Creating controlling GUI

General Algorithm Scheme

• Expand block: Recieves 4 channels from A/D and expands them to 12 channels (18bit each)

** Implemented in the same FPGA

• CTF block: Discovers supports out of 12 channels (support width 7 bit)

• DSP & Detector block**: Reconstructs the Initial Signal

1x BOARD: ProcStar||| GiDEL

4x FPGA: Stratix||| EP3SE110 Altera

Overview

FPGA Environment

PROCStar III Processing unit

Buses on Board

•FPGA to FPGA Bits Max.Freq.(MHz) L/R (I/O) : 100 250 // exp. IC4 V18_L/R : 10 300 Main : 40 300 // global•FPGA to PSDB Bits Max.Freq.(MHz)

L/R_IO : 20 300 // 7 to IC1 L_IN : 8 300 // PSDB to IC L2_IO : 85 300 // only to IC1

Memories• External from FPGA

Bank A: 256 MB DDR2 DRAM Bank B,C: 2 x 1 GB SODIMM

• Internal inside FPGA MLAB 640-bit (639 blocks)

Filter delay lines, small FIFO buffers and shift registers M9K Blocks 9,216-bit (16 blocks)

General purpose memory applications M114K Blocks 147,456-bit (2150 blocks)

Processor code storage, packet and video frame buffering.

Max.Freq.=333MHz

B Max.Freq.= 333MHz C Max.Freq.=166MHz

Max.Freq.=500MHz

Total Internal Memory: 1MByte

Project Goals

• Integrate Designs – Across linked FPGA’s• Set and support Test environment• Design and Implement Debug GUI• Improve Debug GUI to work environment GUI

General Connectivity

20MHZ \2MHZ60MHZ 20MHZ 20MHZ 20MHZ

1. Loading data on board FIFOs from PCI

2. Loading control registers from PCI

3. Transferring data to internal RAMs from external memory

4. Sending Start Loading signal to CTF/DSP/Exp. Units

5. Receiving Ready signal from the CTF/DSP/Exp. Units

6. Sending Ready signal to the main controller. All units ready

7. Main controller Starts the A2D and the system runs

Process FlowSimilar to all Units

Expander EntityInputs:Clk_60 – 60MHz input data clockClk_20 – 20MHz main output data clockClk_2 – 2MHz iteration output data clockClk_240 – 240MHz processing clock

From main controller :rst – resetstart_load – memory ready for readnum_of_itr – number of wanted slicepause – pause the system

From CTF :req_pulse – request of new slice

Memory (20[MHz]) :memory_data – data from memorymemory_ack – requested data is ready

From A/D (60[MHz]) :Data_from_AD – input data for the systemData_in_valid – the input is valid

Outputs:ready_to_arch – finished initilizationdata_to_main – main output to CTF/DSP (20[MHz])data_to_main_valid – main output is validdata_to_CTF – iteration output (2[MHz])data_to_CTF_valid – iteration output is validmemory_read_request – request data from memory

Expander BlocksIncluding on Board Memories

•A2D : FIFO on board memory•Coeff. : FIFO on board memory•Main Bus Debug : FIFO on board memory•CTFDebug : FIFO on board memory

•A2D Reader : Reads data from A2D, simulates A2D input•Main Debug Writer : Writes data from main bus to on board FIFO•CTF Debug Writer : Writes data from Expander to debug memory

•Main Bus Interface : Receives data from Expander & sends with high rate •CTF Bus Interface : Receives data from Expander & sends with high rate

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

•Pll : On board Pll , similar to all

Block Description

DESIGNED TILL NOW:BLOCKS TO IMPLEMENT:

Expander Block DiagramDESIGNED TILL NOW: (NOT YET ON FPGA)BLOCKS TO IMPLEMENT:

Expander State MachineDESIGNED TILL NOW:PATH TO IMPLEMENT:

CTF EntityOutputs:

To Controller :ready – ready to begin

To Expander :req_pulse – requests next iteration To DSP :support – numbers of supportnum_of_supports – total number of supportssupport_valid – support data is valid

To Matrix RAM :A_addr – Address for data from RAMA_rd_req – read enable

Inputs:Clk_20 – 20MHz main input data clockClk_240 – 240MHz processing clockCLk 160 - 160MHz processing clock or as needed

From controller :reset – resetstart_load– memory ready for readpause – pause the systemN_Frame – FrameThreshhold - OMP stopping cond.Num_Of_Ite r- Number of iterations

From Expander :data_from_exp – iterational datadata_exp_valid - iterational data valid

From DSP : initiate – there has been support change

From Matrix RAM:A_data – data from RAM

From Main interface:data_main– input data for the expanderdata_main_valid– the data is valid

CTF BlocksIncluding on Board Memories

•Iteration Debug : FIFO on board memory•Matrix : FIFO on board memory•Memory Debug : FIFO on board memory•Matrix internal : RAM memory

•Main Reader : Reads data from memory, simulates input from Exp. main•Exp.Debug Reader : Reads data from memory, simulates input from Exp. L/R•Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory•Memory Debug Writer: Writes Debug data to memory

•Main Bus Interface : Receives data from main bus & sends with low rate •CTF Bus Interface : Receives data from L/R bus & sends with low rate

•Exp. DebugMod. : Simulates Expander in debug mode•Dsp DebugMod : Simulates DSP in debug mode

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

Block Description

DESIGNED TILL NOW:

+CTF to DSP

BLOCKS TO IMPLEMENT:

CTF Block DiagramDESIGNED TILL NOW: (ON WORK- SIMULATIONS)BLOCKS TO IMPLEMENT:

CTF to DSP

interface

CTF State MachineDESIGNED TILL NOW:PATH TO IMPLEMENT:

DSP EntityOutputs:column_number– number of columndigital_signals – data outputsamples_valid_out– the output data is validsupport_changed– support change was detected

Inputs:Clk_20 – 20MHz main input data clockClk_240 – 240MHz processing clock

From controller :reset – resetstart– memory ready for readpause – pause the system

From CTF :support – numbers of supportsupport_num – how many support passedsupport_valid – support number is valid

Internal FIFO:samples_from_fifo– data from fifosamples_fifo_valid– the data is valid

From Main interface:samples_from_expander– input data for the expandersamples_expander_valid– the data is valid

From Matrix memory:memory_get – matrix row

DSP BlocksIncluding on Board Memories

•MainBus : FIFO on board memory•Matrix : FIFO on board memory•Delay : FIFO on board memory•Output : FIFO on board memory•Matrix internal : RAM memory

•Main Reader : Reads data from memory, simulates input from Exp. Main•Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory•Output Writer : Writes outputdata to memory•Fifo Reader : Reads inputdata from delay fifo

•Main Bus Interface : Receives data from main bus & sends with low rate •Ctf DebugMod. : Simulates CTF in debug mode

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

Block Description

DESIGNED TILL NOW:

+DSP to CTF interface

BLOCKS TO IMPLEMENT:

DSP Block Diagram

DESIGNED TILL NOW: (NOT YET IMPLEMENTED)BLOCKS TO IMPLEMENT:

DSP to CTF

interface

DSP State MachineDESIGNED TILL NOW:PATH TO IMPLEMENT:

• Studying each group Entity’s I/O and single Debug mode operations (from Dima and Oleg)

• Studying Board busses, memories and communication clocks phase\skew problem (Gadi’s Project handle it)

• Design and Implement the communication blocks (Interface blocks) needed for the across linked FPGA’s- and the same time to be able to support groups with 1 FPGA Debug mode operation.

• Debug entire board+ all group’s Entity’s, we will held continuous meetings with the groups to synchronize with them and update them with the needed architecture changes. (each change they might have need to be informed and confirmed with us)

• Design and Implement Debug GUI (Visual C? JAVA? LabView?)- creating the test environment

• Improve GUI for board users

Future Aspirations

Gantt Chart

Learning the system

updated from previous group

Preparing the charactrization presentation

Studying needed Tools

Preparing the Midterm Presentation

System integration (Design)

System simulation

Writing C code Part A

Implement GUI Part A

Exams Period

Preparing Final presentation Part A

14/2/10 6/3/10 26/3/10 15/4/10 5/5/10 25/5/10 14/6/10 4/7/10 24/7/10 13/8/10

project part B (Not in the Gantt…)

• Exams period B… •Test and Debug Entire Board• Finish GUI Test Environment • Improve GUI to System controlling GUI

Questions?