Performed by: Yevgeny Safovich 307015578Yevgeny Zeldin 304649031

Instructor: Yevgeni Rifkin

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

In-depth DSP QA

סמסטר )חורף( שנה 20021

BackgroundHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• Cosmic waves influences on DSP

• Bits reversal in transistors because of radiation

• Any DSP module might be corrupted

• Malfunctioning localization

• General approach to DSP QA

Project goalHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• Develop testing environment

• Host PC used by an operator to:• Run the tests• Present results analysis

• Connection of host PC to DSP to:• Load “active” testing routines• Perform “passive” tests to verify proper functioning of standalone modules

• Localization of failures

Blocks Diagram High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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CPUoControl Registerso6 ALUso32 A data path registerso32 B data path registers

CPUoControl Registerso6 ALUso32 A data path registerso32 B data path registers

GeneraloPLLoInterrupt controlleroBoot configuration

GeneraloPLLoInterrupt controlleroBoot configuration

Peripherals

oEMFIAoEMFIBoMcBSP0oMcBSP1oMcBSP2oUtopiao3 TimersoHPIoGPIO

Peripherals

oEMFIAoEMFIBoMcBSP0oMcBSP1oMcBSP2oUtopiao3 TimersoHPIoGPIO

Buseso)E(DMAoPeripheral bus

Buseso)E(DMAoPeripheral bus

Internal

Memory/

CacheoL2 cacheoL1 cache

Internal

Memory/

CacheoL2 cacheoL1 cache

Boundaries and Specifications High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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3 main optional approaches:

1. Internal tests of the DSP – self test)executing a test program(

1. External tests – access DSP modules form outside to read/write data

2. Mixture of above

3’rd option selected for: Reliability, Complexity, Speed

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Covered modulesHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• PeripheralsEMFIA, EMFIB, McBSP0, McBSP1, McBSP2, Utopia, 3 Timers,

HPI, GPIO

• Buses(E)DMA, Peripheral bus, Internal Memory/Cache, L2 cache

• CPUControl Registers, 6 ALUs, 32 A registers, 32 B registers

• GeneralPLL, Interrupt controller, Boot configuration

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Uncovered modules, limitations High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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CacheL1 cache – tested as integral part of CPU

PeripheralsPCITCPVCP

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Solution architecture High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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DSP6416

Control Program

90%

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Solution architecture )cont.(High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• An external PC computer• Execute/Control the tests• Present the analyzed results

• Direct connection from host computer to DSP• PCI cards to emulate peripheral interfaces (+device drivers)

• UTOPIA master• McBSP master• EMIFA• EMIFB

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Solution architecture )cont.(High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• “Passive tests” – external cross tests by host PC(Using host PC)

• “Active tests” – loading test routines to DSP• The program will be executed on internal CPU• The inputs will be taken from internal memory• The results will be written to internal memory• The outputs will be retrieved by the host PC through HPI

• To get most reliable result cross tests will be used(multiple units groups will be used for same tests)

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AssumptionsHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• L1 cache will not be tested separately

•A failure in major DSP modules cancels all next tests – such as:• L1 cache• internal memory• HPI• DMA

• Failure of HPI cancels all next tests )single direct access interface(

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Open IssuesHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• Direct communication between host PC and all DSP peripherals

• Most of the active tests should be written in assembler

• Most functions involve multiple modules)Especially in “active tests”(

• Slave ports – no cross connections

• DMA buffer – no direct access

• Error correction in peripherals – find a way to “corrupt data”

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ScheduleHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• 15/08/02 Feasibility and requirements study

Design algorithms for testing of all modules except peripheralsDesign algorithms for testing of all peripheralsDesign global architecture

• 15/09/02 Intermediate report

Development of the control programDevelopment of the tests routines running on the host PCDevelopment of the tests routines running on the DSPFinal integration

• 31/10/02 Final report