4/29/2005 1

Phase Locked LoopPhase Locked Loop--Circuits & Circuits & Applications:Applications:

Theory, Analysis and DesignTheory, Analysis and DesignPasquale Lamanna Texas Instruments FranceABB & RF_IC Designer e-mail:p-lamanna@ti.com

BariBariMay 2005May 2005

4/29/2005 2

Talk Outline• Brief History• PLLs Classification• Basic Concepts• Phase-Locked Loops• Charge-pump PLL• Loop Components• What is Frequency Synthesizers ?• Phase Noise Analysis and its Effects on PLL • Basic PLL-Based Frequency Synthesizer• Integer-N Frequency Synthesizer• Fractional-N Frequency Synthesizer • Direct Digital Synthesizer• All Digital PLLs & Software PLLs Overview

4/29/2005 3

PLLs’ History• A first description of what is known as PLL was presented by H. de Bellescise in 1932

and coincides with the invention of “coherent communication”• First PLL IC arrived around 1965. This created an explosion in the use of PLLs.• The first digital PLL appeared around 1970. This was a classical digital PLL.• Few years later the firs all digital PLL appeared.• first Software PLL in the late year 80s• PLLs Today:

- In every cell phone, television, radio, pager, computers…- The most Prolific feedback system built by engineers.

§ To generate an output signal whose output frequency is programmable and rationale multiple of a fixed input frequency

§ To perform frequency modulation and demodulation.§ To generate the carrier from an input signal in which the carrier has been suppressed.§ Clock Recovery Circuits.§ Generation of Clock Signal.§ Frequency Synthesizer

4/29/2005 4

Classification of PLL Types

Software SoftwareSoftware MultiplierSPLL

Digitally ControlledDigitalDigital

DetectorADPLL

VoltageRCDigital DetectorDPLL

VoltageRCAnalog MultiplierAPLL

Controlled oscillatorLoop FilterPhase

DetectorPLL Type

4/29/2005 5

Analog PLL

outφ

VCOinφ errorφ ctrlV

•PLL syncronises the phase generated by an oscillator with the phaseof a reference signal by means of the phase difference of the two signals.

• Operates on excess phase of Vi(t) and Vo(t).• Negative feedback system with PD as an error amplifier.• “Locked” when phase difference between input and output

is constant with time:ttanconsoutin =φ−φ

( ) average.in ff 0dt

doutin

outin =⇒=φ−φ

4/29/2005 6

DIGITAL PLL

VCOLoop FilterChargePump

PFDFref

Fout

UP

DN

qDigital PFD Replace Analog MultiplierqPull in Range is limited only by VCO Tunability Range

qPFD +CP introduce another pole @0 giving a Type II PLL in this way it is possible to decouple BW and gain!q ! φe=0 for an input step frequency!

4/29/2005 7

Region of OperationsThere are four basic regions of operations describing PLL in dynamicand static states.• PLL is in dynamic state when the output is not locked or syncronised in phase with the reference.• PLL is in a static state when output is locked with reference.

hold range

pull in range

lock in range

4/29/2005 8

PLL REGIONS OF OPERATIONSHold range: Describes PLL in a static or locked state, it is the frq range in which a PLL can statically mantain phase tracking ( PLL is initially locked with ref signal, if the refsignal’s frq is slowly reduced or increased too much PLL will lose lock at the edge of the hold range.• PLL is conditionally stable only within the hold range.

Pull in range :Describes the PLL in a dynamic state ( aquisition mode ) it is the range within which a pll will always become locked through the aquisition process.PLL is initially unlocked , it will aquire lock if a ref frq wiithin the pull in range is applied. If the ref frq is outside the pull in range the PLL will not be able to lock onto the ref signal.

Lock range: Is a subset of lock in range, it is the frq range in which a PLL lock within a single-bit mode between the ref frq and output frq.PLL is initially unlocked

Pull out range: Describes the PLL in a static state, it is the dynamic limit for stableoperation; it is the value for a frq step applied to the ref frq that causes the PLL to unlock( PLL is initially locke dwith the ref signal, if a ref frq that is less than the pull out range isapplied to the ref signal the PLL will remain in lock; However , if the frq step excedees the pull out , the PLL will not be able to track the output signal and will fell out the lock.PLL may aquire lock again, but it may be a slow pull in process.

4/29/2005 9

Phase Detector

q Compare the phase difference between the input reference signal and the oscillator output signal and its output is a function of the phase difference between the two input signals.

Ø Is a multiplier in Analog PLLØ Is formed by logic gates in digital PLL

4/29/2005 10

Analog Phase detector

Analog Multiplierx1(t)

x2(t)

y(t)

φ∆α

=

φ∆+ωωα

+

φ∆+ω+ωα

=

φ∆+ω×ωα=

φ∆+ω=ω=

cos2AA)t(y

]t)cos[(2AA

]t)cos[(2AA

)tcos(AtcosA)t(y

)tcos(A)t(x,tcosA)t(x

21

2121

2121

2211

222111

2π

2π-

∆φ

y

Lock

4/29/2005 11

Digital Phase Detector

• Purpose: To produce a signal current or voltage, proportional to the difference in phase or frequency between two input signals.

∆ φ

Phase Detector

Vout(t)

∆φVout = KD

Vout

∆φKD

• Example

4/29/2005 12

Phase Frequency Detector

Up=0Dn=1

Up=0Dn=0

Up=1Dn=0V

R

V

R

V

R

S1 S2 S3

State Diagram

PFDRV

UpDn

Symbol

R

V

Up

Dn

fR > fV

V

R

Dn

Up

fR < fV V lagging R

R

Dn

V

Up

V

Up

R lagging V

R

Dn

4/29/2005 13

Phase Frequency Detector

1

2π

-2π

radians

Gain = 1 / 2 π

radians

Kd

Dead zone at zero phase error

D QCK R

DLCK

QDR

Up

Dn

R

V

Vdd

• Locks for 0 degree phase error• Edge triggered -- duty cycle

independent

τd

R

V

Up

Dn

θd

τd

4/29/2005 14

PFD with Charge Pump

• A switched current source is a good choice for a PFD output stage:- highly integrated- high impedance insures loop filter pole at zero- low noise because of tri-state operation- fast

• Configure the charge pump with equal up and down currents. The value of the current is used to calculate PFD gain : Id / 2π

Id

Id

S1

S2

Up

DnPFD

R

V CVCTL

Phase error :θe = θr - θv

“ On” time of either Up or Dn> tp = |θe|/ωr for each period of

2π/ωr of the reference signal.Average error current over a cycle

ed

dr

r

e

r

pD 2

II22

ti θ

π=

πω

⋅ωθ

=

ωπ

=

PFD gain : ( )( ) π

=θ

=2I

ssiK d

e

DD

4/29/2005 15

PFD with Charge PumpWhen in lock ΦE = 0 and When in lock no current is injected (ideally)

X

UP

Y

Down

Id

Id

S1

S2

Up

DnPFD

R

V CVCTL

4/29/2005 16

Charge Pump Design

VDD/2

up up

downdownG(s)

VDD

Vtune

VDD

offon

VtuneVDD/2

VDD/2

VDD/2

on off

Basic structure:fast current switching

Between twophase comparisons

up up

down down C1R1C2

GND

VDD

GND

GNDVpol

GND

VDD

Ipump

Vtune

Complete Differential Charge Pump

Circuit

4/29/2005 17

Type I Second-Order PLLR

C( ) RC ,

s11sF =τ

τ+=

( )VD

VDn2

nn2

2n

KK1

21 and KK ,

s2ssB

τ=ζ

τ=ω

ω+ζω+ω

=

• Limitations of simple type-I second-order PLL :

- Coupling between ζ, ωn, and K=KDKV> if K ⇑ to reduce static phase error, then ζ ⇓> if ωLPF = 1/τ ⇓ to reduce high-frequency output of PD, then ζ ⇓

- Coupling between loop bandwidth, suppression of high-frequency outputof PD, and capture range.

- Finite DC loop gain causes large static phase error.

4/29/2005 18

CP

Iqp

CZ

RZ

( ) ( )( )

1

pzzp

zzz

ppz2

zLPF

C1

C1R

CR

s1CCss1sZ

−

+=τ

=τ

τ++τ+

=

Type II Second-Order PLL I

• Defining with b the ratio of two capacitors the loop filter impedance

can be written as

PZ CCb =

( )

+τ+

τ+

+=

b1s1sC

s11b

bsZz

z

zLPF

4/29/2005 19

Type II Second-Order PLL IIq open loop transfer function is

q The cross-over frequency equals approximately

q The phase margin of the loop is:

( )

+τ+

τ+

+π=

b1s1Cs

s11b

bN2

KIsG

zz

2zVCOqp

0

N2RKI

CCC

N2RKI zVCOqp

pz

zzVCOqpc π

≈+π

=ω

( )

+ωτ

−ωτ=1b

garctanarctanPM czcz

4/29/2005 20

Type II Second-Order PLL IIq By differentiating the PM equation respect to it the maximum

phase margin is achieved at

q and the maximum phase margins is:

q Notice that the maximum phase margin is only a function of b parameter.

q To complete loop analysis forcing to be the crossover frequency of the loop and getting it in (2) results in:

cω

zc

1bτ

+=ω

++

−+=1b1bgarctan1barctanPM

cω

1bb

C1

N2KI1b

z

VCOqp2z +π

=τ

+

4/29/2005 21

Type II Second-Order PLL IIØ From previous equations a rigorous algorithmic can be developed

to determine the loop filter parameters for an optimal open loop gain characteristics.

q Algorithm: [1]

I. Define KVCO gain II. Choose a desired phase margin and find b from PM equationIII. Choose the loop bandwidth and find τzIV. Select Cz and Iqp such that they satisfied the last equationV. Calculate the noise contribution of R, if the calculated noise is

negligible the design is complete otherwise go back to step fourand increase Cz

4/29/2005 22

Filter G(s)

Zero for phase margin

( ) ( )( )

( )

1

1 2

1 2 1 2

11

( )P

P

sC RG s

sC s sCC C CC C C C C

Σ

Σ

+=

⋅ +

= +

= +

C

ω

|Gloop|dB

ωο Re(s)

Im(s)

unstabile

C

Rω

|Gloop|dB

ωο = ωz Re(s)

Im(s)

ω

|Gloop|dB

ωο

C1C2

R Re(s)

Im(s)

-40dB/dec

-40dB/dec

-40dB/dec

4/29/2005 23

Exercise

4/29/2005 24

Voltage Control Oscillator

VOUT has an angular frq that is controllable by output voltage of the loop filter Vc.

-θ0 is the center frq of VCO (i.e. the out frq when Vc=0)-kVCOis the voltage controlled oscillator conversion gain.

•Output phase is equal to the integral on the frq variation ∆θ(t).

dtVkdt)t( cVCOOUTOUT ∫∫ =ω∆=φ

)t(Vk)t()t( cVCO0OUT0OUT +ω=ω∆+ω=ω

Vc ωOUT

sk VCO

)s(Vs

k)s( cVCO

OUT =φ

]dt)t(vKtcos[A)t(y ∫t

∞contVCOFRC +ω=

4/29/2005 25

PD LPF VCO Vo(t)Vi(t)

Vi(t)

Vo(t)

PDoutput

LPFoutput

t

A Walk Around the Loop

4/29/2005 26

Phase Locked Loop• The open loop transfer function of any PLL is:

( ) ( )( )

( )( ) sticscharacteripassLow ---sFKKs

sFKKsssH

CPVCO

VCOCP

i

oPLL +

=φφ

=

( ) ( )( ) ( ) sticscharacteripassHigh---

sFKKss

sssH

CPVCOi

ee +

=φφ

=

PhasefrequencyDetector

Low Pass FilterF(s)

VCOKVCO

ChargePumpKCP

N1

refφoutφ

( ) ( )s

KN1sFKsG VCO

CP=eφ

4/29/2005 27

Phase Error Function

∆ω

∆ω

KωΔ

ωin

ωout

Φe

t

2nn

2n

2

e

in

ee

ω+sως2+ssως2+s

=)s(H1=)s(H

)s(Φ)s(Φ=)s(H

22nn

2n

2inee

22nn

2

2n

inout

sωΔ

ω+sως2+ssως2+s

=

)s(Φ)s(H=)s(ΦsωΔ

ω+sως2+sω

=

)s(Φ)s(H=)s(Φ KωΔ

=

ως2

ωΔ=

)s(φslim=)∞=t(φ

n

e0→se

4/29/2005 28

Voltage-Controlled Oscillator

Vcont ωout

KvωFR

Vcont

ωout

GND

Vout

Vcont

ω ωout FR v contK V= +

( ) ( )φ ωc FR v contt K V dt= +∫

( ) ( )V t A t K V dtout RF v contt= + ∫−∞cos ω

φexcess v contK V dt= ∫

( )( )

φ sV s

Kscont

v=

Excess phase :Example:

• VCO is an ideal integrator.• Output phase depends on the history of control voltage.

4/29/2005 29

VCO Model ( Feedback Model )

Vi G(A,ω)

H(ω)

Vo

( ) ( )( ) ( )B A V

VG AH G A

o

i, ,

,ωω

ω ω= =

−1

Basic Idea :Loop gain should be 1 at asteady state to achieve oscillation.

- Start-upH(ω) G(0,ω) >1Arg (H(ω) G(0,ω) )=2nπ

- Steady StateH(ω) G(A,ω) =1Ang (H(ω) G(A,ω) )=2nπ

Vo has finite value even though Vi=0. This requires loop gain H(ω) G(A,ω) =1 to have a pair of nonzero poles in right half plane , which gives

( ) ( )V t V e to ot= α βcos

4/29/2005 30

VCO Model ( Negative Resistance Model )

i = f (V)ActiveCircuit

FrequencyDeterminingCircuit

Za (A,ω) Zf (ω)

V

- GaGLC V

i = f(V)

VCNR

Parallel Resonator

i

V

Basic Idea :

Losses in the frequency determiningcircuit are compensated by a negativeresistance seen into the active circuit.

Start-up conditions:

Xa(ωo) + Xf(ωo) = 0

Ra(ωo) + Rf (ωo ) < 0

At steady state:

Xa(A, ωo) + Xf(ωo) = 0

Ra(R, ωo) + Rf (ωo ) = 0

4/29/2005 31

Frequency Step at Input

PD LPF VCO Vo(t)Vi(t)

Vi(t)

Vo(t)

PDoutput

KD∆φLPF

outputt

to

ωo ωo+∆ω

• PLL system has memory.• In lock, input and output frequencies are equal.

4/29/2005 32

Charge Pump PLL

Ip

Ip

S1

S2

Up

Dn

PFDR

V C

VcontVCO

( ) Vp

Vp2

Vp

KC1

2I

js K

C1

2I

s

KC1

2I

sB ⋅π

±=⋅

π+

⋅π=

• Oscillation!!• Need loop-stabilizing zero to keep the PLL stable.

4/29/2005 33

Charge Pump PLL with Zero

Id

Id

S1

S2

Up

Dn

PFDR

V C

VcontVCO

R

( ) ( )ssCsCR1

2I

SV ep

cont θ

+

π=

( )( )

Vp

Vp2

Vp

KC2

IRsK

2I

s

KsCR1C2

I

sB

π+

π+

+π=

Vp

Vp

n K2

CI2R,K

C2I

π=ζ

π=ω

IP

Ip/C

IpR

Vcont

Modulate VCO frequency=> cause reference sideband spurs

C1

Filter the high frequency ripple

C1

4/29/2005 34

Divide-by 4 or 5 Cell

D Q

QbC

D Q

QbCQ1 Q2

D Q

QbCQ3

CKOUT

MC0 0 0

1 0 0

1 1 0

0 1 0

0 1 1

0 0 1MC: X

X0

1

10

10

X

4/5 decision point

CK

Q1

Q2/OUT

Q3

MC

4/29/2005 35

D-Type Flip-Flop with Merged NAND Gate

Vdd

Pbias

A

AbB

Bb

CKCKb

GND

M1 M2

M3 M4

M5 M6

M7 M8M9 M10

M11 M12

M13M14

Q

Qb

M15 M16 M17M18

IB IB

4/29/2005 36

Dual Modulus Prescaler ( P/P+1)

4/5CK OUT

MC D Q

QbC

D Q

QbC

D Q

QbC

D Q

QbC

MC

OUT

CK

Divide-by 64/65 Prescaler

• Dual modulus prescaler consists of synchronous and asynchronouscounters

• Each stage of extender runs at 1/2 frequency of previous stage.• For fast operation and low digital noise, CML is used• In current mode logic design, supply current may be scaled down

in slower stages

4/29/2005 37

True Single Phase Clock /2 divider& Divider operation

ck ck

VDD

GND

D

D

VDD

CK=0

CKD

CK=VDD

VDD

ckck

GND

D

D

D

CK frequency halved

ck ck

VDD

GND

D

D

VDD

ckck

4/29/2005 38

Basic divider component: LatchVDD

Vbias

ck ck

out out

inin

VDD

Vbias

ck ck

out out

In-data sample Hold

Source Coupled Logic (SCL) Latch

4/29/2005 39

E-TSCP for 2/3 divider

MC

÷2 ÷2/3÷2 MC

FFD Q FF

D Q

in

QoutQ

in

MC

out

3 2

in in in in

in3 3 2 3

0.5

3

1.3 2 2

1.5

0.5 0.5 1.3 3

VDD

GND

Extended TSPC logic: “ratioed” logic

4/29/2005 40

• A frequency synthesizer generates a user selectable set of frequencies from a fixed frequency reference.

• Goals in frequency synthesizers for wireless communications:Low Cost : consumerLow power consumption & low supply voltage : PortableHigh performance

- Signal quality : phase noise & spurs- Frequency accuracy- Frequency switching time

• Frequency Synthesizer : PLL-based frequency synthesizer- Integer-N synthesizer- Fractional-N synthesizer

Direct digital frequency synthesizer(DDFS)

Frequency Synthesizer

4/29/2005 41

Phase Noise Overview

qNoise Sources

qLinear Time Invariant model

qThe Linear Time Variant (LTI) Model

qNoise in Voltage Controlled Oscillators

qPhase Noise in Digital and Analog World

qFrom Phase Noise to jitter

4/29/2005 42

Noise Ø Device Noiseq Thermal Noiseq Flicker Noiseq Shot Noise

Ø InterfererqPower Supply NoiseqSubstrate Noise

Massive grown in wireless communications demands for more available channels imposing prohibitive requirements on phase noise in local oscillator LO

In digital applications noise manifests himself as jitter limiting the max clock frequency as well as A/D and D/A interface circuits resolutions

4/29/2005 43

Ideal vs Real OscillatorqIdeal Sinusoidal Oscillator

Spectrum is a couple of impulses @

qReal Sinusoidal Oscillator

Noise impacts Amplitude as phase, its spectrum is not anymore an impulse but presents skirts.

The function is a periodic function of period

( ) ( )00o tcosAtV φ+ω=

0ω− 0ω ωconst0 =φ

0ω±

( ) ( ) ( )[ ]ttftAtV 00o φ+ω⋅=

0ω− 0ω ω

π2( )•f

4/29/2005 44

single sideband noise spectral density

• There are many ways for quantifying fluctuations due to noise. Signal’s short-term instabilities are usually characterized in terms of the single sideband noise spectral density.

L

• represents the single sideband power at a frequency offset of from the carrier with a measurement bandwidth of 1Hz.

• Note that the above definition includes the effect of both amplitude and phase fluctuations.

{ } ( )

ω∆+ω=ω∆

carrier

0sidebandP

Hz1,Plog10

HzdBc

( )Hz1,P 0sideband ω∆+ω

L(ωm) dBc

ω

spur

ω∆+ω0

4/29/2005 45

ωo ωint

Desired Band

blocker

Phase Noise in Transceveir I

Band PassFilter

Band PassFilter

FrequencySynthesizer

PA

LNA

ChannelSelectionDuplexer

Filter

ωωo ωint

Desired Band

blocker

ωo ωint

Desired Band

blocker

LOω ω

ωωIF

IFsint ωωω =

FILTER

IFLO0 ωωω =

IF

Base Band

4/29/2005 46

ωo ωint

Desired Band

blocker

Phase Noise in Transceveir II• Phase Noise Limits the receiver sensitivity!

Band PassFilter

Band PassFilter

FrequencySynthesizer

PA

LNA

ChannelSelectionDuplexer

Filter

ωωo ωint

Desired Band

blocker

ωo ωint

Desired Band

blockerIF

LOω ω

IFsint ωωω =

FILTER

ωωIF

IFLO0 ωωω =

Base Band

4/29/2005 47

Linear Time Invariant Phase Noise Theory

• Simpler Oscillator• At anti-resonant frequency, admittanceis zero

• Quality Factor

• Restoring circuit gives energy to oscillator in periodic manner to restore oscillation amplitude

RESTORING ENERGY

LOSSLESSR L C

( )

ω−ω+=ω

LC11CjGY 2

LC1

0 =ω

ederDissitatAveragePowedEnergyStorQ ω=

4/29/2005 48

Oscillator –Few Equations• For frequencies near to the resonant frequency

• Complete impedance is:

• Where –R is the mean equivalent resistance• of active circuit

ω∆+ω=ω 0

( ) ( )( ) C2jG

LLC2jGY

0

00 ω∆+≈

ω+ω∆

ω+ω∆ω∆+=ω∆+ω

( )

0

0 Q2j1

1G1

GC2j1

1G1

C2jG1Z

ωω∆+

⋅=ω∆+

⋅=ω∆+

≈ω∆+ω

RESTORING ENERGY

LOSSLESSR L C

-R

( )

0

0 Q2j

1G1Z

ωω∆

⋅≈ω∆+ω

4/29/2005 49

single sideband noise spectral density

• R is the only noise element in Oscillator and its noise is

From L

½ taking in account the equiripartion theorem of thermodynamics

L

F takes in account all other noise elements present in the restoring energy lossless

kTG4f

i2=

∆

{ }

ω∆ω

=ω∆2

0

carrier Q2PFkT2log10

2022

sideband Q2kT4GZiP

ω∆ω

==

{ }( )

ω∆+ω=ω∆

carrier

0sideband

P

Hz1,P21

log10

4/29/2005 50

Linear Time Invariant Model• L

• For reducing phase noise High Q values are demanding as well as maximize output swing.

Unfortunatly maximize Q involves also a higher F values. q This equation predict the phase noise of Oscillator but is not able to catch a

quantitative model for real Oscillator.

q Real Oscillator

{ }

ω∆ω

=ω∆2

0

carrier Q2PFkT2log10

HzdBc

L(∆ω)

log∆ω

-3

-2

4/29/2005 51

Leeson LTI Model and its Limits• Lq It is empiricq Factor F is note a posterioriq It is not able to predict the noise corner1/fq It is not possible to predict the corner of

White noise plateau as its value

q The Leeson Model is not able to quantify in a correct way phase noise aspects of a real oscillator ( What is wrong?)

{ }

ω∆

ω∆

+

ω∆ω

+=ω∆3f

120

carrier1

Q21

PFkT2log10

L(∆ω)

log∆ω

-3

-2

3f

1ω∆

carrierPFkT2

4/29/2005 52

Understand Noise in Oscillatorsq LTI Model gives qualitative but not exhaustive quantitative informations:

!something missing?

q LTI not able to explains the creation of new harmonics!q LTV model, extensive invocated due to high non linearity of Oscillators, can

explain these phenomena but fails on quantifying their amplitudes.q What about sinusoidal Oscillators? (XTAL)

OscillatorLTI

noiseω0ω

noiseω0ωWRONGWRONG

RealOscillator

noiseω0ω

noise0 ω±ω

0ω

4/29/2005 53

Oscillator Noise ModelqOscillator is a circuit with n inputs, one for each

noise source, and two outputsqFrequency Oscillation is an intrinsic

characteristic of Oscillator

qThe “Oscillator System” is a Linear Time Variant System!

( ) ( ) ( )[ ]ttftAtV 00o φ+ω⋅=

RealOscillator

0ω ( )t0φ

( )tA

noiseinputs

4/29/2005 54

The Oscillator System Iq Effect of same

noise current impulse on a sinusoidal (linear) LC oscillator injected at different times

q In both cases output present a same variation

ni

CqV =∆

4/29/2005 55

The Oscillator System II• Phase-to-Noise Transfer Function is Linear even if the active elements

constituting the Oscillator experiments high non linearities!• The effect of noise on phase is high dependently from the time it appears in

the system.• Whereas variation on amplitudes are absorbed by system, variation on

phase persists indefinitely in the Oscillator• What is noise? It is a perturbation superimposed on an existing oscillations.

The assertion of linearity is held for .• How we can represent it?

Ø Oscillator in its noise behaviour is a "Linear Time Invariant System !”q Could be characterized by its impulse response

maxnoise qq ≤

( )τφ ,th

τ

niτ

( )tφ

( )τ,thA

τ

ni ( )tA( )tφτ

( )tA

4/29/2005 56

Phase Noise Impulse response I

• Is a periodic function of period 2p. Thake account of different sensitivity of Oscillator to the noise injected @ phase !

• It is called Impulse Sensitivity Function (ISF) and it is a-dimensional independent from frequency.

• Output of Oscillator de to input noise present a time varying phase:

• is periodic could be expandend in taylor series

• Only few terms of series give not negligible contribute

( ) ( ) ( )τ−τωΓ

=τφ tuq

,thmax

0

( )τωΓ 0τω0

( ) ( ) ( ) ( ) ( ) ττ⋅τωΓ=ττ⋅τ=φ ∫∫∞−

∞+

∞−φ di

q1di,tht

t

omax

( )τωΓ 0

( ) ( )no1n

no

o ncosc2c

θ+τω+=τωΓ ∑∞

=

4/29/2005 57

Phase Noise Impulse response IIq Important quantitative informations for designing a low phase noise

Oscillator inside equation!

q Block Diagram of

q Block Diagram of Mathematic sequences is the same as a Direct Conversion RF Receiver

( ) ( ) ( ) ( )

ττωτ+ττ=φ ∫ ∑ ∫

∞− ∞−

t t

on0

maxdncosicdi

2c

q1t

( ) ( ) ( ) ( ) ( ) ττ⋅τωΓ=ττ⋅τ=φ ∫∫∞−

∞+

∞−φ di

q1di,tht

t

omax

( )τωΓ 0

( )maxqti

∫∞−

t ( )tφ

( )τωΓ 0

( )maxqti ( )tφ

4/29/2005 58

Phase Noise Impulse response III( ) ( ) ( ) ( )

ττωτ+ττ=φ ∫ ∑ ∫

∞− ∞−

t t

on0

maxdncosicdi

2c

q1t

2c0

( )maxqti ( )tφ

( )101 tcosc φ+ω

( )n0n tncosc φ+ω

( ) tcosIti 0 ω∆=

( ) ∫∞−

τωτ∆=φt

max

00 dcosq2

cIt

( ) ( )[ ]tmcosIti 0m ω∆+ω=

( ) ∫∞−

τωτ∆=φt

max

mm dcosq2

cIt

( ) ( )tsinq2

cItmax

00 ⋅ω∆ω∆

=φ

( ) ( )tsinq2

cItmax

mm ⋅ω∆ω∆

=φ

4/29/2005 59

Phase Noise Impulse response IV

q A noise tone at an offset from carrier or harmonics generates a new tone at a different frequency. More again its amplitude is a linear function of input amplitude as confirmed by simulations and measurements.

q !! Spectrum of phase φ(t) has been determined not the spectrum of output voltage !!

OscillatorLTVω

0ω

ni

( )τωΓ 0

2c0 1c 2c nc mc

ω∆+ω0n

( )tφ

ωω∆

ω∆

4/29/2005 60

Phase – Voltage Conversion• Amount of Voltage power due phase noise

Ø Even in Phase-Voltage conversion is a non linear transform LTV model entails in f(t) quantification. The concept of nonlinearity heldsin PM modulation for determining the voltage spectrum

Ø Hence injecting a sinusoidal tone at an offset from oscillator frequency or its harmonics produces a couple of tones in the Spectrum of Vat as simulations and measures confirm

( ) ( )( )ttcosAtV 0o φ+ω=

( ) ( )( ) ( ) tsintAtcosAttcosAtV 000o ωφ−ω≅φ+ω=

( ) ( )tsinq2

cItmax

mm ⋅ω∆ω∆

=φ

( ) ( )( ) ( ) ( )[ ]tcostcosq

cIA41tcosAttcosAtV 00

max

mm00o ω∆−ω+ω∆+ω

ω∆+ω≅φ+ω=

4/29/2005 61

single sideband noise spectral density using LTV Model

From L

The term ½ is not present because we have that all noise transforms in phase noise

L

q !! Noise amplitude is a linear function !!q You want less phase noise? ! Reduce cn coefficients and maximize qmax !

2

max

mmsideband q

cAI41P

ω∆

=

{ } ( )

ω∆+ω=ω∆

carrier

0sidebandP

Hz1,Plog10

{ }

ω∆

=ω∆2

max

mmq

cI412log10

4/29/2005 62

single sideband noise spectral density using LTV Model

From L L

If we use Parsifal Theorem

L

q Alert ! This equation contains less information than previous one!

{ }

ω∆=ω∆ 22

max

2m

2m

qcI

81log10 { }

ω∆

∆=ω∆

∑∞

=22

max

0n

2n

2n

q

cf

i

41log10

( ) 2rms

22

00n

2n 2dxx1c Γ=Γ

π= ∫∑

π∞

=

{ }

ω∆

Γ∆=ω∆ 22max

2rms

2n

qf

i

21log10

4/29/2005 63

Phase Noise - Exercise 1-• Use LTV model L to determine the LTI equation

• L

v Result is two time bigger because the assertion all noise is converted in phase noise

{ }

ω∆

Γ∆=ω∆ 22max

2rms

2n

qf

i

21log10

{ }

ω∆ω

⋅=ω∆2

0

carrier Q2PFkT22log10

RkT4

fi2n =

∆maxloadmax VCq =

RV

21P

2max

carrier =

4/29/2005 64

Flicker Noise in Oscillators

• LTV model asserts this noise is weigthed by c0 coefficient only

• L

• Equating the arguments we find an important design equation

• In High Deep CMOS technologies where flicker noise is very high it is mandatory to reduce c0coefficient for low noise oscillators.

f1ω

ω∆

ω⋅= f

12n

2

f1,n

iif

1ω≤ω∆

{ }

ω∆ω∆

ω⋅∆=ω∆

1q

cf

i

81log10 22

max

f1

20

2n

Whereas for white noise we have:

L { }

ω∆

Γ∆=ω∆ 22max

2rms

2n

qf

i

21log10

f12

rms

20

3f1

12c

ωΓ

⋅=ω∆

4/29/2005 65

Simulated Impulse Sensitivity Function

ISF vs Tinject (N=3, fo=1.8GHz)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 1 2 3 4 5 6 7

Tinject (rad)

ISF

4/29/2005 66

LTV Model – Conclusions-Ø LTV Model quantify in mathematical way constraints to follow for

design Low Phase Noise Oscillatorsq Maximize qmax Maximize Output Voltage Swingq Reduce q The active circuit used in each Oscillator to supply for losses must

delivery energy all at once at the phase in which circuit is less sensitive to the noise

q Duty Cycle of 50% is mandatory because this waveform reduces thevalue of cn coefficients for n even

q Reduce c0 coefficient to minimize Flicker Noise

is two times d.c. value and to minimize its value it is mandatory having a symmetric output voltage( rise fall)

q The output impedance must be linear

rmsΓ

( )dxx1c2

00 ∫

πΓ

π=

4/29/2005 67

Impulse Sensitivity Function ISF How to calculate

qBy means of simulations:Noise impulse is injected at different phase

moments (0…..2π) then after few cycles the phase shift is measured

then is calculated and multiplied by qmax

qDirectly from output signal properties

Tt2 ∆

π=φ∆

( )τφ ,th

4/29/2005 68

JITTER vs PHASE NOISE• Why different definitions for the same phenomena?

Clock Generation FrequencySynthesis

Digital World Analog World

Jitter PhaseNoise

always

constraints

PLL

4/29/2005 69

Phase Noise and Timing Jitter analysis

• Phase noise and timing jitter– Phase noise

• Measure of spectral density of clock frequency• Units: dBc/Hz (decibels below the carrier per Hz)• à Analog people care about this

– Timing Jitter• Measurement of clock transition edge to reference• Units: Seconds (usually pS)• à More intuitive, useful in digital systems

4/29/2005 70

Jitter Definitionq The n-th period is defined as:

q For an ideal clock this time difference is independent of n, but in reality it varies with n as a result of noise in the circuit. This results in a deviation from its mean period :

q The quantity ∆Tn is an indication of jitter.

Ideal Clock

Real Clock

Long term jitter1TT ∆+

nt

2TT ∆+

jt

n1nn ttT −= +

TTT nn −=∆

4/29/2005 71

Jitter Definitionsq If is a sequence of transition times with nominal period T

q The sequence characterizes the long term jitter and limits the resolution of

A/D Converters

q period jitter characterizes the variation in the period from the nominal or average period

it reduces the time available for data processing per clock cycle; the period jitter is the first difference

of absolute jitter.

q Jitter over k-period is

q The first difference of period jitter provides another measure of jitter called adjacent period jitter

It characterizes the local changes in the period from one cycle to the adjacent one

{ }nt( ) { }TntnA nj −=

( ){ }TttTP n1nnjitter −−= +

( ) ( ) ( ){ }TntTkntTkttkTP nknnknnjitter −−+−=−−= ++

( ) ( ) ( ) ( ){ }n1n1n2nnjitter1njittern ttttTPTPjitter −+−=−=∆ ++++

4/29/2005 72

Jitter from Phase Noise I• The variance for stationary absolute jitter is related to the total area

of its power spectrum

• From relation between period jitter and absolute jitter it is possible to write

• the variance for period jitter is

• more generally the variance over k period is

( )( )dffS

f21

20

2A ∫

∞+

∞−φ

π=σ

( ) ( )nA1nAP jjnjitter −+=

( )( ) ( )dffSfTsin

f1 2

20

2j ∫

∞+

∞−φπ

π=σ

( )( )

( ) ( )dffSfkTsinf1kT 2

20

2j ∫

∞+

∞−φπ

π=σ

4/29/2005 73

Jitter from Phase Noise IIExercise

q determine the variance for adjacent absolute jitter

( ) ( ) ( ){ }nPknPkTj njnjn −+=∆

( )( ) ( ) ( )( ) ( )( )2knj

knjnjnj

kkTnj 1zzA1zzPzPzPzzP +=+=−=∆

( ) ( )( ) ( ) ( ) ( )( ) 22k22k2

nj2

kTnjkTnjP 1zzS1zzAzPS +=+== φ∆∆

( )( ) ( )( )

( )( ) ( )dffSfkTsin

f4dffS

f21kT 4

20

kTnj

P20

2j ∫∫

∞+

∞−φ

∞+

∞−∆∆ π

π=

π=σ

4/29/2005 74

PLL Noise Transfer Functions NTFq Each building block in the closed loop structure of PLL is an inherit source of noise ,

and its contribution to the output total noise could be easily obtained using following formula

q where is the noise transfer function from each input noise to the PLL output whereas the open loop function is:

( ) ( ) ( )2iniclosedi jHfSfS ω⋅= φφ

( ) ( )s

KN1sFKsG VCO

CP=

outφPhasefrequencyDetector

Low Pass FilterF(s)

VCOKVCO

ChargePumpKCP

N1

refφeφ

nXTALφnPFDφ nCPi

nLPFV nVCOφ

nDIVφ( )ωjH in

4/29/2005 75

PLL Noise Transfer Functions NTF IIq The closed loop transfer function of PLL is

q The contribution of the input noise on the output is

q The PFD introduces noise contribute that manifests as jitter on DN and UP outputs

q Charge pump block introduces different noise contributions as mismatch in UP and DN currents, Dead Zone and PSR and its noise transfer function at system level is:

( ) ( )( )sG1NsGsHPLL +

⋅=

( ) ( )( )

( )( ) ( )sHsG1NsG

sssH PLL

nXTAL

CLKOUTnXTAL =

+⋅

=φ

φ=

( ) ( )( )

( )( )

( )( ) ( )sH

K1

sG1NsG

K1

sG1s

KsFK

sssH PLL

PFDPFD

VCOCP

nPFD

CLKOUTnPFD ⋅=

+⋅

=+

⋅⋅=

φφ

=φ

( ) ( )( )

( )( )

( )( ) ( )sH

KK1

sG1NsG

KK1

sG1s

KsF

sissH PLL

CPPFDCPPFD

VCO

CP

CLKOUTCPi ⋅

⋅=

+⋅

⋅=

+

⋅=

φ=

4/29/2005 76

PLL Noise Transfer Functions NTF IIIq Loop Filter is the third critical component in the loop because the noise

present at output module the VCO by means of its KVCO gain

q Error introduced by the VCO is a phase error and its transfer function is:

q Finally error introduced by the loop feedback divider N is:

( ) ( )( ) ( ) ( )

( )( ) ( ) ( )sH

sFKK1

sG1NsG

sFKK1

sG1s

K

sVssH PLL

CPPFDCPPFD

VCO

nLPF

CLKOUTnLPFV ⋅

⋅=

+⋅

⋅=

+=

φ=

( ) ( )( ) ( ) ( )

( )( ) ( )

( )sHKsFKK

ssG1NsG

sKsFKK

1sG1

1s

ssH PLLVCOCPCPVCO

CPCPVCO

CLKOUTVCO

⋅=+

⋅

⋅=

+=

φφ

=φ

( ) ( )( )

( )( ) ( )sHsG1NsG

sssH PLL

nDIV

CLKOUTnDIV =

+⋅

=φ

φ=φ

4/29/2005 77

Jitter and Phase noise in First Order PLL

• l

PhaseDetector

VCOKVCO

N1

refφeφ

nXTALφnPDφ

nVCOφ

outφ

( )( )

( )lVCOPFDVCO

nVCO

CLKOUTs

s

sKK1

1sHss

ω+=

⋅+==

φφ

φVCOPFDl KK ⋅=ω

4/29/2005 78

Jitter and Phase noise in First Order PLL – VCO Noise -

q The power spectral noise of output is

q Due to the fact that for the phase noise of output CLKOUT is the same as the phase noise of VCO. This equation emphasizes as the loop adjusts VCO control voltage to compensate for its slow random variations which are slower than loop’s dynamics but is not able to react fast enough to high frequency random changes in the VCO output and hence these fast variations appear directly on the output

( ) ( )ω⋅ω+ω

ω=ω φφ nVCO2

L2

2

CLKOUT SS( )ωφS ( )ωφ nVCOS

1ω

( )ωφ nVCOS

( )ωφ nVCOH

L

2A 2

cω

=σ

( ) ( )kTL2A

2j e12kT ω−−σ=σω

4/29/2005 79

Jitter and Phase noise in First Order PLL - XTAL input noise -

qThe power spectral noise of output is

( ) ( )ω⋅ω+ω

ω=ω φφ nXTAL2

L2

2L

CLKOUT SS

N

( )ωφS

( )ωφOUTS

( )ωφ nXTALS

( )ωφ nXTALH

Lω ω

4/29/2005 80

Frequency Spectrum of RF Signal

fBW

20 log(N1)

Synthesizer phase noise floor

Spurs

VCO inherent phase noise

In-band phase noise

Carrier

Noise peaking due to loop transfer function

20 log(N2)

N1 > N2

4/29/2005 81

Phase Noise

Phase noise : -59.7 dBc/Hz @ 500Hz offset with a carrier frequency of 1.8 GHz.

4/29/2005 82

BEHAVIORAL MODELING OF APLL

Manuel CAMUSApril - September 2004

Training supports : Francois Bauduin & Pasquale Lamanna

4/29/2005 83

BEHAVIORAL MODELING OF APLL

PLL’s characteristics– 2 modes over 5 are fractional

(prescaler mode N/N+1)– Compensation of the phase error by

opposite current injection ( by means of DAC )

– Integrated Loop Filter

PFD CPDAC

ACCMOD

IBIAS

LF VCO

LOOPCNT

CKF

RCK

LOCKDET

UP

DNZ

UP2 DNZ2

VCTL FOUT

LOCK

Digital blocks

Analog blocks

N

N

sNKvsZIcp

irsG LF

O ⋅⋅⋅

=ΦΦ

=)()(

PLL’s equations :Open loop ClosOpen loop Close loope loop

)(1)()(sG

sGsGcO

O

+=

4/29/2005 84

BEHAVIORAL MODELING OF APLLAPLL’s Model

PLL's blocks Type of Model Supply noise Phase Noise Other Non-ideal ParametersPFD Verilog or VerilogA no yes Dead Zone

Delay on Up & DnzCP VerilogA yes no Mismatch beetwen UP & DNZ

Output ResistorDAC VerilogA and Verilog no no Current Mismatches LOOPFILTER VerilogA or Spice yes no Leakage Current

Parasitic capcitorVCO VerilogA yes yes Intrinsic JitterDIVIDER VerilogA or Verilog no yes Delay IBIAS VerilogA yes noACCMOD Verilog no noLOCKDET VerilogA no noTEST Verilog no no

• PLL Modeling:– Main function : Not complicated– The major point : understand the significant non-ideal parameters to

modeling – Model’s description :

4/29/2005 85

0

10

20

30

40

50

60

70

100 1000 10000 100000

Supply noise frequency (kHz)

P2P

Jitte

r (ps

)SchemaModel

• Main function plus Supply Noise, Phase Noise & Intrinsic jitter

• Model’s Parameters : only 8– Free running frequency ( Hz ) : – VCO gain ( Kv in Hz/V) : – VCTL Locked ( in Volts ) :– VCO intrinsic Jitter– Power supply rejection :

• Static sensitivity :• Variation vs. frequency ( filter effect )

– Phase Noise : Sideband Power (dBc) at delta frequency ( Hz ) :

BEHAVIORAL MODELING OF APLLExample of critical Block : VCO

VNOISEKVCTLVDDAVCTLKFF LOCKEDVCOcVCO ⋅+−−⋅−= 0))((

VCOK

cF

TFFFVCO

VCOVCO ∆⋅+

=1

LOCKEDVCTL

OK

noisephaseintrinsic TTT _∆+∆=∆

20)(

2/3 10)(f

cT f

fTΓ

∆ ⋅=σ

VCO Supply noise Model

4/29/2005 86

• Time simulation comparison : ( Transient Analyze : 20us )

BEHAVIORAL MODELING OF APLL

VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps)

0.21 12 0.31 13 49.45 104 48.87 1013.53 99 3.76 100 50.92 174 51.22 1773.85 106 3.43 106 50.37 142 50.35 1430.34 16 0.35 19 49.51 107 48.94 102

VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps)

50.55 36 50.62 34 50.59 16 50.64 1453.03 120 53.29 126 52.98 97 53.15 10251.26 113 51.68 108 53.97 107 53.51 11050.58 46 50.22 40 50.81 28 50.27 20

Clean Supplies Supply Noise 10MHz 50mV P2PModel Schema Model Schema

Supply Noise 1MHz 50mV P2P Supply Noise 100KHz 50mV P2PModel Schema Model Schema

MC384 Modeinteger 1

fractionnal 1fractionnal 2

fractionnal 2integer 2

integer 2

MC384 Modeinteger 1

fractionnal 1

• Output results comparison :

Schematic Model10 850 min 24 min

• Waveforms comparison :

VCTL

Outputperiod

Outputperiod

VCTL

Model :

Schematic :

÷450

4/29/2005 87

• Period Jitter :

• Variance :

• Khinchin theorem:

• VCO Phase noise spectrum :

• Model :

• Results :

∫∞

∆ ∆⋅=0

22

0

2 )(sin)(8 dfTffST πϖ

σ θTcT ⋅=∆

2σ

20)(

2/3 10)(f

cT f

fTΓ

∆ ⋅=σ

[ ]{ } [ ] [ ]2

02

0

2

20

22

20

2 )()(E2)(E)]([)()(1ϖ

θθϖ

θϖθ

θθϖ

σTttTttEtTtET

∆+⋅⋅−

∆++=−∆+=∆

[ ])()(E)( τθθτθ +⋅= ttR )]()0([22

0

2 TRRT ∆−=∆ θθϖσ

∫∞

∞−

= dfefSR fj τπθθ τ 2)()(

)()( 322

fc

fcffS FN

c +⋅=Φ

TttT nnn −−=∆ +1

Tfcfc

TTTFvco

c ∆⋅+=

∆+==

111

Schema ModelRMS Jitter (ps) 5.7 5.7P2P Jitter / 300 samples (ps) 33.2 32.3P2P Jitter / 30000 samples (ps) 46.9 52.9

BEHAVIORAL MODELING OF APLLAppendix 3 : VCO phase Noise Model

4/29/2005 88

φiPFDCP LF VCO

LOOPCNTDivider M

CKF

RCK

Icp VCTL FOUT

Reference Noise

++ +

+

PFD CPNoise

VCONoise

DividerNoise

φnrφnc

φnd

φnv

• Reference Noise :

• CHPUMP Noise :

• VCO Noise :

• Divider Noise :

)(1)(

)(1

)()(1

0

00

sGsGN

sKv

NsZIcp

sKvsZIcp

nrsT

+⋅=

⋅⋅+

⋅⋅==

φφ

)(1)(

)(1

)()(2

0

00

sGsG

IcpN

sKv

NsZIcps

KvsZ

ncsT

+⋅=

⋅⋅+

⋅==

φφ

)(11

)(1

1)(30

0

sGs

KvN

sZIcpnvsT

+=

⋅⋅+

==φφ

)(1)(

)(1

)()(4

0

00

sGsGN

sKv

NsZIcp

sKvsZIcp

ndsT

+⋅=

⋅⋅+

⋅⋅==

φφ

BEHAVIORAL MODELING OF APLLAppendix 4 : Noise in PLL

4/29/2005 89

• Second order LoopFilter :

R=20k C1=80pF C2=1.8pF

• Integrated LoopFilter : Capacitor with transistor– Current Leakage– Capacitor Variation vs. VCTL

)1()(

1)(

10

1010

1

sCC

CCRsCC

RCsH

++⋅⋅+

+=

fz fp

-20dB/dec

-20dB/dec

f ( log )

Current Leakageeffect on VCTL :

BEHAVIORAL MODELING OF APLLAppendix 5 :Loopfilter

4/29/2005 90

• ACCUMULATOR MODULO-P : Example: 13->99 MHz :

M=8P=13

• Phase Error Compensation :

61538.71388

1357

1399

=+=

BEHAVIORAL MODELING OF APLLAppendix 6 : Fractional Mode

4/29/2005 91

PCS CDMA Transceiver

ADC & DAC

Filters

Modem

LNA

1855 MHz

1619.62-1649.62MHz

220.38 MHz

÷2

PLL

Resonator

Q

I

1750-1780 MHz

Q

÷2

130.38MHz1900MHz

SAW

1619.62-1649.62 MHzI

260.76 MHz

Tank

Duplex

PLL

1840-1870MHz

4/29/2005 92

Synthesizer Circuitsq Reference Oscillators

q Phase Frequency Detectors (PFDs)

q Charge Pump and Loop Filters

qVoltage-Controlled Oscillators (VCOs)

q Frequency Dividers

4/29/2005 93

Reference Oscillators

• Generally based on Quartz Crystal ( Q > 10000 )

• Crystals are designed to operate at a single frequency in range 1 to 100 MHz.

• Key spec is frequency stability which is expressed in ppmover a fixed temp. range.

- Temperature compensation circuit can be built.- Tuning mechanism can be built.

4/29/2005 94

Sideband Spurs in PLL

• Result from systematic fluctuation of the PLL• Mathematical View

PFD/CP LPF VCO : Kvf (Hz/V)Vc(t)=∆V sin(2πfreft)

- Peak frequency deviation from the carrier frequency : ∆fpeak=Kvf ∆V- Modulation index : β = ∆fpeak /fref- Then, single sideband-to-carrier ratio : 20 log (β/2 ) dBc=> Spurs can be reduced not only by decreasing ∆fpeak, but also by increasing fref.

• Approaches to reduction in spurs :- Choose much narrower loop bandwidth than reference frequency- Use high- order loop filter if possible.- Choose higher reference frequency if possible.- Use dead-zone free phase frequency detector and charge pump.- Minimize mismatch in currents and switching in charge pump.- Use fully differential configuration if possible.- Reduce leakage current.

……

4/29/2005 95

Charge Pump PLL-Based Synthesizer

fo

Id

Id

S1

S2

Up

DnPFD

fr

fv C

VCLPF

1/N

F(s) C1 C

R

Vc

( ) ( )( )F s ss C C s

=+

+ +1

12

1 1τ

τ

where and τ τ1 11

2=+

=CCC C

R RC

• Close-loop transfer function:

( ) ( ) ( )

( ) ( )B s

K KC C

s

s s K KN C C

s K KN C C

d v

d v d v=

++

+ ++

++

12

31

2 21 1 1

1

1

τ

ττ

τ

• Open-loop transfer function:

( ) ( ) ( ) ( )G s H s K K

N C Cs

s sd v=

+⋅

+

+12

21

11

τ

τ

Type 2 third-order PLL

4/29/2005 96

Phase Frequency Detector and Charge Pumpq Purpose: To produce a signal current, proportional to the

difference in phase or frequency between two input signals.

q Design Issues§ - Gain and linearity§ - Dead-zone free PFD/CP§ - Mismatch between sourcing and sinking currents§ - Mismatch in switching time between UP and Down§ - Charge charging§ - Leakage current § - Voltage compliance § - Others

4/29/2005 97

VCOs

• Key Specs- Spectral Purity ( Phase Noise )- Tuning Range- Tuning Linearity- Supply and Substrate Noise Rejection (Integrated VCO)

=> Differential operation is very important

• Typical Approach- Ring Oscillator --- too much phase noise!?- LC Oscillator- Colpitts, Hartley Configurations

• VCO Design & Analysis Models- Feedback Model- Negative Resistance Model

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Frequency Dividers

• Reference Divider

- Max input frequency typically < 50MHz for low power- Programmability to accommodate multiple channel spacings

or reference frequencies - Any programmable ripple or synchronous counter will do.

=> Synchronous counter preferred ( low noise )

• Loop Frequency Divider

- Max input frequency = synthesizer output frequency- Low power & low noise design ( current mode logic)- Use specialized pulse-swallower architecture

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Pulse Swallower Counter

A

• Counter functionality:- asynchronous load of value at Program data when LD is high.- count down to terminal state $0 when LD is low.

• Effective divide ratio N: N = B ( P+1 ) + ( A - B ) P = AP + B

P/P+1 Prescaler

CK MC OUTfin

Program counter

CK LD OUT

Program counter

CK LD OUT

B

fout A - B

B

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Fractional Divider

P/P+1 PrescalerCK OUT

MC

foutfin

DCK

CK

Carry

M bitK

• Mean value of divide ratio :

( ) ( )N

K P K PP K Keff

m

m mm=

⋅ + + − ⋅= + ≤ <

1 22 2

2where 0

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Design Example of PLL

-180

Ph. o

f GH

F (Hz)

GHdB

F (Hz)

0

- 40 dB/dec.

- 20 dB/dec.

- 40 dB/dec.

ωp

φp

• Design loop filter:

( ) ( ) ( )( )

G j H jK K j

C N jd Vω ω

ωτ

ω ωτ

ττ

=− +

+

11

22

1 112

( ) ( ) ( )φ ω ωτ ωτ= + −180 2 1a atan tan

( ) ( )dd

φω

τ

ωτ

τ

ωτ=

+−

+=2

22

1

121 1

0

ωτ τp =11 2

For a given desired loop bandwidth and phase margin

( )( )

τφ φ

ωτ

ω τ ω

ττ

ω τ

ω τ

ττ

τ1 2 2

11 2

12

22

12 1 2

121 1

11=

−= =

+

+= −

=

sec tan , ,p p

p p

d v

p

p

p

C K KN

C C RC

, ,

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Integer-N Frequency Synthesizer

÷ R PFD

N

Fref

fref

θref

LPF

fo/Nθo/N

fo

θo

VCO

f FR

N f Noref

ref= ⋅ = ⋅

Channel Spacing= Reference Freq.

• Design tradeoffs for a given system :

- Phase noise improves with higher PLL bandwidth- Spurious tones improve with lower PLL bandwidth

• Drawback of single loop integer-N frequency synthesizer

- Channel Spacing Divide Ratio In-band Phase Noise

- Channel Spacing Loop Bandwidth Switching Time

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Fractional-N Frequency Synthesizer

PFD LPF VCO

÷N or N+1

m-bit Accum.clock

km bit

fref

overflow

f N k fo m ref= +

⋅2

Nfref

(N+1)fref

(N.F)fref

• Divider modulus is a periodic function of time.

• Reference frequency can be greater than the resolution frequency.

• In-band gain is reduced when reference frequency is increased ==> lower in-band noise.

• Typically, loop bandwidth of PLL can be increased compared to integer-N divide ==> faster lock

• Spurs generated by time-manipulation of divider modulus ==> fractional spurs

B.H. Park, 6/23/99

4/29/2005 104

Fractional Division Example

Consider fractional division which controlled by a 3-bit accumulator with k=1.Reference frequency fref =240 kHz. Synthesize frequency 1200.03 MHz.

Accumulator contents vs. timecycle contents carry divide ratio

1 0 0 1 0 50002 0 1 0 0 50003 0 1 1 0 50004 1 0 0 0 50005 1 0 1 0 50006 1 1 0 0 50007 1 1 1 0 50008 0 0 0 1 50019 0 0 1 0 5000

10 0 1 0 0 5000

average divide ratio over 8 cycles is 5000.125

clock cycles

2π

Radians at VCO ouputor divider input

CENTER FREQ. 30 60 90 120 150f ( kHz )

Spurs at VCO output

B.H. Park, 6/23/99

4/29/2005 105

Phase Estimation by DAC

B.H. Park, 6/23/99

PFD LPF

N/N+1

DAC

m bitaccum.

K

carry

fr fo

fv

fr

fv

Phase error

DAC output

EffectivePd. error

• Cancels fixed spurs by phase interpolation

• Cancellation is limited by analog mismatch in the DAC

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Fractional-N Synthesizer with Σ∆ Modulator

B.H. Park, 6/23/99

• Idea : Eliminate fractional spurs by modulating divide ratio using high-order Σ∆ modulator.

• First-Order Σ∆ Modulator

+ Y(z)

Q(z)

A(z)

D residueR

outputm bit

input k

ck

F(z)+ +

z -1

+

-

2m

z -1

Y(z)

2m

0

+

-

+

+

A(z)

4/29/2005 107

Modeling of First-Order Σ∆ Modulator

B.H. Park, 6/23/99

Y(z) = F(z) + ( 1 - z -1 ) Q(z)

Q(z)

+

z -1

Y(z)F(z)

+

-1- z -1

1 +

+

+

-

+

- Q(z)

+

4/29/2005 108

Cascaded High-Order Σ∆ Modulator

B.H. Park, 6/23/99

Y(z) = F(z) + ( 1 - z -1 )n Qn (z)

First-Order Σ−∆Modulator

f(n)

First-Order Σ−∆Modulator

-q1(n)

First-Order Σ−∆Modulator

-q2(n)

First-Order Σ−∆Modulator-qn-1(n)

yn(n)

y3(n)

y2(n)

y1(n)

Bit

Manipulation

y(n)

This system is always stable because the structure use a noise feed-forward scheme.

4/29/2005 109

B.H. Park, 6/23/99

Third-Order Delta-Sigma Modulator Implementation

{-3, -2, -1, 0, 1, 2, 3, 4}

+z -1

-

{0, 1}

z -1

-

{0, 1}+

z -1

-

{0, 1}+

z -1

- +

z -1z -1

z -1

+ + +

+

+

+

- ++

z -1

{-1, 0, 1, 2}

output

input

4/29/2005 110

B.H. Park, 6/23/99

Fully-Integrated CMOS Fractional-N Synthesizer Example

fo = 1/R ( N + k / 2m ) Fref = ( N +k / 2m ) fref

Freq.

Setting

Data

/ RRef.Input

Fref

fref PFD/CP LPF

VCOMultimodulus

Prescaler Buffer

High-Order Σ∆ Modulatorm bits

k

Output

4/29/2005 111

Swallow counter divider

( ) ( )( )M 1 S P S M

PM S

+ + − =

+

Number of pulsescounted

( )VCO Reff PM S fS 1,2...

= + ⋅

=

M/M+1Prescaler

ProgramCounter

SwallowCounter

/P

/S

Moduluscontrol

fVCOfRef

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Tracking and Acquisition

• Tracking : Extent to which the loop can follow variationin the input frequency

• Acquisition: How the loop goes from unlocked state to completephase lock

4/29/2005 113

Integer-N Architecture

PD LPF VCOfREF fout

÷M

Modulus Selection

- DrawbackReference SpurLoop BandwidthPhase Noise

4/29/2005 114

Pulse Swallow Frequency Divider

÷(N+1)/N ÷Pfin fout

÷S

Modulus Selection

÷MPrescaler

Program Counter

ResetSwallow Counter

Modulus Control

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Fractional-N Synthesizer

PFD LPF VCOfREF fout

PulseRemover

Remove

PFD LPF VCOfREF fout

÷M PulseRemover

Remove

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Dual-Modulus Divider

PFD LPF VCOfREF fout

÷ (N+1)/N

Modulus Control

PD LPF VCOfREF fout

÷M

÷10/11Modulus Control

TREFt

9TREF

4/29/2005 117

Randomization & Noise Shaping

÷ (N+1)/N

To PD From VCO

Randomizer

÷ (N+1)/N

To PD From VCO

Randomizationand

Noise Shaping

4/29/2005 118

Dual-Modulus Divider

÷ (N+1)/N

To PD From VCO

Σ∆Modulator

fout

b(t)

xF(t)

4/29/2005 119

Dual-Loop Synthesizer

PLL1

PLL1

FrequencyAdder

fREF1

fREF2

fc + M fREF2

Channel Selection

4/29/2005 120

Dual-Loop Synthesizer

LPF

Channel Selection

+

×VCO1

÷N

fREF1

fREF2

×

LPF ×VCO2

÷M

×

I

Q

I

Q

fout

SSB Mixer

4/29/2005 121

Dual-Loop Architecture

LPF

Channel Selection

VCO1

÷M

fREF1 ×I

Q

I Q

fout

SSBMixer

PLL2

f2

fREF1 LPF

÷N

×f0

SSBMixer

fREF1 f

4/29/2005 122

Why All Digital PLL?Why All Digital PLL?

*Progress in increasing • Performance• Speed• Reliability

*Progress in reducing • Size• Cost

Improvements in digital designs

* Portability/ Reusability* Programmability* Testability

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Why All Digital PLL?Why All Digital PLL?Solves Problems Related to Analog PLLs(APLL)

• Sensitivity to DC Drifts• Component Saturations• Difficulties building higher order loops• Initial calibration and periodic adjustments

4/29/2005 124

Issues of Issues of ADPLLsADPLLs versus versus APLLsAPLLs• Limitation on operating speed• Chip area

• Power Consumption

• Worse jitter performance due to D/A converter resolution limitation

* Note: The above issues need further exploration[7] as some papers have reported better ADPLL performance.

4/29/2005 125

Example ADPLL Loop FilterExample ADPLL Loop Filter• Up/Down control from the Phase Detector

Controls the Counter value or the Digital Phase difference – Transfer Function ~ 1/sTi

Up/Down Counter

4/29/2005 126

Example Digital VCO (DCO)Example Digital VCO (DCO)• Up/Down Counter Value or the Phase

Error is utilized to create the clock

%N Counter

4/29/2005 127

ResultsResults[2][2]• Shorter Locking in time• Better Jitter Performance• Better Portability (cell-based design)• Reduced circuit complexity• Reduced Design Time• Note: Some other papers have reported

ADPLLs area and power statistics better than APLLs

4/29/2005 128

• No need for off-chip components• Technology portability• Testability• Programmability

• Fast Acquisition Time• Large hold-in range• Large lock-in range• Better phase jitter performance

• Simpler design and faster simulation

• Stability

ECE1352F ECE1352F –– Topic Presentation Topic Presentation -- ADPLLADPLL

Summary- Why are ADPLLsBetter?

4/29/2005 129

Future of ADPLL• Digital IP (Intellectual Property) vendors

are already creating ADPLL products• As technology progress happens skew

problems will require ADPLLs within the design components to synchronize the clock signal between various blocks