PP0104_IFE.pdf

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DEPARTMENT OF SEMICONDUCTOR AND OPTOELECTRONIC DEVICESSemiconductor Device Laboratory

DIGITAL INTEGRATED CIRCUIT CMOS 1

Laboratory Exercise 4

Digital Integrated Circuit CMOS

The aim of the exercise

The aim of this laboratory exercise is to understand basic DC characteristics of theCMOS integrated circuits, as well as their dynamic properties during switching processes.

Bac groundsDesign and operation of the CMOS basic logic element

The advantages such as simpler technology, lower power losses, big input resistance,voltage control, were the main features influencing the development of integrated circuitsthat are based on field effect transistors with insulated gates. !n the CMOS"Complementary Metal Oxide Semiconductors# technology, mainly the enhancement$mode transistors are used as their thresholds voltages assure that the MOS transistorsare turned off at %& gate$source voltage. The basic part of CMOS logic elements is theinverter that is built of two complementary transistors' the one with (n($type channel, andthe other with (p( $type one ")ig. *#.

Fig. 1. The basic scheme of the inverter

)ig. + presents DC characteristics of the inverter shown in )ig. *. hen the inputvoltage e-uals to the supplying voltage " !/ 0 DD#, T * transistor conducts and T + one isbloc1ed. The output voltage e-uals to %& which represents logic state (%(. hen theinput voltage e-uals to %, T * does not conduct, and T + does. The output voltage e-uals tothe supplying voltage, practically, and we have the logic state (*(. The powerconsumption in CMOC circuits is very low. !n a static state, always one of the transistorsis bloc1ed. The consumption increases during switching ")ig. +# and the power lossesincrease proportionally to the increase of wor1ing fre-uency.

Fig. 2. Transient characteristics of the inverter

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/2/D CMOS gateThe scheme of /2/D CMOS gate is introduced in )ig. 3. !t is based on two inverters

T* 4 T + and T 3 $ T 5 . The scheme realises the logic function ABY =

hen the input potentials are low, the upper transistors conduct "with (p( channels#and the output is connected with the supply. hen the input potentials are high, thesetransistors are bloc1ed and the output is connected to the ground.

Fig.3. CMOS NAND gate with two inp ts

The changes of the states are caused by the changes of input voltages and ta1e placewithin the, so called, 6propagation time7. 8ropagation times are defined as the delays ofthe signal change at the gate output resulting from the signal change at the gate input.The idea, how to measure propagation times both low to high $ t p9: and high to low $ t p:9 is illustrated in )ig. 5.

Fig.!. Time p"ot for the inp t an# o tp t vo"tages # ring switching

Tab"e 1. The comparison of the "ogic circ its ma#e in TT$ %transistor&transistor "ogic'an# CMOS techno"ogies.

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Tab"e 2. T(pica" va" es of basic parameters for the CMOS e"ements.

The sco!e of the exerciseDuring the experiment the inverter with two input /2/D gate is examined. The followingmeasurements should be performed

Ta1e the transient characteristic ; 0 f" < # $ with the aid of the oscilloscope andthe (point by point( method.

Ta1e the output characteristic ! < 0 f" < # for the above element. Measure the propagation times for the gate.

ExerciseTransient characteristic $ the oscilloscope method

The diagram of the measurement circuit is introduced in )ig. =. The measurementsshould be conducted for the supplying voltage dd 0 =& and *%& and the generatorfre-uency of about +%%:>. The /2/D gate should be tested for three different ways ofthe input signals connection.

Fig. ). Diagram of meas rement circ it for transient characteristics%the osci""oscope metho#'

Transient characteristic $ (point by point( measurementsThe scheme of the measurement circuit is introduced in )ig. ?. The measurements

should be conducted for the supplying voltage dd 0 =& and *%&. The /2/D gate shouldbe tested for three different ways of the input signals connection.

Fig. *. Diagram of meas rement circ it for transient characteristics%+point b( point, metho#'

Output characteristicsTa1e the output characteristics ! < 0 f" < # for the tested element with (point by point(

method for the supplying voltage DD 0 =& and *%& in the low state ")ig. @# and the highone ")ig. A# on the output. B;M;M ;B that < changes in the range of % DD . The

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scheme of the measurement circuit for low state on the output is introduced in )ig. @ andfor high state on the output in )ig. A.

Fig. -. Meas rement circ it for o tp t characteristic in the "ow state on the o tp t

Fig. . Meas rement circ it for o tp t characteristic in the high state on the o tp t

8ropagation timesMeasure the propagation times for DD 0 =& and *%& "B;M2BE the amplitude on the

generator should be adFusted to DD value and the offset should e-ual to %.= DD .Bemember to switch the offset O/#. The scheme of measurement circuit is introduced in)ig. G. The generator fre-uency should be about =%% 1:>. ;valuate influence of C 9capacitor on propagation times and shape of the output signal.

Fig. / Meas rement circ it for propagation times

"e!ortThe report from the laboratory exercise should contain

2ll transient characteristics obtained with the aid of different methods Output characteristics. Hive the static and small signal impedancies for 3%I DD "for the low state at the

output# and @%I DD "for the high state at the output# 8ropagation times "gather them in the table#. Bemar1s, observations and conclusions.

BeferencesJ*K L. 9isi1, 8odstawy fi>y1i pdpr>ewodni1ow, 89, *GG5 "in polish#J+K L. Eor>ec, Tran>ystory polowe. /T, ars>awa *G@3 "in polish#J3K .&. Leghbroec1, 8rinciples of Semiconductor Devices, +%**,

http ecee.colorado.edu Nbart boo1 boo1 contents.htm Jaccess *%.+%*5K

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PP0104_IFE.pdf