Rahul M Patil M. Tech, VLSI Design p.rahul89@gmail.com+91-7418646428

Objective:

Looking for a challenging role in VLSI domain that will offer the best opportunity for further development of my abilities, skills and knowledge in an established firm with long term career growth possibilities. Strengths include:

• Problem-Solving • Verilog - RTL Design, STA• Research / Report Writing • System Verilog /UVM - Verification• Planning and Organizational Skills • AHB, AHB2APB Bridge, MIPI-DSI• Meeting Deadlines • Xilinx, Questasim, Riviera-pro, Spyglass(Lint)

Experience:

Intern at Maven Silicon, BangaloreResponsibility: Verification of AMBA-AHB2APB Bridge using UVM Methodology

Intern at Larsen and Toubro, PES, Chennai (15 months) Responsibility:

Designed AMBA-AHB Slave as a part of M. Tech Project. Owned Lane_Merger and Depacketiser modules of MIPI-DSI Interface.

Projects:

1. AMBA-AHB2APB Bridge Description: The AHB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. The read and write transfers on the AHB are converted into equivalent transfers on APB.

Responsibility: Verification of the RTL using SV/UVM

HVL : System Verilog

HVL Methodology : UVM

2. MIPI-DSI Receiver: (At L&T) Description: DSI defines a high speed serial interface between a peripheral, such as an On - Panel Display Controller, and a host processor in a mobile device. DSI receiver collects the serial data from DSI Transmitter and controls the On-Panel Display Controller.

Responsibility: Lane_Merger : Collects data bits from the PHY lanes, structures into word and sends to de-packetizer. Depacketiser : Decodes the type of packet, checks for ECC and CRC.

HDL: VerilogSimulation Environment : QuestasimHDL Checker : Spyglass

3. AMBA-AHB Interface: [M.Tech Final Semester Project] Description: AHB is a new generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs. AMBA AHB is a new level of bus which sits above the APB and implements the features required for high-performance, high clock frequency.

Design: Involved in designing Slave blocks of AMBA-AHB Interface. Used in USB and xHCI protocols.Hardware Description Language: Verilog

Education:

M.Tech (VLSI Design Engineering), at SRM University, Kattangulathur (2012 - 2014) with First Class

BE (Electronics & Communication Engineering), at Asan Memorial College of Engineering and Technology, Keerapakkam (2007 - 2011) - First Class

HSC, at SDA Mat. Hr. Sec. School, Chengalpattu, (2006 - 2007) - 83 % SSLC, at Little Jacky Matriculation Hr. Sec. School, Chengalpattu, (2004-2005) 79.40%