Schematics & Layout with Cadence tools - TAU · Schematics & Layout with Cadence tools ... It creates the VLSI_lab directory and cd to it ... The cell is the basic design entity

1 אבי אפרתי VLSI -מעבדה ל

Schematics & Layout with

Cadence tools

בניין כיתות 220חדר , אפרתיאבי

בניין כיתות 208חדר ,VLSI Lab

[email protected]


מבוא

עקרונות , השקפים מתמקדים בכלים שבהם נשתמש

שחם' פרופושיטות התכנון ניתנות בהרצאה של

אני מניח ידע בסיסי ב-Linux ובכל מקרה יש מבוא ל-

Linux/UNIX באתר המעבדה

באתר המעבדה ניתן למצוא שקפים אלו וחומר נוסף

VLSI-ל

http://www.eng.tau.ac.il/research/laboratories/VLSI_lab/

http://www.eng.tau.ac.il/research/laboratories/VLSI_lab/


VLSI Circuit and Layout Design

Design and size circuit

Virtuoso XL Schematics

Simulate for speed/power/noise

ADE XL (Analog Design Environment)

Includes Spectre/SPICE

Design Layout

Virtuoso XL Layout

Check rules and re-simulate

Assura & QRC, ADE XL

Fabricate chip – not covered here


You’ll learn to create those…


First access and Login


Login to VLSI Lab computer

Computer name is micron.eng.tau.ac.il, also

micron2.eng.tau.ac.il

From any PC in computer farm:

Click on puTTY and login in text mode to micron

computer with your username and password

Within micron vncserver is activated automatically

– You get a VNC number, e.g. :17

– Close puTTY , you don’t need it any more in campus

Activate VNC with the :number you got

– example micron.eng.tau.ac.il:17

– Enter your password when asked


Login thru VNC

Enter your VNC number

VNC opens new form

Enter your password

Press Connect


First time setup, in VNC screen By default you login to your $HOME directory

ONLY FIRST TIME run the script

/home/cadence/sourcefiles/runmeonceVLSI_lab

It creates the VLSI_lab directory and cd to it

You may now activate virtuoso, type virtuoso & at prompt


Regular login campus

Start VNC to micron or micron2

use your VNC number, e.g. micron.eng.tau.ac.il:4

Within VNC screen:

The first xterm appears, click in it and work in text

mode

cd VLSI_lab change directory to VLSI_lab

virtuoso & activate virtuoso

AT ANY TIME you may create additional xterm’s

by mouse left-click and chose xterm from menu


Regular login from home Login to gate.tau.ac.il thru puTTY

When working from home DON’T close puTTY

Start VNC to localhost

use your VNC number preceeded by 59, e.g.

localhost:5904

Within VNC screen:

The first xterm appears, click in it and work in text

mode

cd VLSI_lab change directory to VLSI_lab

virtuoso & activate virtuoso

AT ANY TIME you may create additional xterm’s by

mouse left-click and chose xterm from menu

Working from home is not guaranteed


Some basic problems

If you registered late your account on micron

may not be active yet, send me email

Your account password is the same as your

regular university account

Your home directory is specific to this course, not

the default university home

VNC requires a password

you may define it same or different from university

password

You can reset it by yourself, no need for my help


Creating a Design


Creating Library and Cellview

The cell is the basic design entity

Schematics or Layout are Cellviews

Cellviews reside in Libraries

For this class:

We create a library called lab_090 under

directory VLSI_lab

Use the templates in gpdk090 library

Open either schematic or layout

cellviews in library lab_090


Opening new Library


Opening new Schematic


Opening new Layout


Add transistor to schematic

Add instance button


Add Instance Details In Library Browser choose the right component, symbol view

Transistors from gpdk090, nmos1v and pmos1v

Sources, GND, VDD from analogLib


The transistor form

Library, cell, view

Channel length

default 100nm

Width

Based on exercise

request or your design

decisions

Number of fingers

Very wide transistors are

usually split to “fingers”


Creating an inverter schematic

Place two transistors

NMOS and PMOS and

give them sizes

At any time can move

transistor and modify

properties

click on transistor to

select

click to re-open form

and change properties


Add wires and pins

Use buttons for:

narrow wires

in/out/inout pins

Define global pins

connected by name

additional properties

not added to symbol

view of cell


Create symbol view

Create Cellview From Cellview

Fill form and press OK


Symbol view

You may edit symbol shape, terminal

names and more…


Add Power and input sources

Add instance:

from analogLib

from your own library

connect to wires

Modify properties

Set power source voltage

set input source voltages, type, slope

many built-in input types – pulse, ramp,

exponential, sine…


Place & connect inverters and sources


Simulation with ADE

Chose

simulation

mode (tran, DC)

and signals to

plot

Double-click on test

to open Test Editor

start sim


Results window

waves

post-processing

tools


Layout representation

Layout is a 2-D representation of devices

and interconnect

Layout is the input to Masks generation

Masks are used for photolithography in

the fabrication flow – you’ll learn this in

lectures

Now we’ll focus on layout representation

of devices, wires and vias


CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Create Layout from schematic

Open Schematic of existing cell

Start Layout of new cell


Auto-generation of devices

Connectivity

Generate…

All From Source…

Form appears

Add details

Press OK and you get

– Transistors

– Terminals

– Underlying connectivity

At any time

click(select) info

nmos pmos

pins


Place and align the 2 transistors

N-well

Thin oxide

(for actual device

and diffusion)

P-implant

N-implant

poly contacts


Connect the transistor gates

Join the two gate poly

Add wider poly and

contact

This is the inverter

input


Add Well tap and substrate tap

N-well tap including:

• thin oxide marking

• N-implant

• As many contacts as possible

Substrate(P) tap including:

• thin oxide marking

• P-implant

• As many contacts as possible


Add metal1 for power and output

gates

connection to

metal1 port

VDD connection

to N-well tap and

diffusion

VDD connection

to N-well tap and

diffusion

output diffusions

connection to

metal1 port


1-bit static Full-adder cell

from gsclib090 cell library


DRC-הגדרת מושגים ב

רוחב ,Length=אורך =Width במשמעות

הרגילה

מרווח=Spacing - distance from the

outside of the edge of a shape to the

outside of the edge of another shape.


(המשך) DRC-הגדרת מושגים ב

Enclosure - distance from the=כיסוי

inside of the edge of a shape to the

outside of the edge of another shape.



חפיפה=Overlap - distance from the

inside of the edge of a shape to the

inside of the edge of another shape.



נגיעה=Butting - outside of the edge of a

shape touching the outside of the edge

of another shape.


דוגמאות 90בתהליךnm נתוני המתכות הם, שלנו:

M1 minW = 0.12μ, maxW = 12μ, minSpacing = 0.12μ

M2-M7 minW = 0.14μ, maxW = 12μ, minSpacing = 0.14μ

M8-M9 minW = 0.44μ, maxW = 12μ, minSpacing = 0.4μ

חוקיPoly

Documents

Schematics & Layout with Cadence tools - TAU · Schematics & Layout with Cadence tools ... It creates the VLSI_lab directory and cd to it ... The cell is the basic design entity