An Integrated L-Band Transceiver in 0.35um SiGe for Radar Applications

Song Ye and Jun Fan

Chengdu University of Information Technology, 24Xuefu Road, Chengdu, 610225 China.

ABSTRACT

An integrated high linear L-band transceiver with an on-chip fault detector is demonstrated. The transmitter and receiver exhibit an output 1dB compression point (OP1dB) of 12dBm and 15dBm respectively under 3.3V operation voltage. The transceiver has high linearity and low power consumption. The transceiver works at a time division mode by adopting an on-chip switch for radar applications. The measurement result shows an isolation of 64dBc between the transmitter and receiver. The transceiver is fabricated in a standard 0.35 um SiGe technology with a chip area of 2.5 mm × 3.3 mm, including contact pads. Keywords: Radar, Transmitter, Receiver, T/R module, SiGe, RFIC.

1. INTRODUCTION Phased array radars are increasingly being favored over conventional mechanically scanned

systems. Such a system consists of several thousands of Transmit/Receive (T/R) module [2]. Therefore, it is of importance to reduce the costs of the T/R module. The cost of the T/R module is mainly determined by the cost of the Radio Frequency (RF) components, which are mostly composed of RF integrated circuits (RFICs). To decrease the cost of the T/R module, it is important to reduce the total number of RFICs in each module and to select a low cost technology. The number of RFICs needed for one T/R module can be drastically reduced by combining many functions such as amplification, switching, attenuation, amplification onto a single multi-function RFIC. SiGe technology is a very attractive solution for the multi-function RFICs in terms of cost [3]. This technology is not capable to outperform the GaAs technology in terms of high frequency performance, but with higher integration. Therefore SiGe is a promising and feasible candidate for cost reduction.

In this paper, a RFIC for use in phased array radar has been designed, fabricated, and measured based on a 0.35 um SiGe BiCMOS technology.

2. TRANSCEIVER ARCHITECTURE To meet low noise figure and the high linearity requirements, the chip includes two on-chip LNA

and a large range VGA. The receiver adopts two off-chip filter to reject the image signal and suppress the out band noise.It also incorporates a low-spurious output amplifier (PA).

Fig.1 shows the architecture of the L-Band transceiver. In receive mode the signal path is from the RX_IN port through LNA1, RF bandpass filer (RF_BPF), Mixer1, IF bandpass filter, VGA and RX_PA before going to the ADC. In transmit mode of operation, the signal path is TX_IN port through Mixer2, RF_Amp, followed by the off-chip bandpass filter (RF_BPF1), amplifier TX_PA

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before going through the off-chip power amplifier. The LO to the transmitter and the receiver is through the T/R switch which is toggled through a control logic. The transmitter and the receiver are working at the frequency band of 1300~1400MHz and 1250~1500MHz respectively.

TX_OUT

Mixer1 VGALNA2LNA1

RX_IN

RF_BPF IF_BPF

Mixer2

RF_Amp1

RX_PA

RX_OUT

TX_IN

TX_PA

PD

Fault Detector

RF_BPF1

SW1

LO

T/R_SWBandgap

Figure 1. Transceiver architecture

3. IMPLEMENTATION

3.1 Receiver Section Fig.2 shows the architecture of the LNA1. The LNA1 with a CE-CB configuration provides

20dB gain and amplifies the RF signal which comes from the antenna and then driver it to the off chip filter. It has high gain and low noise figure.

Figure 2. LNA1 schematic

The second LNA stage is shown as Fig.3, using a single-to-differential architecture for the following reason. The mixer should be a double-balanced mixer in order to minimize the LO feed-through that will cause an large dc offset. LNA2 comprises a variable gain LNA and a 4-bit attenuator to achieve wide gain range from 12dB to -30dB. The variable gain LNA provides three gain modes with low noise figure and high linearity to increase the sensitivity of the receiver and prevent interference from the undesired adjacent-channel. The 4-bit attenuator offers high, well

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bdO(

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controlled attenuation range while maintains good thermal stability and high power handling capability. A gain control logic circuit is introduced to ensure each of the eight gain step working normally.

Variable gain LNA

4-bit attenuator

Gain Control

Gain Control

VDD

S1

S2 S3

Figure 3. LNA2 core circuits

The receiving mixer (Mixer1) illustrated in Fig.4 down-converts the RF signal at 1250MHz~1500MHz band to an IF of 200MHz. It has a gain of 9.4dB and a noise figure of 8.8dB.

Vlo

VB2

R C R C

VDDa

on chip gnd on chip gnd

INA INB

output

M1 M2

M3 M4

Q1 Q2 Q3 Q4

M5 M6

VB1

Figure 4. Mixer1 schematic and PA core circuit

The IF amplifier RX_PA amplifies the signal of 200MHz to drive the external ADC. It has a voltage gain of 21dB and an output 1-dB compression point of 15dBm. The core circuit of the RX_PA is illustrated in Fig.4. 3.2 Measurement Results

The chip was fabricated in a standard 0.35um SiGe process and packaged in a CQFP64. The chip layout is shown in Fig.5. The measurement results are shown through Fig.6 to Fig.8. The chip performance is summarized in the table followed.

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Figure 5. Chip Layout

Figure 6. Rx Gain vs. RF Frequency and Rx NF vs. RF Frequency

Figure 7. Rx OP1dB vs. RF Frequency and Tx Gain vs. RF Frequency

Figure 8. TX_PA output impedance and Rx input impedance

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Table 1. Performance Summary

PARAMTERS CONDITIONS RESULTS UNITS

RECEIVER SECTION

RF Frequency Range 1.25 ~ 1.5 GHz

Total Power Gain 30 dB

RF Gain Control Range 6dB per one step 42 dB

IF Gain Control Range 1dB per one step 16 dB

Noise Figure 11.5 dB

Output P-1dB Power Gain =30dB 15.2 dBm

Input P-1dB Power Gain =30dB -13 dBm

TRANSMIT SECTION

RF Frequency Range 1.3 ~ 1.4 GHz

Total Power Gain 13 dB

Output P-1dB Power Gain =30dB, 12.5 dBm

4. CONCLUSION An integrated transmitter/receiver has been developed using a standard 0.35um SiGe process and

demonstrates 64dBc Tx/Rx isolation with a die area of 3.3mm x 2.5mm. The measured OP1dB of Tx and Rx are 12dBm and 15dBm respectively. The fault detector outputs a sign when the power level detected is outside the threshold range of 4~8dBm. The switching time to -20dBm output power level is 39ns. The chip can be used in L-Band radar T/Rs, or as an IF channel in C-, X-Band phased array radars. To suppress the noise further, an off-chip LNA in front of the chip may be required.

REFERENCES

[1] H. Ma, S. J. Fang, F. Lin, and H. Nakamura, "Novel Active Differential Phase Splitters in RFIC for Wireless Applications". IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 46, NO. 12(1998).

[2] Schuh, H. Sledzik, R. Reber, K. Widmer, A. Fleckenstein, B. Schweizer and M. Oppermann. T/R-Module Technologies Today and Future Trends. Proc. of the 40th European Microwave Conference. Paris, pp. 1540-1543(2010).

[3] Jeong and I. Yom. SiGe BiCMOS Chip sets for use in an X-band Multi-function Chip. 2010 Second International Conference on Advances in Satellite and Space Communications. pp. 25-30.(2012).

[4] S. Wang, K. Tsai, K. Huang, S. Li, H. Wu, and C. C. Tzuang. Design of X-Band RF CMOS Transceiver for FMCW Monopulse Radar. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, JANUARY 2009, VOL. 57, NO. 1.

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