tanner 2nd Sem Final

8/7/2019 tanner 2nd Sem Final

http://slidepdf.com/reader/full/tanner-2nd-sem-final 1/10

Prob : 1Design a NMOS transistor with it's drain connected to voltage source VDD in stepsof 0.1 volt from 0 volt to 5 volt for each value of gate to source voltage VGS andvary VGS from 0 volt to 5 volt in steps of 1 volt. Vary the gate to source voltageVDS and vary VDS from 0 volt to 5 volt in steps of 1 volt.

Circuit Diagram:

Circuit Diagram

NETLIST for the above Circuit* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Mar 12, 2006 at 07:18:05

* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0".include "C:\Program Files\Tanner EDA\Demo\T-+Spice\models\ml1_typ.md"* Main circuit: Module0M1 N7 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv2 N5 Gnd 5.0v3 N7 Gnd 5.0.dc v3 0 5 .01 v2 0 5 1.print i(m1,n7)*End of main circuit: Module0



* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Mar 12, 2006 at 07:18:05

* Waveform probing commands.probe.options probefilename="File0.dat"

+ probesdbfile="File0.sdb"+ probetopmodule="Module0".include "C:\Program Files\Tanner EDA\Demo\T-+Spice\models\ml1_typ.md"* Main circuit: Module0M1 N7 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv2 N5 Gnd 5.0v3 N7 Gnd 5.0.dc v2 0 5 .01 v3 0 5 1.print i(m1,n7)* End of main circuit: Module0

Prob: 2In figure 1 plot the drain current ID as a function of bulk voltage VBB as VBBis varied from -5 volts to 0 volts. Ashume default level 1 MOS model parameter for TSPICE.

ID

+(1.2 V) 2 V

VBB _



Circuit Diagram in Tanner Spice

* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Mar 12, 2006 at 08:54:14

* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0".include "C:\Program Files\Tanner EDA\Demo\T-+Spice\models\ml1_typ.md"* Main circuit: Module0M1 N4 N3 Gnd N2 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv2 N3 Gnd 1.2v3 N2 Gnd 5.0v4 N4 Gnd 2.0.dc v3 0 -5 .01.print i(m1,n4)*End of main circuit: Module0

The output waveform



Prob :3In Fig 2. VDD! = +5 V and VDD2 = +6 V. Plot IOUT as a function of Iin. Theaspect ratio of each transistor is 5 um/5um. Repeate the process with VDD@ = +5V. Also plot Vout1 and Vout2 as a function of Iout. Use default level 1 MOS modelparameters for SPICE.

Circuit Diagram in Tanner Spice

NETLIST for the above Circuit* SPICE netlist written by S-Edit Win32 6.00* Written on Mar 9, 2006 at 19:15:15* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0"* Main circuit: Module0

M1 N1 N3 N9 Gnd NMOS L=5u W=5u AD=66p PD=24u AS=66p PS=24uM2 N9 N13 Gnd Gnd NMOS L=5u W=5u AD=66p PD=24u AS=66p PS=24uM3 N13 N13 Gnd Gnd NMOS L=5u W=5u AD=66p PD=24u AS=66p PS=24uM4 N3 N3 N13 Gnd NMOS L=5u W=5u AD=66p PD=24u AS=66p PS=24uv5 N3 Gnd 5.0v6 N1 Gnd 6.0.include "C:\Program Files\Tanner EDA\Demo\T-+Spice\models\ml1_typ.md".dc v5 0 5 .01.print i(m4,n3) i(m1,n1)*End of main circuit: Module0

•



Prob:4Design a resistive load nMOS inverter of which the load resistance is 5 KOHM.Observe it's voltage transfer charasteristics. Apply a bit stream of 10101101 to theinput where each bit has a duration of 20 nSec. A rise time and fall time of 0.01nSec. Observe the transient output response. Repeat the process for an activePMOS load inverter, a current source load inverter and a push pull inverter.Compare and comment on your observations with different inverters. Asshume thatthe on voltage is +5 volt and off voltage is 0 volt.

Circuit Diagram for 3 Different MOSFET Digital Inverter Circuit

NETLIST for the above 3 different Inverter Circuit

* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Apr 17, 2006 at 22:51:22* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0".include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.md"* Main circuit: Module0M1 N14 N2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM2 N11 N2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM3 N21 N2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M4 N21 N2 N13 N13 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM5 N11 N11 N13 N13 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uR6 N13 N14 5k TC=0.0, 0.0v7 N2 Gnd bit({0100101111} pw=20n on=5.0 off=0.0 rt=.01n ft=.01ndelay=0 lt=10n ht=10n)v8 N13 Gnd 5.0.tran .01n 200n 0*.plot v(n14) v(n11) v(n21) v(n2).plot v(n2) i(m1,n14) i(m2,n11) i(m3,n21)*End of main circuit: Module0



The Output current with respect to input voltage pulse

In the above output with respect to the pulse (bottommost) it is clear that theresistive and current source inverter circuit consumes current in on state, whereasthe push pull circuit does not consumes any current in no load state. The no loadcurrent drawn in the resistive inverter circuit is less(0.95 mA peak) than the

current source inverter circuit (6.3 mA peak). So, it can be concluded that the pushpull inverter is the best among all.



Prob:5Using CMOS logic design a CMOS 2 input (1) NAND gate (2) NOR Gate (3)XOR Gate. In each case Name the inputs as A and B. Apply a bit stream of A=10101101 and B=10110001 and observe the output of the gate. Take theduration of each bit as 20 nano second. Take rise time and fall time as 0.1 nanosecond.

NAND Circuit Diagram NOR Circuit Diagram

NETLIST for above NAND Circuit

* SPICE netlist written by S-Edit Win32 Demo 9.12

* Written on Apr 18, 2006 at 04:25:43

* Waveform probing commands.probe.options probefilename="File0.dat"+ probesdbfile="File0.sdb"+ probetopmodule="Module0"

* Main circuit: Module0M1 N1 N3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM2 N7 N5 N1 N1 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM3 N7 N3 N2 N2 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM4 N7 N5 N2 N2 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv5 N5 Gnd bit({10101101} pw=20n on=5.0 off=0.0 rt=0n ft=0n

delay=0 lt=10n ht=10n)v6 N3 Gnd bit({10110001} pw=20n on=5.0 off=0.0 rt=0n ft=0ndelay=0 lt=10n ht=10n)v7 N2 Gnd 5.0.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.md".tran .01n 200n.print v(n5) v(n3) v(n7)* End of main circuit: Module0



NAND Output Waveform

NETLIST for above NOR Circuit

* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Apr 18, 2006 at 03:03:56


* Main circuit: Module0M1 N7 N2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM2 N7 N3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM3 N1 N3 N5 N1 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM4 N7 N2 N1 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uv5 N3 Gnd bit({10101101} pw=20n on=5.0 off=0.0 rt=0n ft=0n delay=0lt=10n ht=10n)

v6 N2 Gnd bit({10110001} pw=20n on=5.0 off=0.0 rt=0n ft=0n delay=0lt=10n ht=10n)v7 N5 Gnd 5.0.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.md".tran .01n 200n.print v(n7) v(n3) v(n2)* End of main circuit: Module0



NOR Output Waveform(Bottom) with two input sequence(middle & Top)

XOR Circuit Diagram in Tanner Spice



NETLIST for above XOR Circuit* SPICE netlist written by S-Edit Win32 Demo 9.12* Written on Apr 18, 2006 at 03:51:56


* Main circuit: Module0M1 N9 N6 N12 N12 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM2 N12 N1 N2 N2 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM3 N16 N1 N12 N12 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM4 N2 N6 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM5 N9 N1 N7 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM6 N17 N1 N12 N12 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM7 N16 N6 N7 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24uM8 Gnd N6 N17 N17 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

v9 N1 Gnd bit({10101101} pw=20n on=5.0 off=0.0 rt=0n ft=0ndelay=0 lt=10n ht=10n)v10 N6 Gnd bit({10110001} pw=20n on=5.0 off=0.0 rt=0n ft=0ndelay=0 lt=10n ht=10n)v11 N7 Gnd 5.0.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.md".tran .1n 200n.print v(n1) v(n6) v(n12)*End of main circuit: Module0

XOR Output Waveform (Top) with two input sequence(Medium & Bottom)

Documents

tanner 2nd Sem Final