THIẾT KẾ VI MẠCH TƯƠNG TỰ - hcmut.edu.vnhoangtrang/lecture note/AnalogICdesign... · THIẾT KẾ VI MẠCH TƯƠNG TỰ CHƯƠNG 2: CMOS Technology Hoàng Trang -bộmônKỹThuật

THIẾT KẾ VI MẠCH TƯƠNG TỰCHƯƠNG 2: CMOS Technology

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử

TP.Hồ Chí Minh 12/2011

Hoàng Trang bộ môn Kỹ Thuật Điện Tử[email protected]

11

1. Overview

- IC technology

CMOS BJT- CMOS vs BJT

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/20112

What is Integrated Circuit Technology?


How Does IC Technology Influence Analog IC Design?

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 4

Classification of Silicon Technology


Why CMOS Technology?


Components of a Modern CMOS Technology


CMOS Components – Transistors


2.BASIC IC PROCESS TECHNOLOGYFUNDAMENTAL IC PROCESSING STEPS

100‐200‐300‐450mm


Oxidation


Diffusion


Ion implantation


Deposition


Etching


Shallow Trench Isolation


Epitaxial


Photolithography


Illustration of Photolithography ‐ Exposure


Illustration of Photolithography –Positive Photoresist


3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS

Major Fabrication Steps for a DSM CMOS Process1 ) p and n wells1.) p and n wells2.) Shallow trench isolation3.) Threshold shift4.) Thin oxide and gate polysilicon5.) Lightly doped drains and sources6.) Sidewall spacer) p7.) Heavily doped drains and sources8.) Siliciding (Salicide and Polycide)9 ) Bottom metal tungsten plugs and oxide9.) Bottom metal, tungsten plugs, and oxide10.) Higher level metals, tungsten plugs/vias, and oxide11.) Top level metal, vias and protective oxide



Step 1 – Starting MaterialThe substrate should be highly doped to act like a good conductor



Step 2 - n and p wellsThese are the areas where the transistors will be fabricated -NMOS in the p well and PMOS in the n wellNMOS in the p-well and PMOS in the n-well.Done by implantation followed by a deep diffusion.



Step 3 – Shallow Trench IsolationThe shallow trench isolation (STI) electrically isolates one region/transistor from anotherregion/transistor from another.



Step 4 – Threshold Shift and Anti-Punch Through Implants- The natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An p-implant is used to make the NMOS harder to invert and the PMOS p peasier resulting in threshold voltages balanced around zero volts.- Also an implant can be applied to create a higher-doped region beneath the channels to prevent punch-through from the drain depletion region extending to source depletion region.



Step 5 – Thin Oxide and Polysilicon GatesA thin oxide is deposited followed by polysilicon. These layers are removed where they are not wantedremoved where they are not wanted.



Step 6 – Lightly Doped Drains and SourcesA lightly-doped implant is used to create a lightly-doped source and drain next to the channel of the MOSFETsand drain next to the channel of the MOSFETs.



Step 7 – Sidewall Spacers A layer of dielectric is deposited on the surface and removed in such a way as to leave “sidewall spacers” next to the thin oxidesuch a way as to leave sidewall spacers next to the thin-oxide-polysilicon-polycide sandwich. These sidewall spacers will prevent the part of the source and drain next to the channel from becoming heavily doped.



Step 8–Implantation of the Heavily Doped Sources and DrainsNote that not only does this step provide the completed sources and drains but allows for ohmic contact into the wells andand drains but allows for ohmic contact into the wells and substrate.



Step 9 – SilicidingSiliciding and polyciding is used to reduce interconnect resistivity by placing a lowresistance silicide such as TiSi2 WSi2 TaSi2 etcby placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions.



Step 10 – Intermediate Oxide LayerAn oxide layer is used to cover the transistors and to planarize (or polish >CMP) the surfacepolish->CMP) the surface.



Step 11- First-Level MetalTungsten plugs are built through the lower intermediate oxide layer to provide contact between the devices wells and substratelayer to provide contact between the devices, wells and substrate to the first-level metal.



Step 12 – Second-Level MetalThe previous step is repeated to from the second-level metal.



Completed Fabrication After multiple levels of metal are applied, the fabrication is completed with a thicker top-level metal and a protective layer to hermetically seal the circuit from the environment. Note that metal is used for the upper level metal vias The chip is electrically connected byNote that metal is used for the upper level metal vias. The chip is electrically connected byremoving the protective layer over large bonding pads.



Scanning Electron Microscope (SEM) of a MOSFET cross-section



SEM: Showing Metal Levels and Interconnect



DSM CMOS Technology Summary


4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS

What is UDSM CMOS Technology?Vindication of Moore’s Law“The minimum feature size decreases by approximately 0.7 every two years.”y pp y y y

Minimum feature size ~25 nanometers (2012)2006 state of the art:- 65 nm drawn length - 35 nm transistor gate length- 1.2 nm transistor gate oxide - 8 layers of copper interconnect



Example: about 65 Nanometer CMOS Technology



UDSM Metal and Interconnects



Advantages of UDSM CMOS Technology:



Disadvantages of UDSM CMOS Technology (for Analog)?• Reduction in power supply resulting in reduced headroom• Gate leakage currents

R d d ll i l i t i i i• Reduced small-signal intrinsic gains• Increased nonlinearity (IIP3)• Noise and matching?

Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:


Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, 2005


the Gate Leakage Problem?



Gate Leakage and fgate



UDSM CMOS Technology Summary

• Increased transconductance and frequency capabilityL l lt• Low power supply voltages

• Reduced parasitics• Gate leakage causes challenges for analog applications of g g gUDSM technology• Other . . . ?


5. PN JUNCTIONS in CMOS

How are PN Junctions used in CMOS?• PN junctions are used to electrically isolate one semiconductor region from anotheranother• PN diodes• Creation of the thermal voltage for bandgap purposes• Depletion capacitors – voltage variable capacitors (varactors)

Components of a PN junction:1.) p-doped semiconductor – a semiconductor having atoms containing a lack of electrons (acceptors). The concentration of acceptors is NA in atoms per cubic centimeter.2.) n-doped semiconductor – a semiconductor having atoms containing an excess of electrons (donors) The concentration of these atoms is ND in atomsexcess of electrons (donors). The concentration of these atoms is ND in atoms per cubic centimeter.


6. MOS TRANSISTORPHYSICAL ASPECTS OF MOS TRANSISTORS

Physical Structure of MOS Transistors in an n-well Technology

Width (W) of the MOSFET = Width of the source/drain diffusionLength (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusionsNote: the MOSFET is isolated from the well/substrate by reverse biasing the resulting


PN junction


Enhancement MOSFETsThe channel between the source and drain of an enhancement MOSFET is formed when the proper potential is applied to the gate of the MOSFET. This potential inverts th t i l i di t l b l th t t th t f i it th dthe material immediately below the gate to the same type of impurity as the source and drain forming the channel.



Depletion Mode MOSFETThe channel is diffused into the substrate so that a channel exists between the source and drain with no external gate potential.

The threshold voltage for a depletion mode NMOS transistor will be negative (a negative gate potential is necessary to attract enough holes underneath the gate to


negative gate potential is necessary to attract enough holes underneath the gate to cause this region to invert to p-type material).


W k I i O iWeak Inversion Operation


6. MOS TRANSISTORLAYOUT OF MOS TRANSISTORS

Layout of a Single MOS transistor

Comments:• Make sure to contact the source and drain with multiple contacts to evenly distribute the current flow under the gate


the current flow under the gate.• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.


Geometric Effects

Orientation:Devices oriented in the same direction match more precisely than those oriented in other directions



Diffusion and Etch Effects

• Poly etch rate variation – use dummy elements to prevent etch rate differences.• Do not put contacts on top of the gate for matched transistors.• Be careful of diffusion interactions for diffusions near the channel of the MOSFET



Thermal and Stress Effects• Oxide gradients – use common centroid geometry layout• Stress gradients – use proper location and common centroid geometry layout• Thermal gradients – keep transistors well away from power devices and use common centroid geometry layout with interdigitated transistors

Examples of Common Centroid Interdigitated transistor layout:Examples of Common Centroid Interdigitated transistor layout:



MOS Transistor LayoutPhotolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI comes from optical interactions between pthe UV light and the masks.

Examples of the layout of matched MOS transistors:1 E l f i t d h t lith hi i i1. Examples of mirror symmetry and photolithographic invariance.



Examples of the layout of matched MOS transistors (cont)2. Two transistors sharing a common source and laid out to

hi b th h t lith hi i i d t idachieve both photolithographic invariance and common centroid.



Examples of the layout of matched MOS transistors (cont)3. Compact layout of the previous example.


7. CAPACITORS in CMOS technology

Types of Capacitors for CMOS Technology


7. CAPACITORS in CMOS technology

Characterization of Capacitors


7. CAPACITORS in CMOS technologyPN JUNCTION CAPACITORS

PN Junction Capacitors in a Well


7. CAPACITORS in CMOS technologyPN JUNCTION CAPACITORS

PN Junction Capacitors in a Well


7. CAPACITORS in CMOS technologyMOSFET GATE CAPACITORS

MOSFET Gate Capacitor StructureThe MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulkthe capacitor and some combination of the source, drain, and bulk as the other terminal.In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending ongate capacitance is really two capacitors in series depending on the condition of the channel.


7. CAPACITORS in CMOS technologyMOSFET GATE CAPACITORS

MOSFET Gate Capacitor StructureThe MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulkthe capacitor and some combination of the source, drain, and bulk as the other terminal.In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending ongate capacitance is really two capacitors in series depending on the condition of the channel.


Reference

Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”, 2nd Edition, Oxford Univeristy Press, 2002.g , , y ,


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THIẾT KẾ VI MẠCH TƯƠNG TỰ - hcmut.edu.vnhoangtrang/lecture note/AnalogICdesign... · THIẾT KẾ VI MẠCH TƯƠNG TỰ CHƯƠNG 2: CMOS Technology Hoàng Trang -bộmônKỹThuật