TKT-1212 Digitaalijärjestelmien toteutus · 2009-04-06 · TKT-1212 Digitaalijärjestelmien toteutus. Acknowledgements 2 Ari Kulmala, ... N-type cmos transistor channel 4 Ari Kulmala,

Lecture 13 - System design trends & challenges

Ari Kulmala, TUT, 2009

TKT-1212 Digitaalijärjestelmien toteutus

Acknowledgements


The International Technology Roadmap for Semiconductors

M. Keating and P. Bricaud, “Reuse Methodology Manual for System-on-a-Chip Designs, 3rd Edition”

OutlineChallenges in digital systems

Hierarchical design in HDL

3 Ari Kulmala, TUT, 2008

Sidenote: technology nodeWe speak about 90nm, 65 nm etc. What exactly that means?

It depends For MPU/ASIC it is typically gate-length isolated feature size

Or channel length

DRAM half pitch is roughly the minimum distance between two wires

Gate

substratesource drain

Note that there is some tolerance between manufacturers, e.g. 90nm process might actually be like 85-100 nm

N-type cmos transistor

channel


Challenges in digital system designHigh-level challenges, not taking into account physical and manufacturing issues

1. Design complexity

2. Power consumption

3. Verification

4. (Chip area & performance)


Design complexity85% of IC projects miss their original schedules

Average slip is 44%

http://eetimes.eu/semi/showArticle.jhtml?articleID=204702114&printable=true

One problem is that re-usable components are not, after all, easy to integrate


Digital systems challenges#1 - Increased complexity

TI OMAP3430


Parallel computingA few cores on desktop processorsSeveral cores on embedded devicesTens of cores in research embedded systems

E.g. 35 processors, 23 other ip components, 3 FPGA boards usedHow to write software?

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System-on-chip (SoC)Purely:

Integrating whole system on a single chipChip complexity increasesProcessors, memories, hardware accelerators, I/Os, analog RF, …

LooselyA highly complex chip full of digital logicInterfaces to external memories, analog devices, etc

Two main types: power-efficient (PE) and high-performance (HP, later a.k.a. CS)

Target is to reduce cost1990-1992 mobile phones included 15 ICs and 800 other discrete components and in 2002 3-4 ICs and 200 discrete components

Cellular phones as embedded systems. Neuvo, Y. s.l. : IEEE International Solid-State Circuits Conference,Digest of Technical Papers, 2004. pp. 32-37.


Power-efficient SoCs (SOC-PE)Its typical application area is electronic equipment categorized as “Mobile Consumer Platforms’”

this application area will make rapid progress in the foreseeable future across semiconductor technology generations.

Very high performance required while the power consumption is strictly limited by the battery (lifetime).

Advanced power consumption reduction techniquesAs a result, the requirement for processing power will be 1000× in the next ten years, while the requirement for dynamic power consumption will not change noticeably. The life cycle of “Mobile Consumer Platform” products is short, and will stay short in the future

The design effort cannot be increased—it needs to stay at the current level for the foreseeable future.

Die-size of around 64 mm2

ITRS 2005, http://www.itrs.net/Links/2005ITRS/SysDrivers2005.pdf10 Ari Kulmala, TUT, 2008

Trends on SoC-Pes #2

ITRS 2005, http://www.itrs.net/Links/2005ITRS/SysDrivers2005.pdf11 Ari Kulmala, TUT, 2008

SoC-PE Design complexity trends


SoC Consumer Stationary (SoC-CS)E.g. a high-end game machine (like PS3)Processing performance is most important differentiator. Required processing performance in year 2020 will be more than 70 TFLOPS.As Functions will be implemented and realized mainly by software, high processing power is required, and hence this SOC needs many dataprocessing engine( DPE ). Comparing with the SOC-PE, has lower performance-per-power than SoC-PE, but better than in terms of functional flexibility in case of adding or modifying functions. The life cycle of those SOC-CS is relatively long, because it is easy to add or modify functions, and as a result the application area is wide. Less processing engines than in SoC-PE but the beasts are mightier in SoC-CSDie-size of around 220 mm2


SoC-CS

ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf

DPE = data processing engine


Power consumption

15

Chip power consumption can be defined asPavg = Pdynamic + Pshort + Pleakage + Pstatic

Traditional view of CMOS transistors is that they do not consumepower while static (Pstatic)

However, in 90nm and below, leakage becomes an increasingly important factor (Pleakage)

A large proportion of power is consumed by dynamic operations and switching (next slide)Pshort = short-circuit power, e.g. when gate switches state, both transistor types are conducting at the same time for some time

~10% of total chip power

Benini: dynamic power managementAri Kulmala, TUT, 2008

Dynamic power consumption

16

K = average number of transitions of the output node every cycle divided by two (e.g. ½ means that there is a single transition each cycle)

Glitches etc

Vdd = Supply voltagef = clock frequencyCout = output capacitanceNote the square-law dependence of Vdd

Typically, higher the f, higher Vdd required

2dynamic out ddP K C V f= ⋅


Soc-CS

ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf

Leakage power will be much more than the calculated value shown in Figure because of variability and temperature effects

Power consumption per a DPE itself will be reduced


SOC-CS POWER CONSUMPTION TRENDS

Different from the SOC-PE, the SOC-CS is generally free from the battery life issue, however rapid power consumption growth has a critical impact on chip packaging issue and cooling issue.

Leakage power will be much more than the calculated value shown in last slide because of variability and temperature effects.

Power consumption per a DPE itself will be reduced because the decreasing factor such as Vdd and insulator dielectric constant become dominant.


Cost of designing a Soc-PE•Blue line: costs nowadays•Purple: cost without the inventions on the design productivity

http://www.itrs.net/Links/2005ITRS/Design2005.pdf19 Ari Kulmala, TUT, 2008


Simplified Electronic Product Development Cost Model


Design development costsManufacturing non-recurring engineering (NRE) costs are on the order of millions of dollars (mask set + probe card) for high-end chipsDesign NRE costs routinely reach tens of millions of dollarsDesign shortfalls being responsible for silicon re-spins that multiply manufacturing NRE. Rapid technology change shortens product life cycles and makes time-to-market a critical issue for semiconductor customers. Manufacturing cycle times are measured in weeks, with low uncertainty. Design and verification cycle times are measured in months or years, with high uncertainty. Software can account for 80% of embedded-systems development costTest cost has grown exponentially relative to manufacturing costVerification engineers outnumber design engineers on microprocessor project teams


ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/02_Design_2006Update.pdf23 Ari Kulmala, TUT, 2008

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ITRS 2005: Interconnect

Delay of global wires does not scale with technology

gate

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global signals with repeaters

global signals


Note on High-end processorsReally, really complex and exotic structuresParallel development projects

Intel has around 400-500 engineers for new CPU architecture projectDevelopment flow (simplistic)

High-level modelingFunctional models with RTLAnalysis of bottlenecks and microarchitectural choices

Don’t forget the market pressure (e.g. compromise performance to get high frequencies)

Implementation of critical blocks in low-level customEven single transistors tweaked, delays very carefully calculated etcVery time consuming, not doable with HDL

Formal methods used in critical partsVery high volume

Speed binning – chips are priced according to their freqeuncy


New architectures: Intel terascale


80 cores (small processors)Interconnected with Mesh network-on-chipStacked chip: local memory problems

IBM/Sony/Toshiba CELL BE


synergistic processor elements (SPE)dual-threaded power processor element (PPE)element interconnect bus (EIB)

1 PowerPC8 SPEs

Moore’s law and more


SiP: Many ICs in a single package

Teaching in DCS


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System design process



Traditional waterfall model just does not work in large designs

Serialized HW-SW development

Time-to-market pressure

=> Parallalize everything possibleHW development (prototypes, emulation)SW developmentVerification (verification environment)HW/SW integration

System development

System development at 2000s


”Spiral flow”

Parallel all the time

Iterations after iterationsInevitable

Physical issues taken into account early

”aina kiire jonnekin on, on, on”

Design and verification cycle interlock

Func. spec

DESING CYCLE DURATION

High-level designDesign implementation

Final physical design

Create ver. plan Evolve verification plan

Implement environmentFrom plan Debug HDL and environment

regression

Plan review checkpoint Tape-out readinesscheckout

Tape out35 Ari Kulmala, TUT, 2008

System Design Process

36

1. System specificationidentify the system requirements (engineering, marketing)formulate the preliminary specification

2. Develop a behavioural modelBasic algorithms, their usability (e.g. good enough video encoding quality)Executable specification, “golden reference”

3. Model refinement and testverification environment for verifying the functionality and performance of the designfloating point model -> fixed-point model -> cycle-accurate and bit-accurate model

4. HW/SW partitioning (decomposition)largely a manual process guided by experience and understanding of tradeoffs (area(cost) vs. performance)define the interfaces between HW and SW, communication protocols


System Design Process (2)

37

4. Specify and develop a hardware architectural modelMemory architectureInterconnection structure, bandwidth, latencyStart from high level models, transaction-level modelingRefine the architecture until it meets the requirements

5. Refine and test architectural model (co-simulation)A behavioural model of the HWA prototype version of the SWKey to success – efficient HW-SW co-design


System Design Process (3)

38

6. Specify implementation blocksHW specification:

Basic functions

Timing, area, and power requirements

Physical and SW interfaces

Descriptions of the I/O pins and register map


System design (4)


Blocks preferable re-usable IP

Blocks implemented as in earlier lectures with re-usable macros

Integrating macros into a SoC


Problems in integrating IP


Interfaces do not work as documentedfor example, some pin is inverted

Misunderstanding of the block’s function

Functional bugs (…)

Someone needs to get familiar with the IP

Documentation is incomplete

Interface of the IP is proprietary (does not match used bus)

Verification models poor (abstract, fast models)

Limited support from IP provider

Examples of integration cost


Integration costs!

The used IP may be lightning fast, but proprietary interface may incur substantial overhead

E.g. Data needs to be fetch somewhereE.g. data permutation

Examples from MPEG-4 Encoder

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Execution time

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Where time is spent?

Area

Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, "IP Integration Overhead Analysis in System-on-Chip Video Encoder", IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2007, Krakow, Poland, April 11-13, 2007, pp. 333-336.

Selecting the IP, criteria


GeneralQuality of the documentationRobustness of design

”Proven in silicon”

For hard macroCompleteness of the design and verification environment

Functional, timing, synthesis, floorplaninng modelsIf CPU, compilers, debuggers

Physical design limitationsAspect ratio, blockage and porosity of the macro (how much it blocks routing)

For soft macroRobustness of verification environment

Rich set of models and monitors for automated stimulus and checkersEase of use

Interfacing the macro to the rest of the designUser-friendly installation and synthesis scripts, tools in general

SystemC

Higher abstraction level language for system modeling


Fundamentals of SystemCSystemC is based on C++Primary goal of SystemC to enable system-level modeling

Systems implemented in SW, HW, or some combination of thoseRequirements for system-level design language

Specification and design at various levels of abstractionFast simulation speed to enable design-space explorationIncorporation of embedded software (SW) codeCreation of executable specification of design intentCreation of executable platform modelsConstructs allowing the separation of computation and communication

Needs to support wide range of models of computation and communication, levels of abstraction, and methodologies used in system design

E.g. DSP problems naturally map to a dataflow or Kahn process network (KPN) models


SystemC (2)Compiles to an .exe (i.e. built-in simulator)

Own debug printf()’s required for feedback

Core language includes:Modules, ports, processes, events, interfaces, channelsEvent-driven simulation kernel

Functional modeling and transaction-level modeling enable hiding “uninteresting” details at early stage of development

Increased simulation speed and faster design space exploration

Not very well supported for synthesisMay lead problems of keeping two separate models up-to-date (SystemC and VHDL of a block)


Summary


Increasingly complex systems need new methodologiesHierarchical, re-usable design style is the current solutionIn future, maybe new design methodologies?Formal verificationExecutable specifications (what goes around comes around)

Divergence to two types of SoCsHigh-performanceLow-power

Several advances and active research required in order to keep on pushing the technology in its limitsParallel processing is the only way to increase performance

New methodologies for SW programmers need to be adaptedCurrently, tool support for parallelization is weak

System design nowadays ”parallel continuous refinement” (Spiral flow)

Documents

TKT-1212 Digitaalijärjestelmien toteutus · 2009-04-06 · TKT-1212 Digitaalijärjestelmien toteutus. Acknowledgements 2 Ari Kulmala, ... N-type cmos transistor channel 4 Ari Kulmala,