At the core of the user experience.™
John BourgoinChairman & CEO
October 30, 2002
Nikkei Embedded Processor Nikkei Embedded Processor Symposium 2002Symposium 2002
At the core of the user experience.TM
3
Changing Forces in Design Decisions
90nm technology changes the rules….
Product lifecycles shrinking faster…..
Rapid processor performance increases coupled with exploding NRE’s
dictate that
programmable devices will take a larger share of the SOC function
These require a change in design approach…
At the core of the user experience.TM
4
DSPs, Specialty Processors
DSPs, Specialty Processors
Options for the SOC Developer
MicroprocessorsMicroprocessors
Dedicated Hardware
Dedicated Hardware
Flexibility, Adaptability, Upgradability
Source: John Hennessy
Pe
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ce, N
RE
, 1/U
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ime
-to-
Mkt
At the core of the user experience.TM
5
Key Questions for Solutions Options
1. Can it perform the application? Performance, power, feature set, etc.
2. Can it meet the cost needs for the market? Combination of NRE, unit, and opportunity costs
3. Can I get it to market early? Or at least early enough
At the core of the user experience.TM
6
Increasingly, Programmable Solutions
are the Answers
Why?
Standard, programmable cores increasingly address all three issues as
performance grows rapidly.
At the core of the user experience.TM
8
Historical Perspective
Pe
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rma
nc
e
Time
Programmable Microprocessor
Performance Needed by Market for a Given Function
Hard-wired Logic or Specialized Processor
PerformanceGap
Time-to-Market Sacrifice
Headroom for Other Functions
At the core of the user experience.TM
9
Cheap Transistors Change the Game
Programmable Microprocessor
Hard-wired Logic or Specialized Processor
PerformanceGap
Time-to-Market Sacrifice
Invest transistors to boost processor performance,
recover time to market.
Pe
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e
Time
At the core of the user experience.TM
10
New Systems Need Performance More features and functions each generation Device convergence adding complexity Greater streaming media content High computational loads High throughput demands High task capacity Real-time deadlines Security issues Quality of service
Meeting these challenges with a programmable solution requires very high performance
Traffic shaping
Load balancing
“Deep” packet processing
Billing and statistics
Stateful firewalls
Interactive video
Wireless games
Wireless local loop
4G
3G
W/CDMA
CDMA-2000
IP over Sonet
IPv6Peer-to-peer
VoP
Internet edge routing
MPLS
QoS
Multi-service processors
AES
IPSec
OC-768
OC-192
802.11a
Artificial intelligence
Voice synthesis
Voice recognition
Virtual reality
Digital TV
HDTV
AAC
3D Audio
RAID
VideoconferencingMultimedia
MPEG4
MPEG2
Video processing
Image processing
Streaming video
JPEG2000
Data compression
Software radio
Vocoding
xDSL
Soft Peripherals
Steerable antenna arrays
Powertrain control
Navigation systems
Telematics
Digital radio
High-realism 3D animation
Games AC-3
MP3
WMA
RSA
Moore’s Law to the rescue
At the core of the user experience.TM
11
Performance per $ Accelerates
0.5 0.81 1.31 2.1 3.4 5.4 8.7 14 22.5 36 58 94150
242
389
625
1005
1615
0
200
400
600
800
1000
1200
1400
1600
1800
0x
500x
1000x
1500x
2000x
2500x
3000x
3500x
Integer performance per dollar increasing at 61% per year
MIP
S p
er $
Imp
rovem
ent S
ince 1990
Source: ITRS & MIPS TechnologiesSource: ITRS & MIPS Technologies
At the core of the user experience.TM
12
Effective Performance Will Increase Even Faster!
Architecture enhancements will boost streaming-media performance even higher
Advanced microarchitecture techniques will: Increase utilization of existing transistors, which boosts
processor throughput and response times Increase processor tolerance to slow memories
Chip multiprocessing will exploit additional levels of parallelism Floating-point performance rising even faster than integer
At the core of the user experience.TM
13
Dedicated Hardware
Dedicated Hardware
DSPs, Specialty Processors
DSPs, Specialty Processors
Options for the System Developer
MicroprocessorsMicroprocessorsMicroprocessorsMicroprocessorsHigh-Performance Microprocessors
High-Performance MicroprocessorsHigh-Performance Microprocessors
High-Performance Microprocessors
High-Performance Microprocessors
High-Performance Microprocessors
High-Performance Microprocessors
High-Performance Microprocessors
High-Performance Augmented
Microprocessors
High-Performance Augmented
Microprocessors
High-Performance Augmented
Microprocessors
High-Performance Augmented
Microprocessors
Flexibility, Adaptability, UpgradabilityPe
rfo
rman
ce, N
RE
, 1/U
nit
$, T
ime
-to-
Mkt
High-Performance Augmented
Microprocessors
High-Performance Augmented
Microprocessors
At the core of the user experience.TM
15
Mask Costs Go Ballistic
$0K
$200K
$400K
$600K
$800K
$1,000K
$1,200K
0.35µ 0.25µ 0.18µ 0.13µ 0.10µ
Process Technology Node
Mas
k C
ost
s p
er S
et
At the core of the user experience.TM
16
2003
NRE Costs Skyrocket
Design Costs
Mask Costs
Mfg. Costs
$0M
$1M
$2M
$3M
$4M
$5M
$6M
$7M
$8M
$9M
$10M
1995(0.35um)
1997(0.25um)
1999(0.18um)
2001(0.13um)
2003(0.10um)
Design
100%
Mfg.(250KU)
Assumptions: 6M → 70M transistors, 3 mask spins, 250K Units, transistor costs and productivity projected from the ITRS
62%
MasksDesign
100%
Masks
Mfg.(250KU)
1995
13%
At the core of the user experience.TM
17
Die Cost Impact of Low Volumes: Total Cost of Production
$53.75
$19.67
$7.99$4.57 $3.38 $3.04
$0.00
$10.00
$20.00
$30.00
$40.00
$50.00
$60.00
100K 300K 1M 3M 10M 30M
Unit Volumes
To
tal C
ost
/Die
Fully Amortized Die Cost
Assumptions: $2M mask charge, 25 wafer min lot size, $3000/300mm wafer, $3M dev cost
At the core of the user experience.TM
18
Programmability Leverages Design Costs Across Multiple Products
Right first time
Simpler designs
More design reuse
Broader applicability
Memory
AFE
10/100Phy
MemoryControl
StdPer
VoicebandAFE
10/100MAC
StandardPeripherals
HardwareAAL
DSL Phy
Security
Vocoders& Fax (DSP)
µPCore
At the core of the user experience.TM
19
Programmability Lowers NRE Lower total mask costs
Software flexibility increases 1st silicon success Reuse of known-good processor cores Product changes without hardware redesign Fewer silicon spins (fewer mask sets)
Lower design costs Less complex SOC designs (vs. alternatives) Greater reuse of hardware blocks (processors) Reuse complete SOC designs in other products and in
upgraded products
At the core of the user experience.TM
21
One MillionUnits
Time-to-Market Is Vital
0 2 4 6 8 10 12 14 16 18 20
Years After Introduction
Sal
es V
olu
me
B&W TVCable TVColor TVVCRPCCellularPCS DVBDVD
The impact of being late to market is becoming more significant
Source: Semico Research
At the core of the user experience.TM
22
The Value of Time-to-MarketTime-to-market is an increasingly large factor
in a product’s total integrated profit
Assumes: 18 month market ramp, 40 month product life, $10M NRE, 50% margins
-20%
0%
20%
40%
60%
80%
100%
120%
0 3 6 9 12 15
Months Late
Pro
fits
At the core of the user experience.TM
23
Time-in-Market Boosts Integrated Profit
Time
Dwell Time in Market
Longer Time at Higher
Profitability
HardwiredSolution
Programmable Solution
Flexibility Extends Time-in-MarketFlexibility Reduces Design Timeand NRER
ev
enu
eC
os
ts
Sooner to Revenue
Profit
NRE
Unit Costs
At the core of the user experience.TM
24
Programmability Speeds Time-to-Market and Extends Time-in-Market
Reduced SOC development time Late binding of product features: start design early, finalize after
tape-out Adaptability to late changing standards Greater design reuse, higher productivity
Extended product lifetime Tweak to match changing market conditions Protection from obsolescence Reuse SOC in derivative products Reuse SOC in adjacent products
At the core of the user experience.™
Apply the falling cost of transistors to lower
the rising costs of development
At the core of the user experience.TM
27
Disappearing Cost of Transistors
0
50
100
150
200
250
300
350
400
450
500
1997 1999 2001* 2003* 2005*
µC
en
ts/t
ran
sis
tor
* Source: ITRS 2001, packaged parts + 60% GPM
-30% / year
At the core of the user experience.TM
28
Strategy for the Future Apply falling transistor costs to
Higher-performance processor cores Enabling more programmable solutions
Giving lower NRE, faster time-to-market Thus lower costs, higher revenues And, increased profits
How? 8 32 64 128-bit architectures Vector processing, data-parallel SIMD ALUs Fine-grain multithreading High-frequency instruction-parallel pipelines Chip multiprocessing (CMP)
At the core of the user experience.™
Processor Performance Increasingly Will Be Applied to Improve NRE
&Time in Market