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Static Timing Analysis

ICSOC

IC

Static Timing Analysis STA

IC IC

IC STA

STA IC

STA

STA Timing Model

Timing Constraint

Path-Based Block-Based

Path-Based A B

4 Y Timing Model

Timing

Constraint

1. A 2AT=2AT Arrival Time

2. B 5AT=5

3. 10 YRT=10RT Required Time

P1 P2 PathP1 A

2 1 2

42+2 P1 Y 72+2+3

Timing Constraint P1

Timing

B Y 115+1+3+2

Timing Constraint P2 Timing

6 Path-Based STA

6 IC

Timing Constraint

STA Signoff EDA PrimeTime Path-Based Path-Based

Block-Based Timing Information

Node Timing Constraint

A AT 2B AT 5 Y RT 10Block-Based

AT RT RT AT

Timing Constrain Timing

STA

STA STA

Design Data Block Model STA

STA

Library Data

STA Timing Model Cell Library

Timing Arc Timing Arc

Combinational Timing ArcSetup Timing Arc

Hold Timing ArcEdge Timing ArcPreset and Clear Timing ArcRecovery Timing

ArcRemoval Timing ArcThree State Enable & Disable Timing ArcWidth Timing

Arc 1458

Combinational Timing Arc Timing ArcTiming Arc

A Z

Combinational Timing Arc Sense inverting negative

unatenon-inverting positive unate non-unate Timing Arc

Z A

0 1 1 0 Timing Arc inverting sense

Timing Arc non-inverting sense

Timing Arc non-unate

Timing Arc

Setup Timing ArcSequential Cell Flip-Flop

Latch Setup Time Clock 2

Hold Timing Arc Hold Time Clock

2

Edge Timing Arc Clock Active Edge

Clock 2

Preset and Clear Timing ArcPreset Clear

Preset Clear

4 Timing Arc

STA

Recovery Timing Arc Clock Active Edge

Clock 2

Removal Timing Arc Clock Active Edge

Clock 2

Three State Enable & Disable Timing Arc Tri-State

Enable Enable Disable 2

Width Timing Arc 0

1 2

Combinational Timing Arc

Transition Time

2

Timing Table STA

Timing Model

STA

Ddelay 1 50% 1 50%

Dtransition 1 20%80% 80%20%

0.5 0.2

I2 0.432

0.25 0.15STA

Timing Arc

Operating Condition

ProcessVoltageTemperature

PVT

nom_processnom_voltage nom_temperature

Interconnect Data

STA

Interconnect Delay DSM IC

P&R

Wireload Model Wireload Model

Fan-outSTA

RC Extraction

Back-annotateSTA

Timing Constraints

Timing Constraint

Clock

Clock Period

Clock Timing Constraint

Clock Latency Uncertainty Clock

Latency Clock

Clock Uncertainty Clock Clock

Flip-Flop

Clock Clock

Flip-Flop Flip-Flop

Clock C1 C2

0Clock Ssource latency

1 Clock

Clock P Clock

Clock C1 C2

P C1 C2

P C1 1

P C2 2 Clock C1

C2 2 13

1 source latency

P C1 C2

network latency Uncertainty

Clock

P Flip-Flop Clock

Clock C1 C2

Flip-Flop

network latency

Clock C1 C2 Latencysource latency +

network latency

Clock P

Flip-Flop Clock

Clock C1 C2

Uncertainty Clock

Uncertainty 1 Clock 3

Latency 3 1 2 4 C1

12 14 C2

Clock Boundary

Condition Boundary Condition

Path STA Path

Path

Path 4

1. Flip-Flop Clock Flip-Flop

2. Primary Input PI Flip-Flop

3. Flip-Flop Clock Primary Output PO

4.

Clock 1 Path Timing Constraint

3 Path Boundary

Condition

Boundary Condition

1. Driving Cell

2. Input Transition Time

3. Output Capacitance Load

4. Input Delay Clock

Delayclk-Q + a

5. Output Delay Clock

c

Boundary Condition 4 Path

1 PathFlip-Flop Flip-Flop Boundary Condition

Clock Path Timing Constraint

Path Timing Constraint

Path Path

Path Path

Timing Exception False Path Multi-cycle Path

STA

STA

Timing Arc Setup TimeHold Time Setup Time

1 STA

Setup Time

Timing ModelTiming

Constraint

3ns 2ns

2ns 1ns

Net 2ns 1ns

Flip-Flop Clock Q 3ns

Flip-Flop Setup Time 1nsTs

Flip-Flop Hold Time 1nsTh

Clock 14nsDclkp

Clock source latency 2nsDclks

Clock network latency 3nsDclkn

Clock uncertainty 1nsDclku

B C input delay 1nsDaDbDc

Y output delay 3nsDY

Step-By-Step

1. Timing Path 3 Timing Path

2. A 0 1 1 Path Arrival

Time AT

3. A 1 0 1 Path AT

4. 1 Path Required Time RT

5. A 0 1 1 Path SlackSlack RT

AT Setup Time RT - AT Hold Time

AT - RT Setup Time Slack

Path Timing

6. A 1 0 1 Path SlackSlack

Timing

5 6 1 Path Timing Slack 4ns

7. Flip-Flop 0 1 2 Path AT


9. 2 Path RT

10. Flip-Flop0 12 PathSlackSlack

Timing


Timing

10 11 2 Path Timing Slack -3

14. 3 Path RT


Timing


Timing

15 16 3 Path Timing Slack -4

Critical Path Path3

Slack -4

STA STA

IC

Static Timing Analysis

IC

SOC IC

Static Timing Analysis STA

IC

IC Static Timing

Analysis

STA STA

32bit x 32bit Pipeline

Pipeline 3

Cell-based

SynthesisP&R

Synopsys Design Compiler

Synopsys Astro

Artisan 0.18um Cell Library

Timing Constraint

SDC

1 Clock Specification

1.1 6ns create_clock -name "MY_CLOCK" -period 6 -waveform {0 3}

[get_ports {clk}]

1.2 Source Latency1ns set_clock_latency -source 1 [get_clocks {MY_CLOCK}]

1.3 Network Latency1ns set_clock_latency 1 [get_clocks {MY_CLOCK}]

1.4 Skew0.5ns set_clock_uncertainty 0.5 [get_clocks {MY_CLOCK}]

2 Boundary Condition

2.1 Input Delay1.2ns set allin_except_CLK [remove_from_collection [all_inputs]

[get_ports clk] ]

set_input_delay $I_DELAY -clock MY_CLOCK $allin_except_CLK

2.2 Output Delay1.2ns set_output_delay $O_DELAY -clock MY_CLOCK [all_outputs]

2.3 Output Loading0.5pF set_load $O_LOAD 0.5 [all_outputs]

3 Timing Exception

Synopsys Design Compiler

report_timing -path full -delay max -max_paths 10 -input_pins \

-nets -transition_time -capacitance > timing_syn.txt

timing_syn.txt

Critical Path

Startpoint: S2/B2_reg_0_

(rising edge-triggered flip-flop clocked by MY_CLOCK)

Endpoint: S3/P3_reg_47_

(rising edge-triggered flip-flop clocked by MY_CLOCK)

Path Group: MY_CLOCK

Path Type: max

Critical Path Flip-Flop 2 Pipeline Stage

B2 0 Flip-Flop 3 Pipeline Stage

P3 47

Critical Path Wire Load Model

UMC18_Conservative Model Model

Interconnect Delay

Critical Path

Point Fanout Cap Trans

Incr Path

-----------------------------------------------------------------

--------------

clock MY_CLOCK (rise edge) 0.00

0.00

clock network delay (ideal) 2.00

2.00

S2/B2_reg_0_/CK (DFFHQX4) 0.00

0.00 2.00r

S2/B2_reg_0_/Q (DFFHQX4) 0.16 0.30

2.30r

S2/n36 (net) 1 0.03 0.00

2.30r

S2/U10/A (BUFX20) 0.16 0.00

2.30r

S2/U10/Y (BUFX20) 0.23 0.21

2.51r

...

...

S3/add_106/U0_5_47/A (XNOR2X2) 0.18

0.00 7.74f

S3/add_106/U0_5_47/Y (XNOR2X2) 0.12

0.22 7.96f

S3/add_106/SUM[47] (net) 1 0.01

0.00 7.96f

S3/add_106/SUM[47] (stage3_DW01_add_54_0)

0.00 7.96f

S3/N94 (net) 0.01

0.00 7.96f

S3/P3_reg_47_/D (DFFTRXL) 0.12 0.00

7.96f

data arrival time

7.96


6.00

clock network delay (ideal)

2.00 8.00

clock uncertainty

-0.50 7.50

S3/P3_reg_47_/CK (DFFTRXL)

0.00 7.50r

library setup time

-0.28 7.22

data required time

7.22

-----------------------------------------------------------------

---------------

data required time

7.22

data arrival time

-7.96

-----------------------------------------------------------------

---------------

slack (VIOLATED)

-0.74

Point

Net Fanout

Cap Trans

Transition Time Incr

Path

Critical Path

clock network delay (ideal)

2.00 2.00

2ns clock network delay

1ns source latency network latency 2ns

S2/B2_reg_0_/CK (DFFHQX4) 0.00

0.00 2.00 r

Critical Path S2 Instance B2_reg_0_ instance

CK 2ns network delay

2ns 0ns Transition Time

0ns Transition Time

r Flip-Flop r f

S2/B2_reg_0_/Q (DFFHQX4) 0.16

0.30 2.30 r

Flip-Flop CK

Q 0.3ns Transition Time 0.16ns

2+0.3=2.3ns r Q

0 1 1 0

fCell LibraryTiming

TableStatic Timing Analysis

S2/n36 (net) 1 0.03

0.00 2.30 r

S2/U10/A (BUFX20) 0.16 0.00

2.30 r

Path

Flip-Flop Q

BufferAInterconnect

Delay Design Compiler

Cell Dealy

Point net

Fanout Cap S2/n36 net Buffer Fanout 1

Buffer 0.03pF

S2/U10/Y (BUFX20) 0.23

0.21 2.51 r

Buffer 0.21

Buffer 2.3+0.21=2.51ns

S3/add_106/U0_5_47/A (XNOR2X2) 0.18

0.00 7.74 f

S3/add_106/U0_5_47/Y (XNOR2X2) 0.12

0.22 7.96 f

Critical Path 7.96ns

f 1 0

S3/add_106/SUM[47] (net) 1 0.01

0.00 7.96 f

S3/add_106/SUM[47] (stage3_DW01_add_54_0)

0.00 7.96 f

S3/N94 (net) 0.01

0.00 7.96 f

S3/P3_reg_47_/D (DFFTRXL) 0.12 0.00

7.96 f

data arrival time

7.96

Logic Hierarchy

Critical Path 7.96ns Arrival Time

AT Required TimeRT


6.00

clock network delay (ideal) 2.00

8.00

clock uncertainty -0.50

7.50

S3/P3_reg_47_/CK (DFFTRXL) 0.00

7.50 r

library setup time -0.28

7.22

data required time

7.22

Critical Path Flip-Flop 2ns network delay

1 6ns 6+2=8ns

Required TimeRT 8ns 0.5ns

clock uncertainty 0.5ns RT

8-0.5=7.5ns Setup Time 0.28ns RT

7.5-0.28=7.22ns

data required time

7.22

data arrival time

-7.96

---------------------------------------------------------------------

-----------

slack (VIOLATED)

-0.74

RT AT slack slack

STA

Interconnect Delay

Wire Load Model Astro

Virtual RouteVRVR

Astro VR

Critical Path

* Start point : S3.B3_reg_4_/CK

* ( Rising edge-triggered flipflop clocked by MY_CLOCK )

* End point : S4.out_reg_63_/D

* ( Rising edge-triggered flipflop clocked by MY_CLOCK at CK )

* Clock Group : MY_CLOCK

* Delay Type : Max

* Slack : -1.0682 (VIOLATED)

Critical Path

Critical Path

Port/Pin

Cap Fanout Trans. Incr Arri Master/Net

-----------------------------------------------------------------

----------------

Rising edge of clock MY_CLOCK 0.0000 0.0000

Clock Source delay 1.0000 1.0000

Clock Network delay 1.0000 2.0000

-----------------------------------------------------------------

----------------

S3.B3_reg_4_/CK

0.0000 0.0000 2.0000 r DFFTRX4

S3.B3_reg_4_/Q

0.1501 15 0.5663 0.5307 2.5307 r B3[4]

S4.mult_123.B3_reg_4_ASTipoInst106/A

0.5839 0.0294 2.5602 r BUFX1

S4.mult_123.B3_reg_4_ASTipoInst106/Y

0.0231 5 0.3842 0.3252 2.8853 r

S4.mult_123.B3_4_ASThfnNet53

...

...

S4.add_133.U155/A

0.3328 0.0006 8.0590 f XNOR2X2

S4.add_133.U155/Y

0.0030 1 0.0894 0.2341 8.2931 f S4.N109

S4.out_reg_63_/D

0.0895 0.0001 8.2932 f DFFTRXL

-----------------------------------------------------------------

----------------



Clock Network delay 1.0000 8.0000

Clock Skew 0.5000 7.5000

Setup time 0.2749 7.2251

-----------------------------------------------------------------

----------------

Required time 7.2251

Arrival time 8.2932

-----------------------------------------------------------------

----------------

Slack -1.0682 (VIOLATED)

Point

Port/Pin Master/Net Critical

Path S3.B3_reg_4_ CK

2nsSource Latency + Network Latency

S3.B3_reg_4_ Q 0.5307ns 2.5307ns

S4.mult_123.B3_reg_4_ASTipoInst106

A

0.0294ns 2.5602ns

Net Name Net

Net

slack

VR VR VR VR

* Start point : S2.A2_reg_9_/CK

* ( Rising edge-triggered flipflop clocked by MY_CLOCK )

* End point : S3.P3_reg_32_/D

* ( Rising edge-triggered flipflop clocked by MY_CLOCK at CK )

* Clock Group : MY_CLOCK

* Delay Type : Max

* Slack : -0.2721 (VIOLATED)

*****************************************************************

****************

Port/Pin Cap Fanout Trans. Incr Arri

Master/Net

-----------------------------------------------------------------

----------------



Clock Network delay (propagated) 0.9998 1.9998

-----------------------------------------------------------------

----------------

S2.A2_reg_9_/CK 0.1451 0.0000 1.9998 r

DFFHQX4

S2.A2_reg_9_/Q 0.0278 1 0.1576 0.3282 2.3280 r

A2[9]

...

S3.P3_reg_32_/D 0.1001 0.0002 8.0062 f

DFFTRXL

-----------------------------------------------------------------

----------------



Clock Network delay (propagated) 0.9854 7.9854

Clock Skew 0.0000 7.9854

Setup time 0.2513 7.7341

-----------------------------------------------------------------

----------------

Required time 7.7341

Arrival time 8.0062

-----------------------------------------------------------------

----------------

Slack -0.2721

(VIOLATED)

Critical Path

Clock Tree

Critical Path Flip-Flop Clock Network

DelayLatency 0.9998ns 1ns Flip-Flop

Clock Network DelayLatency 0.9854ns 0.5ns Clock Skew

slack -0.2721

slack

STA IC

STA (/)