2009.03 _TI-DSP簡報_slide_share

TMS320介紹與應用

2009/3/18

p.20-1

TMS 320F2812介紹與應用

報告人 : Harry


2009/3/18

p.20-2

控制器架構

TMS320 於控制器之應用

TMS320 軟/硬體架構

實作範例程式架構

實作範例展示

大綱


2009/3/18

p.20-3

控制器架構

A1-CPU卡 A2-介面卡 A3-伺服卡

ROM(32k)

x2

54373 x2

CPLD x3

( Encoder )

54245 x2

80196

RAM(1k)

x2

CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,

pull-high … device D/A x2

OP

( rate loop PID )

OP

( notch filter )


2009/3/18

p.20-4



54373 x2

CPLD x3

( Encoder )

54245 x2

80196

CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,


OP

( rate loop PID )

OP

( notch filter )

data/address bus

ROM(32k)

x2

RAM(1k)

x2


2009/3/18

p.20-5

data/address bus

可供外部IO / 記憶體擴充使用

(≦1.5M )

ex: *(unsigned int*)(0x2009) = 0x01 ;


2009/3/18

p.20-6



ROM x2

54373 x2

CPLD x3

( Encoder )

54245 x2

80196

RAM x2 CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,


OP

( rate loop PID )

OP

( notch filter )

data/address bus

On-chip

RAM / Flash


2009/3/18

p.20-7

On-chip RAM / Flash

2k

8k

128k 8k

4k


2009/3/18

p.20-8

記憶體配置( .cmd 檔 ) MEMORY

{

PAGE 0:

FLSH_USR1 : origin = 0x3F6000, length = 0x001FF6 /* on-chip FLASH free */

BEGIN : origin = 0x3F7FF6, length = 0x000002 /* on-chip FLASH - entry point */

FLSH_MON : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH used by monitor*/

RAMH0_MON : origin = 0x3f8000, length = 0x000080 /* on-chip RAM H0 used by monitor */

RAMH0 : origin = 0x3F8080, length = 0x001F80 /* on-chip RAM H0 free */

/* This memory block loaded with the reset vector only if

booting from XINTF Zone 7. Otherwise reset vector is

fetched from boot ROM. See .reset section below */

RESET : origin = 0x3FFFC0, length = 0x000002

PAGE 1:

FLSH_USR2 : origin = 0x3D8000, length = 0x01C000 /* on-chip FLASH free */

RAML0_MON : origin = 0x008000, length = 0x000300 /* on-chip RAM L0 used by monitor */

RAML0 : origin = 0x008300, length = 0x000D00 /* on-chip RAM L0 free */

RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM L1 free */

RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM M0 free */

RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM M1 free */

EXTMEM : origin = 0x100000, length = 0x040000 /* external RAM memory free */

.................

}

SECTIONS

{

codestart : > BEGIN, PAGE = 0

.text : > FLSH_USR1, PAGE = 0

.cinit : > FLSH_USR1, PAGE = 0

.switch : > FLSH_USR1, PAGE = 0

.data : > FLSH_USR1, PAGE = 0

.................

}


2009/3/18

p.20-9



ROM x2

54373 x2

CPLD x3

( Encoder )

54245 x2

80196

RAM x2 CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,


OP

( rate loop PID )

OP

( notch filter )

data/address bus

On-chip

RAM / Flash

CAN module

GPIO

2.0B

≦56 channels


2009/3/18

p.20-10

45 PI

to p.20-18


2009/3/18

p.20-11



ROM x2

54373 x2

CPLD x3

( Encoder )

54245 x2

80196

RAM x2 CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,


OP

( rate loop PID )

OP

( notch filter )

data/address bus

On-chip

RAM / Flash

CAN module

GPIO

digital

controller


2009/3/18

p.20-12

Digital controller

150 M (核心1.9V)

135 M (核心1.8V) 14 M ( 80196 )


2009/3/18

p.20-13



ROM x2

54373 x2

CPLD x3

( Encoder )

54245 x2

80196

RAM x2 CPLD x2

( Status )

CPLD x2

( CAN )

CPLD ( Decoder )

analog , driver ,

pull-high … device

OP

( rate loop PID )

OP

( notch filter )

TMS 320 F2812

3.3 V 5V

D/A x2


2009/3/18

p.20-14

2k

8k

128k

8k

4k

TMS320

軟/硬體

架構

•支援32 x 32 bit乘加運算

•高性能CMOS技術

•低功率核心1.9V下

150MHz

•3.3V 燒錄Flash

•市場需求量大

品質穩定不會有停產問題


2009/3/18

p.20-15

車規 1100 NTD( min order 40EA )

市場( 特性 / 量 )市值?

市場 :

C2000 馬達控制

C5000 數位相機

C6000 智慧手機

TI

2007營收 138.35億USD

DSP 50.7億USD


2009/3/18

p.20-16

TMS320

軟/硬體

架構


2009/3/18

p.20-17

Xint( ) : 計數按鍵被按下次數並顯示於LED

Timer( ) : 計算目標位置與載具位置間之誤差

並將命令輸出至D/A

Main( ) : 顯示encoder角度於LCD上

實作範例程式架構


2009/3/18

p.20-18

中斷程式撰寫流程

to p.20-10 3. PieCtrlRegs.PIEIER2.all = M_INT4;

// 以M_INT2設定致能PIE群2的D4位元中斷T1PINT

4. IER |= M_INT2 ; //致能CPU中斷

5. EINT; // 致能中斷總開關 INTM

ERTM; // Enable Global realtime interrupt DBGM

1. DINT; // 除能所有中斷

IER = 0x0000; // 除能所有CPU中斷

IFR = 0x0000; // 除能所有CPU中斷旗號

2. EvaRegs.T1PR =0x800;//設定timer週期

EvaRegs.EVAIMRA.bit.T1PINT = 1; //致能timer中斷

EvaRegs.EVAIFRA.bit.T1PINT = 1; //清除timer中斷旗號

EvaRegs.T1CON.all = 0x1742;

//上數計時,預除128,使用內部時脈...等


2009/3/18

p.20-19

實作範例展示


2009/3/18

p.20-20

報告完畢

謝謝聆聽

Technology

2009.03 _TI-DSP簡報_slide_share